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CodeScopeDevelopment ToolsOpenOCDdebug_level

debug_level variable

Syntax

extern int debug_level;
Implemented in log.c:35

References

LocationReferrerText
log.c:35
int debug_level = LOG_LVL_INFO;
log.h:94
extern int debug_level;
FLASHPlugin.c:157loaded_plugin_load()
LOG_DEBUG("FLASH plugin: placing the stack at 0x%08x-0x%08x", lastSectionEnd, lastSectionEnd + stackSize);
FreeRTOS.c:158freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %" PRIu32,
FreeRTOS.c:180freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read pxCurrentTCB at 0x%" PRIx64 ", value 0x%" PRIx64,
FreeRTOS.c:193freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read xSchedulerRunning at 0x%" PRIx64 ", value 0x%" PRIx32,
FreeRTOS.c:242freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu32,
FreeRTOS.c:290freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRIu32,
FreeRTOS.c:307freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx32,
FreeRTOS.c:323freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read Thread ID at 0x%" PRIx32 ", value 0x%" PRIx64,
FreeRTOS.c:343freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read Thread Name at 0x%" PRIx64 ", value '%s'",
FreeRTOS.c:378freertos_update_threads()
LOG_DEBUG("FreeRTOS: Read next thread location at 0x%" PRIx32 ", value 0x%" PRIx32,
FreeRTOS.c:416freertos_get_thread_reg_list()
LOG_DEBUG("FreeRTOS: Read stack pointer at 0x%" PRIx64 ", value 0x%" PRIx64,
ThreadX.c:244get_stacking_info_arm926ejs()
LOG_DEBUG(" solicited stack");
ThreadX.c:247get_stacking_info_arm926ejs()
LOG_DEBUG(" interrupt stack: %" PRIu32, flag);
aarch64.c:184aarch64_mmu_modify()
LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
aarch64.c:212aarch64_init_debug_access()
LOG_DEBUG("%s", target_name(target));
aarch64.c:217aarch64_init_debug_access()
LOG_DEBUG("Examine %s failed", "oslock");
aarch64.c:324aarch64_wait_halt_one()
LOG_DEBUG("target %s timeout, prsr=0x%08"PRIx32, target_name(target), prsr);
aarch64.c:337aarch64_prepare_halt_smp()
LOG_DEBUG("target %s exc %i", target_name(target), exc_target);
aarch64.c:360aarch64_prepare_halt_smp()
LOG_DEBUG("target %s prepared", target_name(curr));
aarch64.c:381aarch64_halt_one()
LOG_DEBUG("%s", target_name(target));
aarch64.c:480update_halt_gdb()
LOG_DEBUG("Halting remaining targets in SMP group");
aarch64.c:537aarch64_poll()
LOG_DEBUG("Target %s halted", target_name(target));
aarch64.c:586aarch64_restore_one()
LOG_DEBUG("%s", target_name(target));
aarch64.c:619aarch64_restore_one()
LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
aarch64.c:645aarch64_prepare_restart_one()
LOG_DEBUG("%s", target_name(target));
aarch64.c:690aarch64_do_restart_one()
LOG_DEBUG("%s", target_name(target));
aarch64.c:731aarch64_restart_one()
LOG_DEBUG("%s", target_name(target));
aarch64.c:787aarch64_step_restart_smp()
LOG_DEBUG("%s", target_name(target));
aarch64.c:796aarch64_step_restart_smp()
LOG_DEBUG("error restarting target %s", target_name(first));
aarch64.c:949aarch64_resume()
LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
aarch64.c:953aarch64_resume()
LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
aarch64.c:979aarch64_debug_entry()
LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), dscr);
aarch64.c:1080aarch64_post_debug_entry()
LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
aarch64.c:1150aarch64_step()
LOG_DEBUG("Restarted all non-stepping targets in SMP group");
aarch64.c:1161aarch64_step()
LOG_DEBUG("target step-resumed at 0x%" PRIx64, address);
aarch64.c:1223aarch64_restore_context()
LOG_DEBUG("%s", target_name(target));
aarch64.c:1295aarch64_set_breakpoint()
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
aarch64.c:1357aarch64_set_breakpoint()
LOG_DEBUG("Failed to set DSCR.HDE");
aarch64.c:1407aarch64_set_context_breakpoint()
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
aarch64.c:1437aarch64_set_hybrid_breakpoint()
LOG_DEBUG("brp(CTX) found num: %d", brp_1);
aarch64.c:1447aarch64_set_hybrid_breakpoint()
LOG_DEBUG("brp(IVA) found num: %d", brp_2);
aarch64.c:1518aarch64_unset_breakpoint()
LOG_DEBUG("Invalid BRP number in breakpoint");
aarch64.c:1521aarch64_unset_breakpoint()
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
aarch64.c:1542aarch64_unset_breakpoint()
LOG_DEBUG("Invalid BRP number in breakpoint");
aarch64.c:1545aarch64_unset_breakpoint()
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_j,
aarch64.c:1573aarch64_unset_breakpoint()
LOG_DEBUG("Invalid BRP number in breakpoint");
aarch64.c:1576aarch64_unset_breakpoint()
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_i,
aarch64.c:1771aarch64_set_watchpoint()
LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, wp_i,
aarch64.c:1777aarch64_set_watchpoint()
LOG_DEBUG("Failed to set DSCR.HDE");
aarch64.c:1803aarch64_unset_watchpoint()
LOG_DEBUG("Invalid WP number in watchpoint");
aarch64.c:1806aarch64_unset_watchpoint()
LOG_DEBUG("rwp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, wp_i,
aarch64.c:1904aarch64_enable_reset_catch()
LOG_DEBUG("EDECR = 0x%08" PRIx32 ", enable=%d", edecr, enable);
aarch64.c:1931aarch64_clear_reset_catch()
LOG_DEBUG("Reset Catch debug event %s",
aarch64.c:1952aarch64_assert_reset()
LOG_DEBUG(" ");
aarch64.c:2012aarch64_deassert_reset()
LOG_DEBUG(" ");
aarch64.c:2418aarch64_read_cpu_memory()
LOG_DEBUG("Reading CPU memory address 0x%016" PRIx64 " size %" PRIu32 " count %" PRIu32,
aarch64.c:2665aarch64_examine_first()
LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
aarch64.c:2673aarch64_examine_first()
LOG_DEBUG("Examine %s failed", "oslock");
aarch64.c:2680aarch64_examine_first()
LOG_DEBUG("Examine %s failed", "CPUID");
aarch64.c:2689aarch64_examine_first()
LOG_DEBUG("Examine %s failed", "Memory Model Type");
aarch64.c:2697aarch64_examine_first()
LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
aarch64.c:2712aarch64_examine_first()
LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
aarch64.c:2713aarch64_examine_first()
LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
aarch64.c:2714aarch64_examine_first()
LOG_DEBUG("debug = 0x%08" PRIx64, debug);
aarch64.c:2755aarch64_examine_first()
LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
adapter.c:214adapter_khz_to_speed()
LOG_DEBUG("convert khz to adapter specific speed value");
adapter.c:218adapter_khz_to_speed()
LOG_DEBUG("have adapter set up");
adapter.c:235adapter_rclk_to_speed()
LOG_DEBUG("trying fallback speed...");
adapter.c:250adapter_config_khz()
LOG_DEBUG("handle adapter khz");
adapter.c:259adapter_config_rclk()
LOG_DEBUG("handle adapter rclk");
adapter.c:948adapter_gpio_config_handler()
LOG_DEBUG("Processing %s", CMD_ARGV[i]);
adapter.c:961adapter_gpio_config_handler()
LOG_DEBUG("-chip arg is %s", CMD_ARGV[i + 1]);
adi_v5_dapdirect.c:33dapdirect_jtag_empty_command()
LOG_DEBUG("dapdirect_jtag_empty_command(\"%s\")", CMD_NAME);
adi_v5_dapdirect.c:180dapdirect_jtag_select()
LOG_DEBUG("dapdirect_jtag_select()");
adi_v5_dapdirect.c:187dapdirect_swd_select()
LOG_DEBUG("dapdirect_swd_select()");
adi_v5_dapdirect.c:196dapdirect_init()
LOG_DEBUG("dapdirect_init()");
adi_v5_jtag.c:364adi_jtag_dp_scan_u32()
LOG_DEBUG_IO("DP BANK SELECT: %" PRIx32, (uint32_t)sel);
adi_v5_jtag.c:617jtagdp_overrun_check()
LOG_DEBUG("DAP transaction stalled during replay (WAIT) - resending");
adi_v5_jtag.c:671jtagdp_transaction_endcheck()
LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
adi_v5_jtag.c:684jtagdp_transaction_endcheck()
LOG_DEBUG("JTAG-DP STICKY OVERRUN");
adi_v5_jtag.c:798jtag_ap_q_bankselect()
LOG_DEBUG_IO("AP BANK SELECT: %" PRIx32, (uint32_t)sel);
adi_v5_jtag.c:808jtag_ap_q_bankselect()
LOG_DEBUG_IO("AP BANK SELECT1: %" PRIx32, (uint32_t)(sel >> 32));
adi_v5_swd.c:116swd_queue_dp_bankselect()
LOG_DEBUG_IO("DP BANK SELECT: %" PRIx32, sel);
adi_v5_swd.c:251swd_multidrop_select_inner()
LOG_DEBUG_IO("Selected DP_TARGETSEL 0x%08" PRIx32, dap->multidrop_targetsel);
adi_v5_swd.c:287swd_multidrop_select()
LOG_DEBUG("Failed to select multidrop %s, retrying...",
adi_v5_swd.c:552swd_queue_ap_bankselect()
LOG_DEBUG_IO("AP BANK SELECT: %" PRIx32, (uint32_t)sel);
adi_v5_swd.c:560swd_queue_ap_bankselect()
LOG_DEBUG_IO("AP BANK SELECT1: %" PRIx32, (uint32_t)(sel >> 32));
adi_v5_swd.c:741swd_select()
LOG_DEBUG("no SWD driver?");
adi_v5_swd.c:747swd_select()
LOG_DEBUG("can't init SWD driver");
aduc702x.c:78aduc702x_erase()
LOG_DEBUG("performing mass erase.");
aduc702x.c:89aduc702x_erase()
LOG_DEBUG("mass erase successful.");
aduc702x.c:107aduc702x_erase()
LOG_DEBUG("erased sector at address 0x%08lX", adr);
aduc702x.c:297aduc702x_write_single()
LOG_DEBUG("wrote %d bytes at address 0x%08lX", (int)count, (unsigned long)(offset + x));
aducm302x.c:137aducm302x_probe()
LOG_DEBUG("bank=%p", bank);
aducm302x.c:240aducm302x_erase()
LOG_DEBUG("bank=%p first=%d last = %d", bank, first, last);
aducm302x.c:304aducm302x_protect()
LOG_DEBUG("WRPROT 0x%"PRIx32, wrprot);
aducm302x.c:355aducm302x_write_block()
LOG_DEBUG("bank=%p buffer=%p offset=%08"PRIx32" dwcount=%"PRIx32,
aducm302x.c:365aducm302x_write_block()
LOG_DEBUG("no working area for block memory writes");
aducm302x.c:384aducm302x_write_block()
LOG_DEBUG("retry target_alloc_working_area(%s, size=%"PRIu32")",
aducm302x.c:443aducm302x_write()
LOG_DEBUG("bank=%p buffer=%p offset=%08"PRIx32" count=%"PRIx32,
aducm302x.c:476aducm302x_write()
LOG_DEBUG("writing flash word-at-a-time");
aducm360.c:207aducm360_write_block_sync()
LOG_DEBUG("'aducm360_write_block_sync' requested, dst:0x%08" PRIx32 ", count:0x%08" PRIx32 "bytes.",
aducm360.c:329aducm360_write_block_async()
LOG_DEBUG("'aducm360_write_block_async' requested, dst:0x%08" PRIx32 ", count:0x%08" PRIx32 "bytes.",
aducm360.c:447aducm360_write_modified()
LOG_DEBUG("performing slow write (offset=0x%08" PRIx32 ", count=0x%08" PRIx32 ")...",
ambiqmicro.c:185ambiqmicro_read_part_info()
LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
ambiqmicro.c:233ambiqmicro_read_part_info()
LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro.c:271check_flash_status()
LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
ambiqmicro.c:312ambiqmicro_exec_command()
LOG_DEBUG("state = %d", target->state);
ambiqmicro.c:588ambiqmicro_write_block()
LOG_DEBUG("address = 0x%08" PRIx32, address);
arc.c:64arc_reg_data_type_add()
LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
arc.c:107arc_reset_caches_states()
LOG_DEBUG("Resetting internal variables of caches states");
arc.c:208arc_reg_add()
LOG_DEBUG(
arc.c:230arc_get_register()
LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
arc.c:241arc_get_register()
CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
arc.c:244arc_get_register()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, desc->arch_num,
arc.c:258arc_get_register()
LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
arc.c:284arc_set_register()
LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
arc.c:376arc_build_reg_cache()
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
arc.c:378arc_build_reg_cache()
LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
arc.c:391arc_build_reg_cache()
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
arc.c:393arc_build_reg_cache()
LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
arc.c:467arc_build_bcr_reg_cache()
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
arc.c:472arc_build_bcr_reg_cache()
LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
arc.c:524arc_get_gdb_reg_list()
LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
arc.c:542arc_get_gdb_reg_list()
LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
arc.c:554arc_reg_get_field()
LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
arc.c:585arc_reg_get_field()
CHECK_RETVAL(reg->type->get(reg));
arc.c:600arc_get_register_value()
LOG_DEBUG("reg_name=%s", reg_name);
arc.c:608arc_get_register_value()
CHECK_RETVAL(reg->type->get(reg));
arc.c:618arc_set_register_value()
LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
arc.c:632arc_set_register_value()
CHECK_RETVAL(reg->type->set(reg, value_buf));
arc.c:643arc_configure_dccm()
CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "version",
arc.c:645arc_configure_dccm()
CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size0",
arc.c:647arc_configure_dccm()
CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size1",
arc.c:652arc_configure_dccm()
CHECK_RETVAL(arc_get_register_value(target, "aux_dccm", &(arc->dccm_start)));
arc.c:658arc_configure_dccm()
LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc.c:675arc_configure_iccm()
CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "version",
arc.c:677arc_configure_iccm()
CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size0",
arc.c:679arc_configure_iccm()
CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size1",
arc.c:682arc_configure_iccm()
CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
arc.c:690arc_configure_iccm()
LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc.c:696arc_configure_iccm()
CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size0",
arc.c:698arc_configure_iccm()
CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size1",
arc.c:703arc_configure_iccm()
CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
arc.c:710arc_configure_iccm()
LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc.c:719arc_configure()
LOG_DEBUG("Configuring ARC ICCM and DCCM");
arc.c:724arc_configure()
CHECK_RETVAL(arc_configure_dccm(target));
arc.c:729arc_configure()
CHECK_RETVAL(arc_configure_iccm(target));
arc.c:740arc_examine()
CHECK_RETVAL(arc_jtag_startup(&arc->jtag_info));
arc.c:743arc_examine()
CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
arc.c:750arc_examine()
CHECK_RETVAL(arc_configure(target));
arc.c:764arc_exit_debug()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
arc.c:766arc_exit_debug()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
arc.c:770arc_exit_debug()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
arc.c:772arc_exit_debug()
if (debug_level >= LOG_LVL_DEBUG) {
arc.c:773arc_exit_debug()
LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
arc.c:774arc_exit_debug()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
arc.c:775arc_exit_debug()
LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
arc.c:786arc_halt()
LOG_DEBUG("target->state: %s", target_state_name(target));
arc.c:789arc_halt()
LOG_DEBUG("target was already halted");
arc.c:809arc_halt()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
arc.c:811arc_halt()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
arc.c:815arc_halt()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &irq_state));
arc.c:824arc_halt()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
arc.c:827arc_halt()
if (debug_level >= LOG_LVL_DEBUG) {
arc.c:828arc_halt()
LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
arc.c:829arc_halt()
CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
arc.c:830arc_halt()
LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
arc.c:849arc_save_context()
LOG_DEBUG("Saving aux and core registers values");
arc.c:919arc_save_context()
LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
arc.c:934arc_save_context()
LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
arc.c:965get_current_actionpoint()
CHECK_RETVAL(arc_reg_get_field(target, "debug", "ah",
arc.c:972get_current_actionpoint()
CHECK_RETVAL(arc_reg_get_field(target, "debug",
arc.c:1000arc_examine_debug_reason()
CHECK_RETVAL(arc_reg_get_field(target, "debug", "bh",
arc.c:1008arc_examine_debug_reason()
CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
arc.c:1028arc_debug_entry()
CHECK_RETVAL(arc_save_context(target));
arc.c:1032arc_debug_entry()
CHECK_RETVAL(arc_reset_caches_states(target));
arc.c:1033arc_debug_entry()
CHECK_RETVAL(arc_examine_debug_reason(target));
arc.c:1044arc_poll()
CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
arc.c:1058arc_poll()
CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
arc.c:1060arc_poll()
LOG_DEBUG("ARC core in halt or reset state.");
arc.c:1063arc_poll()
CHECK_RETVAL(arc_debug_entry(target));
arc.c:1065arc_poll()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
arc.c:1067arc_poll()
LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
arc.c:1074arc_poll()
LOG_DEBUG("ARC core is in debug running mode");
arc.c:1076arc_poll()
CHECK_RETVAL(arc_debug_entry(target));
arc.c:1078arc_poll()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED));
arc.c:1090arc_assert_reset()
LOG_DEBUG("target->state: %s", target_state_name(target));
arc.c:1104arc_assert_reset()
LOG_DEBUG("Starting CPU execution after reset");
arc.c:1105arc_assert_reset()
CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
arc.c:1134arc_assert_reset()
CHECK_RETVAL(target_halt(target));
arc.c:1141arc_deassert_reset()
LOG_DEBUG("target->state: %s", target_state_name(target));
arc.c:1153arc_arch_state()
if (debug_level < LOG_LVL_DEBUG)
arc.c:1156arc_arch_state()
CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
arc.c:1158arc_arch_state()
LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32,
arc.c:1177arc_restore_context()
LOG_DEBUG("Restoring registers values");
arc.c:1204arc_restore_context()
LOG_DEBUG("Will write regnum=%u", i);
arc.c:1215arc_restore_context()
LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
arc.c:1257arc_enable_interrupts()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
arc.c:1262arc_enable_interrupts()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
arc.c:1263arc_enable_interrupts()
LOG_DEBUG("interrupts enabled");
arc.c:1267arc_enable_interrupts()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
arc.c:1268arc_enable_interrupts()
LOG_DEBUG("interrupts disabled");
arc.c:1282arc_resume()
LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
arc.c:1288arc_resume()
CHECK_RETVAL(arc_reset_caches_states(target));
arc.c:1298arc_resume()
CHECK_RETVAL(arc_enable_breakpoints(target));
arc.c:1299arc_resume()
CHECK_RETVAL(arc_enable_watchpoints(target));
arc.c:1307arc_resume()
LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
arc.c:1315arc_resume()
CHECK_RETVAL(arc_restore_context(target));
arc.c:1317arc_resume()
LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
arc.c:1323arc_resume()
LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
arc.c:1324arc_resume()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
arc.c:1332arc_resume()
LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
arc.c:1334arc_resume()
CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
arc.c:1335arc_resume()
CHECK_RETVAL(arc_single_step_core(target));
arc.c:1336arc_resume()
CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
arc.c:1342arc_resume()
CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
arc.c:1344arc_resume()
CHECK_RETVAL(arc_enable_interrupts(target, !debug_execution));
arc.c:1350arc_resume()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
arc.c:1352arc_resume()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
arc.c:1353arc_resume()
LOG_DEBUG("Core started to run");
arc.c:1360arc_resume()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
arc.c:1361arc_resume()
LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
arc.c:1364arc_resume()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
arc.c:1365arc_resume()
LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
arc.c:1373arc_init_target()
CHECK_RETVAL(arc_build_reg_cache(target));
arc.c:1374arc_init_target()
CHECK_RETVAL(arc_build_bcr_reg_cache(target));
arc.c:1389arc_deinit_target()
LOG_DEBUG("deinitialization of target");
arc.c:1438arc_target_create()
LOG_DEBUG("Entering");
arc.c:1439arc_target_create()
CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
arc.c:1459arc_write_instruction_u32()
LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
arc.c:1467arc_write_instruction_u32()
CHECK_RETVAL(target_write_buffer(target, address, 4, value_buf));
arc.c:1488arc_read_instruction_u32()
CHECK_RETVAL(target_read_buffer(target, address, 4, value_buf));
arc.c:1495arc_read_instruction_u32()
LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
arc.c:1529arc_configure_actionpoint()
CHECK_RETVAL(arc_set_register_value(target, ap_amv_reg_name,
arc.c:1531arc_configure_actionpoint()
CHECK_RETVAL(arc_set_register_value(target, ap_amm_reg_name, 0));
arc.c:1532arc_configure_actionpoint()
CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
arc.c:1538arc_configure_actionpoint()
CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
arc.c:1555arc_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
arc.c:1560arc_set_breakpoint()
CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
arc.c:1563arc_set_breakpoint()
CHECK_RETVAL(arc_write_instruction_u32(target, breakpoint->address,
arc.c:1566arc_set_breakpoint()
CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
arc.c:1576arc_set_breakpoint()
CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
arc.c:1578arc_set_breakpoint()
CHECK_RETVAL(target_write_u16(target, breakpoint->address, ARC_SDBBP_16));
arc.c:1580arc_set_breakpoint()
CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
arc.c:1617arc_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
arc.c:1622arc_set_breakpoint()
LOG_DEBUG("ERROR: setting unknown breakpoint type");
arc.c:1641arc_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
arc.c:1646arc_unset_breakpoint()
CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &current_instr));
arc.c:1663arc_unset_breakpoint()
CHECK_RETVAL(target_read_u16(target, breakpoint->address, &current_instr));
arc.c:1687arc_unset_breakpoint()
LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
arc.c:1700arc_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
arc.c:1704arc_unset_breakpoint()
LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
arc.c:1718arc_enable_breakpoints()
CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
arc.c:1741arc_remove_breakpoint()
CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
arc.c:1778arc_set_actionpoints_num()
LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
arc.c:1920arc_set_watchpoint()
LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
arc.c:1941arc_unset_watchpoint()
LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
arc.c:1954arc_unset_watchpoint()
LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
arc.c:1968arc_enable_watchpoints()
CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
arc.c:1983arc_add_watchpoint()
CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
arc.c:1997arc_remove_watchpoint()
CHECK_RETVAL(arc_unset_watchpoint(target, watchpoint));
arc.c:2008arc_hit_watchpoint()
CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
arc.c:2023arc_hit_watchpoint()
LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
arc.c:2043arc_config_step()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
arc.c:2046arc_config_step()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
arc.c:2048arc_config_step()
LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
arc.c:2052arc_config_step()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info,
arc.c:2055arc_config_step()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
arc.c:2057arc_config_step()
LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
arc.c:2060arc_config_step()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
arc.c:2063arc_config_step()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
arc.c:2065arc_config_step()
LOG_DEBUG("core debug step mode disabled");
arc.c:2073arc_single_step_core()
CHECK_RETVAL(arc_debug_entry(target));
arc.c:2076arc_single_step_core()
CHECK_RETVAL(arc_enable_interrupts(target, 0));
arc.c:2079arc_single_step_core()
CHECK_RETVAL(arc_config_step(target, 1));
arc.c:2082arc_single_step_core()
CHECK_RETVAL(arc_exit_debug(target));
arc.c:2107arc_step()
LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
arc.c:2114arc_step()
CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
arc.c:2118arc_step()
CHECK_RETVAL(arc_restore_context(target));
arc.c:2122arc_step()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
arc.c:2125arc_step()
CHECK_RETVAL(arc_enable_interrupts(target, 0));
arc.c:2128arc_step()
CHECK_RETVAL(arc_config_step(target, 1));
arc.c:2137arc_step()
CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
arc.c:2139arc_step()
LOG_DEBUG("target stepped ");
arc.c:2144arc_step()
CHECK_RETVAL(arc_debug_entry(target));
arc.c:2145arc_step()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
arc.c:2162arc_icache_invalidate()
LOG_DEBUG("Invalidating I$.");
arc.c:2165arc_icache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
arc.c:2182arc_dcache_invalidate()
LOG_DEBUG("Invalidating D$.");
arc.c:2184arc_dcache_invalidate()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
arc.c:2189arc_dcache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
arc.c:2191arc_dcache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
arc.c:2194arc_dcache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
arc.c:2211arc_l2cache_invalidate()
LOG_DEBUG("Invalidating L2$.");
arc.c:2213arc_l2cache_invalidate()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
arc.c:2218arc_l2cache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
arc.c:2220arc_l2cache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
arc.c:2224arc_l2cache_invalidate()
LOG_DEBUG("Waiting for invalidation end.");
arc.c:2225arc_l2cache_invalidate()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
arc.c:2229arc_l2cache_invalidate()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
arc.c:2239arc_cache_invalidate()
CHECK_RETVAL(arc_icache_invalidate(target));
arc.c:2240arc_cache_invalidate()
CHECK_RETVAL(arc_dcache_invalidate(target));
arc.c:2241arc_cache_invalidate()
CHECK_RETVAL(arc_l2cache_invalidate(target));
arc.c:2262arc_dcache_flush()
LOG_DEBUG("Flushing D$.");
arc.c:2265arc_dcache_flush()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
arc.c:2271arc_dcache_flush()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
arc.c:2276arc_dcache_flush()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
arc.c:2280arc_dcache_flush()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
arc.c:2298arc_l2cache_flush()
LOG_DEBUG("Flushing L2$.");
arc.c:2301arc_l2cache_flush()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
arc.c:2305arc_l2cache_flush()
LOG_DEBUG("Waiting for flushing end.");
arc.c:2306arc_l2cache_flush()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
arc.c:2316arc_cache_flush()
CHECK_RETVAL(arc_dcache_flush(target));
arc.c:2317arc_cache_flush()
CHECK_RETVAL(arc_l2cache_flush(target));
arc_cmd.c:133arc_handle_add_reg_type_flags()
LOG_DEBUG("-");
arc_cmd.c:180arc_handle_add_reg_type_flags()
LOG_DEBUG("added flags type {name=%s}", type->data_type.id);
arc_cmd.c:226arc_handle_set_aux_reg()
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, regnum, value));
arc_cmd.c:250arc_handle_get_aux_reg()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, regnum, &value));
arc_cmd.c:282arc_handle_get_core_reg()
CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, regnum, &value));
arc_cmd.c:316arc_handle_set_core_reg()
CHECK_RETVAL(arc_jtag_write_core_reg_one(&arc->jtag_info, regnum, value));
arc_cmd.c:446arc_handle_add_reg_type_struct()
LOG_DEBUG("-");
arc_cmd.c:493arc_handle_add_reg_type_struct()
LOG_DEBUG("added struct type {name=%s}", type->data_type.id);
arc_cmd.c:764arc_handle_actionpoints_num()
LOG_DEBUG("-");
arc_jtag.c:192arc_jtag_status()
CHECK_RETVAL(jtag_execute_queue());
arc_jtag.c:245arc_jtag_write_registers()
LOG_DEBUG("Writing to %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32
arc_jtag.c:286arc_jtag_read_registers()
LOG_DEBUG("Reading %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32,
arc_jtag.c:316arc_jtag_read_registers()
LOG_DEBUG("Read from register: buf[0]=0x%" PRIx32, buffer[0]);
arc_jtag.c:442arc_jtag_write_memory()
LOG_DEBUG("Writing to memory: addr=0x%08" PRIx32 ";count=%" PRIu32 ";buffer[0]=0x%08" PRIx32,
arc_jtag.c:495arc_jtag_read_memory()
LOG_DEBUG("Reading memory: addr=0x%" PRIx32 ";count=%" PRIu32 ";slow=%c",
arc_mem.c:38arc_mem_write_block32()
LOG_DEBUG("Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
arc_mem.c:46arc_mem_write_block32()
CHECK_RETVAL(arc_cache_flush(target));
arc_mem.c:50arc_mem_write_block32()
CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, addr, count,
arc_mem.c:54arc_mem_write_block32()
CHECK_RETVAL(arc_cache_invalidate(target));
arc_mem.c:69arc_mem_write_block16()
LOG_DEBUG("Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
arc_mem.c:76arc_mem_write_block16()
CHECK_RETVAL(arc_cache_flush(target));
arc_mem.c:94arc_mem_write_block16()
CHECK_RETVAL(arc_jtag_read_memory(&arc->jtag_info,
arc_mem.c:107arc_mem_write_block16()
CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info,
arc_mem.c:112arc_mem_write_block16()
CHECK_RETVAL(arc_cache_invalidate(target));
arc_mem.c:127arc_mem_write_block8()
LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
arc_mem.c:131arc_mem_write_block8()
CHECK_RETVAL(arc_cache_flush(target));
arc_mem.c:140arc_mem_write_block8()
CHECK_RETVAL(arc_jtag_read_memory(&arc->jtag_info, (addr + i) & ~3, 1, &buffer_he,
arc_mem.c:145arc_mem_write_block8()
CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, (addr + i) & ~3, 1, &buffer_he));
arc_mem.c:149arc_mem_write_block8()
CHECK_RETVAL(arc_cache_invalidate(target));
arc_mem.c:161arc_mem_write()
LOG_DEBUG("address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
arc_mem.c:223arc_mem_read_block()
LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
arc_mem.c:229arc_mem_read_block()
CHECK_RETVAL(arc_cache_flush(target));
arc_mem.c:231arc_mem_read_block()
CHECK_RETVAL(arc_jtag_read_memory(&arc->jtag_info, addr, count, buf,
arc_mem.c:246arc_mem_read()
LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
arm-jtag-ew.c:98armjtagew_execute_queue()
LOG_DEBUG_IO("runtest %u cycles, end in %i",
arm-jtag-ew.c:107armjtagew_execute_queue()
LOG_DEBUG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
arm-jtag-ew.c:114armjtagew_execute_queue()
LOG_DEBUG_IO("pathmove: %u states, end in %i",
arm-jtag-ew.c:123armjtagew_execute_queue()
LOG_DEBUG_IO("scan end in %i", cmd->cmd.scan->end_state);
arm-jtag-ew.c:128armjtagew_execute_queue()
LOG_DEBUG_IO("scan input, length = %d", scan_size);
arm-jtag-ew.c:140armjtagew_execute_queue()
LOG_DEBUG_IO("reset trst: %i srst %i",
arm-jtag-ew.c:147armjtagew_execute_queue()
tap_set_state(TAP_RESET);
arm-jtag-ew.c:152armjtagew_execute_queue()
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
arm-jtag-ew.c:279armjtagew_state_move()
tap_set_state(tap_get_end_state());
arm-jtag-ew.c:300armjtagew_path_move()
tap_set_state(path[i]);
arm-jtag-ew.c:353armjtagew_scan()
tap_set_state(ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE);
arm-jtag-ew.c:368armjtagew_reset()
LOG_DEBUG("trst: %i, srst: %i", trst, srst);
arm-jtag-ew.c:641armjtagew_tap_execute()
LOG_DEBUG_IO("pending scan result, length = %d", length);
arm-jtag-ew.c:743armjtagew_usb_write()
LOG_DEBUG_IO("armjtagew_usb_write, out_length = %d, result = %d", out_length, result);
arm-jtag-ew.c:760armjtagew_usb_read()
LOG_DEBUG_IO("armjtagew_usb_read, result = %d", result);
arm11.c:43arm11_check_init()
CHECK_RETVAL(arm11_read_dscr(arm11));
arm11.c:46arm11_check_init()
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
arm11.c:47arm11_check_init()
LOG_DEBUG("Bringing target into debug mode");
arm11.c:50arm11_check_init()
CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
arm11.c:70arm11_check_init()
CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
arm11.c:118arm11_debug_entry()
CHECK_RETVAL(arm11_write_dscr(arm11, DSCR_ITR_EN | arm11->dscr));
arm11.c:181arm11_debug_entry()
LOG_DEBUG("Reset c1 Control Register");
arm11.c:234arm11_leave_debug_state()
CHECK_RETVAL(arm11_read_dscr(arm11));
arm11.c:270arm11_leave_debug_state()
CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
arm11.c:272arm11_leave_debug_state()
CHECK_RETVAL(arm11_bpwp_flush(arm11));
arm11.c:277arm11_leave_debug_state()
CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
arm11.c:310arm11_poll()
CHECK_RETVAL(arm11_check_init(arm11));
arm11.c:316arm11_poll()
LOG_DEBUG("enter TARGET_HALTED");
arm11.c:328arm11_poll()
LOG_DEBUG("enter TARGET_RUNNING");
arm11.c:357arm11_halt()
LOG_DEBUG("target->state: %s",
arm11.c:364arm11_halt()
LOG_DEBUG("target was already halted");
arm11.c:370arm11_halt()
CHECK_RETVAL(jtag_execute_queue());
arm11.c:375arm11_halt()
CHECK_RETVAL(arm11_read_dscr(arm11));
arm11.c:395arm11_halt()
CHECK_RETVAL(arm11_debug_entry(arm11));
arm11.c:397arm11_halt()
CHECK_RETVAL(
arm11.c:447arm11_resume()
LOG_DEBUG("target->state: %s",
arm11.c:458arm11_resume()
LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
arm11.c:461arm11_resume()
CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
arm11.c:472arm11_resume()
LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
arm11.c:496arm11_resume()
CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
arm11.c:498arm11_resume()
LOG_DEBUG("Add BP %d at %08" TARGET_PRIxADDR, brp_num,
arm11.c:505arm11_resume()
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
arm11.c:509arm11_resume()
CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
arm11.c:513arm11_resume()
CHECK_RETVAL(jtag_execute_queue());
arm11.c:517arm11_resume()
CHECK_RETVAL(arm11_read_dscr(arm11));
arm11.c:519arm11_resume()
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
arm11.c:542arm11_resume()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
arm11.c:550arm11_step()
LOG_DEBUG("target->state: %s",
arm11.c:562arm11_step()
LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
arm11.c:569arm11_step()
CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
arm11.c:574arm11_step()
LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address);
arm11.c:580arm11_step()
LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address);
arm11.c:584arm11_step()
LOG_DEBUG("Not stepping jump to self");
arm11.c:639arm11_step()
CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
arm11.c:651arm11_step()
CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
arm11.c:655arm11_step()
CHECK_RETVAL(jtag_execute_queue());
arm11.c:664arm11_step()
CHECK_RETVAL(arm11_read_dscr(arm11));
arm11.c:665arm11_step()
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
arm11.c:684arm11_step()
CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
arm11.c:687arm11_step()
CHECK_RETVAL(arm11_debug_entry(arm11));
arm11.c:696arm11_step()
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
arm11.c:717arm11_assert_reset()
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
arm11.c:765arm11_deassert_reset()
CHECK_RETVAL(arm11_poll(target));
arm11.c:779arm11_deassert_reset()
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
arm11.c:805arm11_read_memory_inner()
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
arm11.c:828arm11_read_memory_inner()
CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
arm11.c:833arm11_read_memory_inner()
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
arm11.c:846arm11_read_memory_inner()
CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
arm11.c:852arm11_read_memory_inner()
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
arm11.c:869arm11_read_memory_inner()
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
arm11.c:903arm11_write_memory_inner()
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
arm11.c:1060arm11_add_breakpoint()
LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
arm11.c:1065arm11_add_breakpoint()
LOG_DEBUG("only breakpoints of four bytes length supported");
arm11.c:1165arm11_examine()
CHECK_RETVAL(jtag_execute_queue());
arm11.c:1204arm11_examine()
LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
arm11.c:1211arm11_examine()
CHECK_RETVAL(arm11_dpm_init(arm11, didr));
arm11.c:1227arm11_examine()
CHECK_RETVAL(etm_setup(target));
arm11_dbgtap.c:129arm11_add_ir()
JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
arm11_dbgtap.c:133arm11_add_ir()
JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr), instr);
arm11_dbgtap.c:201arm11_add_debug_scan_n()
JTAG_DEBUG("SCREG <= %d", chain);
arm11_dbgtap.c:245arm11_add_debug_inst()
JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
arm11_dbgtap.c:282arm11_read_dscr()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:285arm11_read_dscr()
JTAG_DEBUG("DSCR = %08x (OLD %08x)",
arm11_dbgtap.c:318arm11_write_dscr()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:320arm11_write_dscr()
JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
arm11_dbgtap.c:395arm11_run_instr_no_data()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:479arm11_run_instr_data_to_core()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:481arm11_run_instr_data_to_core()
JTAG_DEBUG("DTR ready %d n_retry %d", ready, n_retry);
arm11_dbgtap.c:510arm11_run_instr_data_to_core()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:512arm11_run_instr_data_to_core()
JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
arm11_dbgtap.c:755arm11_run_instr_data_from_core()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:757arm11_run_instr_data_from_core()
JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
arm11_dbgtap.c:881arm11_sc7_run()
JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
arm11_dbgtap.c:889arm11_sc7_run()
CHECK_RETVAL(jtag_execute_queue());
arm11_dbgtap.c:911arm11_sc7_run()
JTAG_DEBUG("SC7 => Data %08x", (unsigned) data_in);
arm11_dbgtap.c:988arm11_read_memory_word()
CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
arm11_dbgtap.c:991arm11_read_memory_word()
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
arm720t.c:80arm720t_scan_cp15()
LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
arm720t.c:199arm720t_post_debug_entry()
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
arm720t.c:328arm720t_soft_reset_halt()
if (debug_level >= 3)
arm7_9_common.c:62arm7_9_clear_watchpoints()
LOG_DEBUG("-");
arm7_9_common.c:95arm7_9_assign_wp()
LOG_DEBUG("BPID: %" PRIu32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %u",
arm7_9_common.c:146arm7_9_set_software_breakpoints()
LOG_DEBUG("SW BP using hw wp: %d",
arm7_9_common.c:181arm7_9_set_breakpoint()
LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
arm7_9_common.c:293arm7_9_unset_breakpoint()
LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR,
arm7_9_common.c:303arm7_9_unset_breakpoint()
LOG_DEBUG("BPID: %" PRIu32 " Releasing hw wp: %d",
arm7_9_common.c:640arm7_9_execute_sys_speed()
if (debug_level >= 3)
arm7_9_common.c:813arm7_9_poll()
LOG_DEBUG("DBGACK already set during server startup.");
arm7_9_common.c:875arm7_9_assert_reset()
LOG_DEBUG("target->state: %s", target_state_name(target));
arm7_9_common.c:970arm7_9_deassert_reset()
LOG_DEBUG("target->state: %s", target_state_name(target));
arm7_9_common.c:1091arm7_9_soft_reset_halt()
if (debug_level >= 3)
arm7_9_common.c:1117arm7_9_soft_reset_halt()
LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
arm7_9_common.c:1178arm7_9_halt()
LOG_DEBUG("target->state: %s",
arm7_9_common.c:1182arm7_9_halt()
LOG_DEBUG("target was already halted");
arm7_9_common.c:1269arm7_9_debug_entry()
LOG_DEBUG("target entered debug from Thumb state");
arm7_9_common.c:1274arm7_9_debug_entry()
LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
arm7_9_common.c:1282arm7_9_debug_entry()
LOG_DEBUG("target entered debug from Jazelle state");
arm7_9_common.c:1287arm7_9_debug_entry()
LOG_DEBUG("target entered debug from ARM state");
arm7_9_common.c:1314arm7_9_debug_entry()
LOG_DEBUG("target entered debug state in %s mode",
arm7_9_common.c:1318arm7_9_debug_entry()
LOG_DEBUG("thumb state, applying fixups");
arm7_9_common.c:1335arm7_9_debug_entry()
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
arm7_9_common.c:1343arm7_9_debug_entry()
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
arm7_9_common.c:1391arm7_9_full_context()
LOG_DEBUG("-");
arm7_9_common.c:1507arm7_9_restore_context()
LOG_DEBUG("-");
arm7_9_common.c:1526arm7_9_restore_context()
LOG_DEBUG("examining %s mode",
arm7_9_common.c:1537arm7_9_restore_context()
LOG_DEBUG("examining dirty reg: %s", reg->name);
arm7_9_common.c:1547arm7_9_restore_context()
LOG_DEBUG("require mode change");
arm7_9_common.c:1581arm7_9_restore_context()
LOG_DEBUG("writing register %i mode %s "
arm7_9_common.c:1597arm7_9_restore_context()
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "",
arm7_9_common.c:1612arm7_9_restore_context()
LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
arm7_9_common.c:1617arm7_9_restore_context()
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
arm7_9_common.c:1627arm7_9_restore_context()
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
arm7_9_common.c:1710arm7_9_resume()
LOG_DEBUG("-");
arm7_9_common.c:1733arm7_9_resume()
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRIu32,
arm7_9_common.c:1752arm7_9_resume()
LOG_DEBUG("enable single-step");
arm7_9_common.c:1775arm7_9_resume()
LOG_DEBUG("disable single-step");
arm7_9_common.c:1789arm7_9_resume()
LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
arm7_9_common.c:1792arm7_9_resume()
LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
arm7_9_common.c:1843arm7_9_resume()
LOG_DEBUG("target resumed");
arm7_9_common.c:1978arm7_9_step()
LOG_DEBUG("target stepped");
arm7_9_common.c:2118arm7_9_read_memory()
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
arm7tdmi.c:367arm7tdmi_write_xpsr()
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm7tdmi.c:397arm7tdmi_write_xpsr_im8()
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm7tdmi.c:541arm7tdmi_branch_resume_thumb()
LOG_DEBUG("-");
arm920t.c:412arm920t_post_debug_entry()
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
arm920t.c:450arm920t_post_debug_entry()
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
arm920t.c:626arm920t_write_memory()
LOG_DEBUG("D-Cache buffered, "
arm920t.c:650arm920t_write_memory()
LOG_DEBUG("D-Cache in 'write back' mode, "
arm920t.c:674arm920t_write_memory()
LOG_DEBUG("D-Cache enabled, "
arm920t.c:708arm920t_write_memory()
LOG_DEBUG("I-Cache enabled, "
arm920t.c:753arm920t_soft_reset_halt()
if (debug_level >= 3) {
arm920t.c:880arm920t_handle_read_cache_command()
LOG_DEBUG("error opening cache content file");
arm920t.c:1162arm920t_handle_read_mmu_command()
LOG_DEBUG("error opening mmu content file");
arm926ejs.c:224arm926ejs_examine_debug_reason()
LOG_DEBUG("no *NEW* debug entry (?missed one?)");
arm926ejs.c:229arm926ejs_examine_debug_reason()
LOG_DEBUG("breakpoint from EICE unit 0");
arm926ejs.c:233arm926ejs_examine_debug_reason()
LOG_DEBUG("breakpoint from EICE unit 1");
arm926ejs.c:237arm926ejs_examine_debug_reason()
LOG_DEBUG("soft breakpoint (BKPT instruction)");
arm926ejs.c:241arm926ejs_examine_debug_reason()
LOG_DEBUG("vector catch breakpoint");
arm926ejs.c:245arm926ejs_examine_debug_reason()
LOG_DEBUG("external breakpoint");
arm926ejs.c:249arm926ejs_examine_debug_reason()
LOG_DEBUG("watchpoint from EICE unit 0");
arm926ejs.c:253arm926ejs_examine_debug_reason()
LOG_DEBUG("watchpoint from EICE unit 1");
arm926ejs.c:257arm926ejs_examine_debug_reason()
LOG_DEBUG("external watchpoint");
arm926ejs.c:261arm926ejs_examine_debug_reason()
LOG_DEBUG("internal debug request");
arm926ejs.c:265arm926ejs_examine_debug_reason()
LOG_DEBUG("external debug request");
arm926ejs.c:269arm926ejs_examine_debug_reason()
LOG_DEBUG("debug re-entry from system speed access");
arm926ejs.c:429arm926ejs_post_debug_entry()
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
arm926ejs.c:458arm926ejs_post_debug_entry()
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
arm926ejs.c:548arm926ejs_soft_reset_halt()
if (debug_level >= 1) {
arm946e.c:263arm946e_invalidate_whole_dcache()
LOG_DEBUG("ERROR writing index");
arm946e.c:271arm946e_invalidate_whole_dcache()
LOG_DEBUG("ERROR reading dtag");
arm946e.c:282arm946e_invalidate_whole_dcache()
LOG_DEBUG("ERROR cleaning cache line");
arm946e.c:289arm946e_invalidate_whole_dcache()
LOG_DEBUG("ERROR flushing cache line");
arm946e.c:305arm946e_invalidate_whole_icache()
LOG_DEBUG("FLUSHING I$");
arm946e.c:312arm946e_invalidate_whole_icache()
LOG_DEBUG("ERROR flushing I$");
arm946e.c:352arm946e_post_debug_entry()
LOG_DEBUG("ERROR disabling cache");
arm946e.c:381arm946e_pre_restore_context()
LOG_DEBUG("ERROR enabling cache");
arm946e.c:411arm946e_invalidate_dcache()
LOG_DEBUG("ERROR writing index");
arm946e.c:418arm946e_invalidate_dcache()
LOG_DEBUG("ERROR reading dtag");
arm946e.c:431arm946e_invalidate_dcache()
LOG_DEBUG("ERROR cleaning cache line");
arm946e.c:438arm946e_invalidate_dcache()
LOG_DEBUG("ERROR flushing cache line");
arm946e.c:468arm946e_invalidate_icache()
LOG_DEBUG("ERROR writing index");
arm946e.c:475arm946e_invalidate_icache()
LOG_DEBUG("ERROR reading itag");
arm946e.c:488arm946e_invalidate_icache()
LOG_DEBUG("ERROR flushing cache line");
arm946e.c:506arm946e_write_memory()
LOG_DEBUG("-");
arm946e.c:554arm946e_read_memory()
LOG_DEBUG("-");
arm9tdmi.c:441arm9tdmi_write_xpsr()
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm9tdmi.c:476arm9tdmi_write_xpsr_im8()
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm9tdmi.c:614arm9tdmi_branch_resume_thumb()
LOG_DEBUG("-");
arm_adi_v5.c:400mem_ap_setup_transfer_verify_size_packing()
LOG_DEBUG("AP#0x%" PRIx64 " probed size %u: %s", ap->ap_num, size,
arm_adi_v5.c:409mem_ap_setup_transfer_verify_size_packing()
LOG_DEBUG("probed packing: %s",
arm_adi_v5.c:783dap_dp_init()
LOG_DEBUG("%s", adiv5_dap_name(dap));
arm_adi_v5.c:816dap_dp_init()
LOG_DEBUG("DAP: wait CDBGPWRUPACK");
arm_adi_v5.c:824dap_dp_init()
LOG_DEBUG("DAP: wait CSYSPWRUPACK");
arm_adi_v5.c:859dap_dp_init_or_reconnect()
LOG_DEBUG("%s", adiv5_dap_name(dap));
arm_adi_v5.c:934mem_ap_init()
LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
arm_adi_v5.c:954dap_to_swd()
LOG_DEBUG("Enter SWD mode");
arm_adi_v5.c:972dap_to_jtag()
LOG_DEBUG("Enter JTAG mode");
arm_adi_v5.c:1111dap_find_get_ap()
LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
arm_adi_v5.c:1136dap_find_get_ap()
LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
arm_adi_v5.c:1146dap_find_get_ap()
LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
arm_adi_v5.c:1193dap_get_ap()
LOG_DEBUG("refcount AP#0x%" PRIx64 " get %u", ap_num, ap->refcount);
arm_adi_v5.c:1203dap_get_config_ap()
LOG_DEBUG("refcount AP#0x%" PRIx64 " get_config %u", ap_num, ap->refcount);
arm_adi_v5.c:1218dap_put_ap()
LOG_DEBUG("refcount AP#0x%" PRIx64 " put %u", ap->ap_num, ap->refcount);
arm_adi_v5.c:1402rtp_read_cs_regs()
LOG_DEBUG("Failed read CoreSight registers");
arm_adi_v5.c:1879rtp_rom_loop()
LOG_DEBUG("Failed read ROM table entry");
arm_adi_v5.c:1910rtp_rom_loop()
LOG_DEBUG("Wrong AP # 0x%" PRIx64, component_base);
arm_adi_v5.c:1923rtp_rom_loop()
LOG_DEBUG("Ignore error parsing CoreSight component");
arm_adi_v5.c:2305dap_lookup_cs_component()
LOG_DEBUG("CS lookup ended in AP # 0x%" PRIx64 ". Ignore it", lookup.ap_num);
arm_adi_v5.c:2308dap_lookup_cs_component()
LOG_DEBUG("CS lookup found at 0x%" PRIx64, lookup.component_base);
arm_adi_v5.c:2313dap_lookup_cs_component()
LOG_DEBUG("CS lookup error %d", retval);
arm_adi_v5.c:2316dap_lookup_cs_component()
LOG_DEBUG("CS lookup not found");
arm_adi_v5.h:682dap_dp_poll_register()
LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
arm_adi_v5.h:696dap_dp_poll_register()
LOG_DEBUG("DAP: poll %x timeout", reg);
arm_dap.c:96dap_init_all()
LOG_DEBUG("Initializing all DAPs ...");
arm_dap.c:120dap_init_all()
LOG_DEBUG("DAP %s configured by default to use ADIv5 protocol", jtag_tap_name(dap->tap));
arm_dap.c:123dap_init_all()
LOG_DEBUG("DAP %s configured to use %s protocol by user cfg file", jtag_tap_name(dap->tap),
arm_dpm.c:53dpm_mrc()
LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
arm_dpm.c:77dpm_mrrc()
LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
arm_dpm.c:101dpm_mcr()
LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
arm_dpm.c:125dpm_mcrr()
LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
arm_dpm.c:201dpm_read_reg_u64()
LOG_DEBUG("READ: %s, %8.8x, %8.8x", r->name,
arm_dpm.c:269arm_dpm_read_reg()
LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
arm_dpm.c:305dpm_write_reg_u64()
LOG_DEBUG("WRITE: %s, %8.8x, %8.8x", r->name,
arm_dpm.c:354dpm_write_reg()
LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
arm_dpm.c:904dpm_bpwp_setup()
LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
arm_dpm.c:924dpm_add_breakpoint()
LOG_DEBUG("using HW bkpt, not SW...");
arm_dpm.c:968dpm_watchpoint_setup()
LOG_DEBUG("watchpoint values and masking not supported");
arm_io.c:50arm_code_to_working_area()
LOG_DEBUG("%s: no %d byte buffer", __func__, (int) size);
arm_tpiu_swo.c:169arm_tpiu_swo_handle_event()
LOG_DEBUG("TPIU/SWO: %s event: %s (%d) action : %s",
arm_tpiu_swo.c:610handle_arm_tpiu_swo_enable()
LOG_DEBUG("%s: enable deferred", obj->name);
arm_tpiu_swo.c:639handle_arm_tpiu_swo_enable()
LOG_DEBUG("SWO pin frequency not set, will be autodetected by the adapter");
arm_tpiu_swo.c:1027handle_arm_tpiu_swo_init()
LOG_DEBUG("%s: running enable during init", obj->name);
armv4_5.c:485arm_set_cpsr()
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv4_5.c:620armv4_5_set_core_reg()
LOG_DEBUG("changing ARM core mode to '%s'",
armv4_5.c:1406armv4_5_run_algorithm_inner()
LOG_DEBUG("Running algorithm");
armv4_5.c:1485armv4_5_run_algorithm_inner()
LOG_DEBUG("setting core_mode: 0x%2.2x",
armv4_5.c:1554armv4_5_run_algorithm_inner()
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
armv4_5_mmu.c:34armv4_5_mmu_translate_va()
LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
armv4_5_mmu.c:71armv4_5_mmu_translate_va()
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
armv7a.c:104armv7a_read_midr()
LOG_DEBUG("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
armv7a.c:137armv7a_read_ttbcr()
LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
armv7a.c:172armv7a_read_ttbcr()
LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
armv7a.c:300armv7a_read_mpidr()
LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
armv7a.c:390armv7a_identify_cache()
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
armv7a.c:402armv7a_identify_cache()
LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
armv7a.c:430armv7a_identify_cache()
LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv7a.c:436armv7a_identify_cache()
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv7a.c:450armv7a_identify_cache()
LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv7a.c:456armv7a_identify_cache()
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv7a_cache.c:31armv7a_l1_d_cache_sanity_check()
LOG_DEBUG("data cache is not enabled");
armv7a_cache.c:49armv7a_l1_i_cache_sanity_check()
LOG_DEBUG("instruction cache is not enabled");
armv7a_cache.c:61armv7a_l1_d_cache_flush_level()
LOG_DEBUG("cl %" PRId32, cl);
armv7a_cache_l2x.c:33arm7a_l2x_sanity_check()
LOG_DEBUG("l2x is not configured!");
armv7a_mmu.c:258armv7a_mmu_dump_table()
LOG_DEBUG("L1 desc[%8.8x]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
armv7m.c:174armv7m_restore_context()
LOG_DEBUG(" ");
armv7m.c:369armv7m_read_core_reg()
LOG_DEBUG("read %s value 0x%016" PRIx64, r->name, q);
armv7m.c:371armv7m_read_core_reg()
LOG_DEBUG("read %s value 0x%08" PRIx32, r->name, reg_value);
armv7m.c:439armv7m_write_core_reg()
LOG_DEBUG("write %s value 0x%016" PRIx64, r->name, q);
armv7m.c:441armv7m_write_core_reg()
LOG_DEBUG("write %s value 0x%08" PRIx32, r->name, t);
armv7m.c:606armv7m_start_algorithm()
LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
armv7m.c:656armv7m_wait_algorithm()
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
armv7m.c:704armv7m_wait_algorithm()
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
armv7m.c:715armv7m_wait_algorithm()
LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
armv7m.c:1006armv7m_blank_check_memory()
LOG_DEBUG("Starting erase check of %d blocks, parameters@"
armv7m.c:1088armv7m_maybe_skip_bkpt_inst()
LOG_DEBUG("Skipping over BKPT instruction");
armv8.c:162armv8_read_ttbcr32()
LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
armv8.c:176armv8_read_ttbcr32()
LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
armv8.c:319armv8_read_reg()
LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
armv8.c:328armv8_read_reg()
LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
armv8.c:337armv8_read_reg()
LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
armv8.c:346armv8_read_reg()
LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
armv8.c:355armv8_read_reg()
LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
armv8.c:364armv8_read_reg()
LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
armv8.c:373armv8_read_reg()
LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
armv8.c:382armv8_read_reg()
LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
armv8.c:391armv8_read_reg()
LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
armv8.c:480armv8_write_reg()
LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
armv8.c:489armv8_write_reg()
LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
armv8.c:498armv8_write_reg()
LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
armv8.c:507armv8_write_reg()
LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
armv8.c:516armv8_write_reg()
LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
armv8.c:525armv8_write_reg()
LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
armv8.c:534armv8_write_reg()
LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
armv8.c:543armv8_write_reg()
LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
armv8.c:552armv8_write_reg()
LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
armv8.c:964armv8_set_cpsr()
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv8.c:1248armv8_handle_exception_catch_command()
LOG_DEBUG("found: %s", n->name);
armv8.c:1967armv8_get_gdb_reg_list()
LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
armv8.c:1994armv8_get_gdb_reg_list()
LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
armv8_cache.c:48armv8_cache_d_inner_flush_level()
LOG_DEBUG("cl %" PRId32, cl);
armv8_cache.c:327armv8_identify_cache()
LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
armv8_cache.c:337armv8_identify_cache()
LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
armv8_cache.c:364armv8_identify_cache()
LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv8_cache.c:370armv8_identify_cache()
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv8_cache.c:384armv8_identify_cache()
LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv8_cache.c:390armv8_identify_cache()
LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv8_dpm.c:247dpmv8_exec_opcode()
LOG_DEBUG("EL %i -> %" PRIu32, dpm->last_el, (dscr >> 8) & 3);
armv8_dpm.c:472dpmv8_bpwp_disable()
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
armv8_dpm.c:495dpmv8_mrc()
LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
armv8_dpm.c:520dpmv8_mcr()
LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
armv8_dpm.c:551armv8_dpm_modeswitch()
LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
armv8_dpm.c:554armv8_dpm_modeswitch()
LOG_DEBUG("setting mode 0x%x", mode);
armv8_dpm.c:589armv8_dpm_modeswitch()
LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el);
armv8_dpm.c:605armv8_dpm_modeswitch()
LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
armv8_dpm.c:659dpmv8_read_reg()
LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64);
armv8_dpm.c:661dpmv8_read_reg()
LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64);
armv8_dpm.c:674dpmv8_read_reg()
LOG_DEBUG("READ: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
armv8_dpm.c:675dpmv8_read_reg()
LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
armv8_dpm.c:680dpmv8_read_reg()
LOG_DEBUG("Failed to read %s register", r->name);
armv8_dpm.c:702dpmv8_write_reg()
LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64);
armv8_dpm.c:704dpmv8_write_reg()
LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64);
armv8_dpm.c:716dpmv8_write_reg()
LOG_DEBUG("WRITE: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
armv8_dpm.c:717dpmv8_write_reg()
LOG_DEBUG("WRITE: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
armv8_dpm.c:722dpmv8_write_reg()
LOG_DEBUG("Failed to write %s register", r->name);
armv8_dpm.c:1157dpmv8_bpwp_setup()
LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
armv8_dpm.c:1177dpmv8_add_breakpoint()
LOG_DEBUG("using HW bkpt, not SW...");
armv8_dpm.c:1221dpmv8_watchpoint_setup()
LOG_DEBUG("watchpoint values and masking not supported");
armv8_dpm.c:1327armv8_dpm_handle_exception()
LOG_DEBUG("Exception taken to EL %i, DLR=0x%016"PRIx64" DSPSR=0x%08"PRIx32,
at91sam3.c:2004efc_get_status()
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
at91sam3.c:2027efc_get_result()
LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
at91sam3.c:2111efc_start_command()
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
at91sam3.c:2115efc_start_command()
LOG_DEBUG("Error Write failed");
at91sam3.c:2181flashd_read_uid()
LOG_DEBUG("Begin");
at91sam3.c:2196flashd_read_uid()
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
at91sam3.c:2212flashd_erase_entire_bank()
LOG_DEBUG("Here");
at91sam3.c:2228flashd_get_gpnvm()
LOG_DEBUG("Here");
at91sam3.c:2269flashd_clr_gpnvm()
LOG_DEBUG("Here");
at91sam3.c:2283flashd_clr_gpnvm()
LOG_DEBUG("Failed: %d", r);
at91sam3.c:2287flashd_clr_gpnvm()
LOG_DEBUG("End: %d", r);
at91sam3.c:2333flashd_get_lock_bits()
LOG_DEBUG("Here");
at91sam3.c:2337flashd_get_lock_bits()
LOG_DEBUG("End: %d", r);
at91sam3.c:2923sam3_get_info()
LOG_DEBUG("Start: %s", reg->name);
at91sam3.c:2932sam3_get_info()
LOG_DEBUG("End: %s", reg->name);
at91sam3.c:2957sam3_protect_check()
LOG_DEBUG("Begin");
at91sam3.c:2973sam3_protect_check()
LOG_DEBUG("Failed: %d", r);
at91sam3.c:2979sam3_protect_check()
LOG_DEBUG("Done");
at91sam3.c:3076sam3_get_details()
LOG_DEBUG("Begin");
at91sam3.c:3124sam3_get_details()
LOG_DEBUG("End");
at91sam3.c:3134_sam3_probe()
LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
at91sam3.c:3150_sam3_probe()
LOG_DEBUG("Here");
at91sam3.c:3189_sam3_probe()
LOG_DEBUG("Bank = %d, nbanks = %d",
at91sam3.c:3216sam3_erase()
LOG_DEBUG("Here");
at91sam3.c:3224sam3_erase()
LOG_DEBUG("Here,r=%d", r);
at91sam3.c:3234sam3_erase()
LOG_DEBUG("Here");
at91sam3.c:3247sam3_protect()
LOG_DEBUG("Here");
at91sam3.c:3261sam3_protect()
LOG_DEBUG("End: r=%d", r);
at91sam3.c:3299sam3_page_write()
LOG_DEBUG("Error Read failed: read flash mode register");
at91sam3.c:3307sam3_page_write()
LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
at91sam3.c:3310sam3_page_write()
LOG_DEBUG("Error Write failed: set flash mode register");
at91sam3.c:3312sam3_page_write()
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
at91sam3.c:3399sam3_write()
LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
at91sam3.c:3400sam3_write()
LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
at91sam3.c:3411sam3_write()
LOG_DEBUG("Special case, all in one page");
at91sam3.c:3431sam3_write()
LOG_DEBUG("Not-Aligned start");
at91sam3.c:3460sam3_write()
LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
at91sam3.c:3475sam3_write()
LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
at91sam3.c:3486sam3_write()
LOG_DEBUG("Done!");
at91sam3.c:3543sam3_handle_info_command()
LOG_DEBUG("Sam3Info, Failed %d", r);
at91sam4.c:1454efc_get_status()
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
at91sam4.c:1477efc_get_result()
LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
at91sam4.c:1561efc_start_command()
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
at91sam4.c:1565efc_start_command()
LOG_DEBUG("Error Write failed");
at91sam4.c:1631flashd_read_uid()
LOG_DEBUG("Begin");
at91sam4.c:1646flashd_read_uid()
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
at91sam4.c:1662flashd_erase_entire_bank()
LOG_DEBUG("Here");
at91sam4.c:1678flashd_erase_pages()
LOG_DEBUG("Here");
at91sam4.c:1724flashd_get_gpnvm()
LOG_DEBUG("Here");
at91sam4.c:1765flashd_clr_gpnvm()
LOG_DEBUG("Here");
at91sam4.c:1779flashd_clr_gpnvm()
LOG_DEBUG("Failed: %d", r);
at91sam4.c:1783flashd_clr_gpnvm()
LOG_DEBUG("End: %d", r);
at91sam4.c:1829flashd_get_lock_bits()
LOG_DEBUG("Here");
at91sam4.c:1837flashd_get_lock_bits()
LOG_DEBUG("End: %d", r);
at91sam4.c:2416sam4_get_info()
LOG_DEBUG("Start: %s", reg->name);
at91sam4.c:2425sam4_get_info()
LOG_DEBUG("End: %s", reg->name);
at91sam4.c:2450sam4_protect_check()
LOG_DEBUG("Begin");
at91sam4.c:2466sam4_protect_check()
LOG_DEBUG("Failed: %d", r);
at91sam4.c:2472sam4_protect_check()
LOG_DEBUG("Done");
at91sam4.c:2562sam4_get_details()
LOG_DEBUG("Begin");
at91sam4.c:2580sam4_get_details()
LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
at91sam4.c:2612sam4_get_details()
LOG_DEBUG("End");
at91sam4.c:2640sam4_probe()
LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
at91sam4.c:2656sam4_probe()
LOG_DEBUG("Here");
at91sam4.c:2668sam4_probe()
LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
at91sam4.c:2698sam4_probe()
LOG_DEBUG("Bank = %d, nbanks = %d",
at91sam4.c:2730sam4_erase()
LOG_DEBUG("Here");
at91sam4.c:2738sam4_erase()
LOG_DEBUG("Here,r=%d", r);
at91sam4.c:2748sam4_erase()
LOG_DEBUG("Here");
at91sam4.c:2779sam4_protect()
LOG_DEBUG("Here");
at91sam4.c:2793sam4_protect()
LOG_DEBUG("End: r=%d", r);
at91sam4.c:2836sam4_set_wait()
LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
at91sam4.c:2856sam4_page_write()
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
at91sam4.c:2947sam4_write()
LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
at91sam4.c:2948sam4_write()
LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
at91sam4.c:2959sam4_write()
LOG_DEBUG("Special case, all in one page");
at91sam4.c:2979sam4_write()
LOG_DEBUG("Not-Aligned start");
at91sam4.c:3008sam4_write()
LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
at91sam4.c:3023sam4_write()
LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
at91sam4.c:3034sam4_write()
LOG_DEBUG("Done!");
at91sam4.c:3091sam4_handle_info_command()
LOG_DEBUG("Sam4Info, Failed %d", r);
at91sam4l.c:440sam4l_erase()
LOG_DEBUG("Erasing the whole chip");
at91sam4l.c:448sam4l_erase()
LOG_DEBUG("Erasing sectors %u through %u...\n", first, last);
at91sam4l.c:469sam4l_erase()
LOG_DEBUG("Page %u was not erased.", pn);
at91sam4l.c:486sam4l_write_page()
LOG_DEBUG("sam4l_write_page address=%08" PRIx32, address);
at91sam4l.c:524sam4l_write_page_partial()
LOG_DEBUG("sam4l_write_page_partial address=%08" PRIx32 " nb=%08" PRIx32, address, nb);
at91sam4l.c:554sam4l_write()
LOG_DEBUG("sam4l_write offset=%08" PRIx32 " count=%08" PRIx32, offset, count);
at91sam7.c:280at91sam7_set_flash_mode()
LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
at91sam7.c:294at91sam7_wait_status_busy()
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
at91sam7.c:298at91sam7_wait_status_busy()
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
at91sam7.c:322at91sam7_flash_command()
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
at91sam7.c:630at91sam7_read_part_info()
LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
at91sam7.c:930at91sam7_write()
LOG_DEBUG("first_page: %i, last_page: %i, count %i",
at91sam7.c:957at91sam7_write()
LOG_DEBUG("Write flash bank:%u page number:%" PRIu32, bank->bank_number, pagen);
at91sam7.c:1086at91sam7_handle_gpnvm_command()
LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32,
at91sam9.c:488at91sam9_nand_device_command()
LOG_DEBUG("AT91SAM9 NAND Device Command");
ath79.c:266ath79_spi_bitbang_chunk()
LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08" PRIx32 ", %p, %d)",
ath79.c:269ath79_spi_bitbang_chunk()
LOG_DEBUG("max code %d => max len %d. to_xfer %d",
ath79.c:275ath79_spi_bitbang_chunk()
LOG_DEBUG("Assembled %d instructions, %d stores",
ath79.c:302ath79_spi_bitbang_chunk()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG)) {
ath79.c:304ath79_spi_bitbang_chunk()
LOG_DEBUG("bitbang %02x => %02x",
ath79.c:352ath79_flash_bank_command()
LOG_DEBUG("%s", __func__);
ath79.c:496ath79_erase()
LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
ath79.c:610ath79_write_buffer()
LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
ath79.c:638ath79_write()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
ath79.c:679ath79_read_buffer()
LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
ath79.c:707ath79_read()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
ath79.c:782ath79_probe()
LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
atsamv.c:95samv_efc_start_command()
LOG_DEBUG("starting flash command: 0x%08x", (unsigned int)(v));
atsamv.c:98samv_efc_start_command()
LOG_DEBUG("write failed");
atsamv.c:204samv_clear_gpnvm()
LOG_DEBUG("get gpnvm failed: %d", r);
atsamv.c:208samv_clear_gpnvm()
LOG_DEBUG("clear gpnvm result: %d", r);
atsamv.c:439samv_page_write()
LOG_DEBUG("write page %u at address 0x%08x", pagenum, (unsigned int)addr);
atsamv.c:484samv_write()
LOG_DEBUG("offset: 0x%08x, count: 0x%08x",
atsamv.c:486samv_write()
LOG_DEBUG("page start: %d, page end: %d", (int)(page_cur), (int)(page_end));
atsamv.c:499samv_write()
LOG_DEBUG("special case, all in one page");
atsamv.c:516samv_write()
LOG_DEBUG("non-aligned start");
atsamv.c:540samv_write()
LOG_DEBUG("full page loop: cur=%d, end=%d, count = 0x%08x",
atsamv.c:554samv_write()
LOG_DEBUG("final partial page, count = 0x%08x", (unsigned int)(count));
avr32_ap7k.c:120avr32_write_core_reg()
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
avr32_ap7k.c:260avr32_ap7k_halt()
LOG_DEBUG("target->state: %s",
avr32_ap7k.c:264avr32_ap7k_halt()
LOG_DEBUG("target was already halted");
avr32_ap7k.c:340avr32_ap7k_resume()
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
avr32_ap7k.c:375avr32_ap7k_resume()
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
avr32_ap7k.c:379avr32_ap7k_resume()
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
avr32_ap7k.c:428avr32_ap7k_read_memory()
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
avr32_ap7k.c:468avr32_ap7k_write_memory()
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
avrf.c:129avr_jtagprg_chiperase()
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
avrf.c:190avr_jtagprg_writeflashpage()
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
avrf.c:218avrf_erase()
LOG_DEBUG("%s", __func__);
avrf.c:256avrf_write()
LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
avrf.c:257avrf_write()
LOG_DEBUG("count is %" PRIu32 "", count);
avrf.c:436avrf_handle_mass_erase_command()
LOG_DEBUG("%s", __func__);
avrt.c:83avr_init_target()
LOG_DEBUG("%s", __func__);
avrt.c:89avr_arch_state()
LOG_DEBUG("%s", __func__);
avrt.c:98avr_poll()
LOG_DEBUG("%s", __func__);
avrt.c:104avr_halt()
LOG_DEBUG("%s", __func__);
avrt.c:111avr_resume()
LOG_DEBUG("%s", __func__);
avrt.c:117avr_step()
LOG_DEBUG("%s", __func__);
avrt.c:125avr_assert_reset()
LOG_DEBUG("%s", __func__);
avrt.c:133avr_deassert_reset()
LOG_DEBUG("%s", __func__);
batch.c:91riscv_batch_run()
LOG_DEBUG("Ignoring empty batch.");
batch.c:197dump_field()
if (debug_level < LOG_LVL_DEBUG)
bluenrg-x.c:194bluenrgx_erase()
LOG_DEBUG("address = %08" PRIx32 ", index = %u", address, i);
bluenrg-x.c:291bluenrgx_write()
LOG_DEBUG("no working area for target algorithm stack");
bluenrg-x.c:328bluenrgx_write()
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
bluenrg-x.c:329bluenrgx_write()
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
bluenrg-x.c:330bluenrgx_write()
LOG_DEBUG("write_algorithm_stack->address = " TARGET_ADDR_FMT, write_algorithm_stack->address);
bluenrg-x.c:331bluenrgx_write()
LOG_DEBUG("address = %08" PRIx32, address);
bluenrg-x.c:332bluenrgx_write()
LOG_DEBUG("count = %08" PRIx32, count);
breakpoints.c:93breakpoint_add_internal()
LOG_TARGET_DEBUG(target, "added %s breakpoint at " TARGET_ADDR_FMT
breakpoints.c:143context_breakpoint_add_internal()
LOG_TARGET_DEBUG(target, "added %s Context breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %" PRIu32 ")",
breakpoints.c:198hybrid_breakpoint_add_internal()
LOG_TARGET_DEBUG(target,
breakpoints.c:300breakpoint_free()
LOG_TARGET_DEBUG(target, "free BPID: %" PRIu32 " --> %d", breakpoint->unique_id, retval);
breakpoints.c:328breakpoint_remove_all_internal()
LOG_TARGET_DEBUG(target, "Delete all breakpoints");
breakpoints.c:406watchpoint_free()
LOG_TARGET_DEBUG(target, "free WPID: %d --> %d", watchpoint->unique_id, retval);
breakpoints.c:558watchpoint_add_internal()
LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT
breakpoints.c:646watchpoint_clear_target()
LOG_DEBUG("Delete all watchpoints for target: %s",
breakpoints.c:675watchpoint_hit()
LOG_TARGET_DEBUG(target, "Found hit watchpoint at " TARGET_ADDR_FMT " (WPID: %d)",
cfi.c:337cfi_intel_wait_status_busy()
LOG_DEBUG("status: 0x%x", status);
cfi.c:391cfi_spansion_wait_status_busy()
LOG_DEBUG("status: 0x%x", status);
cfi.c:396cfi_spansion_wait_status_busy()
LOG_DEBUG("status: 0x%x", status);
cfi.c:449cfi_read_intel_pri_ext()
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
cfi.c:462cfi_read_intel_pri_ext()
LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
cfi.c:475cfi_read_intel_pri_ext()
LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
cfi.c:497cfi_read_intel_pri_ext()
LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
cfi.c:550cfi_read_spansion_pri_ext()
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
cfi.c:587cfi_read_spansion_pri_ext()
LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
cfi.c:590cfi_read_spansion_pri_ext()
LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
cfi.c:594cfi_read_spansion_pri_ext()
LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->burst_mode, pri_ext->page_mode);
cfi.c:597cfi_read_spansion_pri_ext()
LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
cfi.c:601cfi_read_spansion_pri_ext()
LOG_DEBUG("WP# protection 0x%x", pri_ext->top_bottom);
cfi.c:660cfi_read_atmel_pri_ext()
LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
cfi.c:680cfi_read_atmel_pri_ext()
LOG_DEBUG(
cfi.c:1288cfi_intel_write_block()
LOG_DEBUG("Using target buffer at " TARGET_ADDR_FMT " and of size 0x%04" PRIx32,
cfi.c:1308cfi_intel_write_block()
LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32,
cfi.c:2195cfi_write_words()
LOG_DEBUG("Buffer Writes Not Supported");
cfi.c:2222cfi_read()
LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
cfi.c:2467cfi_fixup_0002_erase_regions()
LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
cfi.c:2518cfi_query_string()
LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
cfi.c:2652cfi_probe()
LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
cfi.c:2711cfi_probe()
LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
cfi.c:2725cfi_probe()
LOG_DEBUG(
cfi.c:2767cfi_probe()
LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
cfi.c:2773cfi_probe()
LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
cfi.c:2778cfi_probe()
LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
cfi.c:2795cfi_probe()
LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
chibios.c:248chibios_update_stacking()
LOG_DEBUG("Enabled FPU detected.");
chromium-ec.c:93chromium_ec_detect_rtos()
LOG_DEBUG("Chromium-EC: Symbol \"%s\" found",
chromium-ec.c:207chromium_ec_update_threads()
LOG_DEBUG("Current task: %lx tasks_found: %d",
cmsis_dap.c:329cmsis_dap_flush_read()
LOG_DEBUG("Flushed %u packets", i);
cmsis_dap.c:575cmsis_dap_metacmd_targetsel()
LOG_DEBUG_IO("DP write reg TARGETSEL %" PRIx32, instance_id);
cmsis_dap.c:790cmsis_dap_swd_write_from_queue()
LOG_DEBUG_IO("Executing %d queued transactions from FIFO index %u%s",
cmsis_dap.c:795cmsis_dap_swd_write_from_queue()
LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
cmsis_dap.c:825cmsis_dap_swd_write_from_queue()
LOG_DEBUG_IO("%s %s reg %x %" PRIx32,
cmsis_dap.c:845cmsis_dap_swd_write_from_queue()
LOG_DEBUG("refusing to enable sticky overrun detection");
cmsis_dap.c:909cmsis_dap_swd_read_process()
LOG_DEBUG("error reading adapter response");
cmsis_dap.c:939cmsis_dap_swd_read_process()
LOG_DEBUG("CMSIS-DAP Protocol Error @ %d (wrong parity)", transfer_count);
cmsis_dap.c:945cmsis_dap_swd_read_process()
LOG_DEBUG("SWD ack not OK @ %d %s", transfer_count,
cmsis_dap.c:960cmsis_dap_swd_read_process()
LOG_DEBUG_IO("Received results of %d queued transactions FIFO index %u, %s mode",
cmsis_dap.c:972cmsis_dap_swd_read_process()
LOG_DEBUG_IO("Read result: %" PRIx32, data);
cmsis_dap.c:1247cmsis_dap_swd_switch_seq()
LOG_DEBUG_IO("SWD line reset");
cmsis_dap.c:1252cmsis_dap_swd_switch_seq()
LOG_DEBUG("JTAG-to-SWD");
cmsis_dap.c:1257cmsis_dap_swd_switch_seq()
LOG_DEBUG("JTAG-to-DORMANT");
cmsis_dap.c:1262cmsis_dap_swd_switch_seq()
LOG_DEBUG("SWD-to-JTAG");
cmsis_dap.c:1267cmsis_dap_swd_switch_seq()
LOG_DEBUG("SWD-to-DORMANT");
cmsis_dap.c:1272cmsis_dap_swd_switch_seq()
LOG_DEBUG("DORMANT-to-SWD");
cmsis_dap.c:1277cmsis_dap_swd_switch_seq()
LOG_DEBUG("DORMANT-to-JTAG");
cmsis_dap.c:1369cmsis_dap_init()
LOG_DEBUG("CMSIS-DAP: Packet Size = %" PRIu16, pkt_sz);
cmsis_dap.c:1393cmsis_dap_init()
LOG_DEBUG("CMSIS-DAP: Packet Count = %u", pkt_cnt);
cmsis_dap.c:1396cmsis_dap_init()
LOG_DEBUG("Allocating FIFO for %u pending packets", cmsis_dap_handle->packet_count);
cmsis_dap.c:1510cmsis_dap_execute_tlr_reset()
tap_set_state(TAP_RESET);
cmsis_dap.c:1597cmsis_dap_flush()
LOG_DEBUG_IO("Flushing %d queued sequences (%d bytes) with %d pending scan results to capture",
cmsis_dap.c:1629cmsis_dap_flush()
LOG_DEBUG_IO("Copying pending_scan_result %d/%d: %d bits from byte %d -> buffer + %d bits",
cmsis_dap.c:1655cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO("[at %d] %u bits, tms %s, seq offset %u, tdo buf %p, tdo offset %u",
cmsis_dap.c:1663cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO("START JTAG SEQ SPLIT");
cmsis_dap.c:1668cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO("Splitting long jtag sequence: %u-bit chunk starting at offset %u", len, offset);
cmsis_dap.c:1678cmsis_dap_add_jtag_sequence()
LOG_DEBUG_IO("END JTAG SEQ SPLIT");
cmsis_dap.c:1715cmsis_dap_add_tms_sequence()
LOG_DEBUG_IO("%d bits: %02X", s_len, *sequence);
cmsis_dap.c:1733cmsis_dap_state_move()
LOG_DEBUG_IO("state move from %s to %s: %d clocks, %02X on tms",
cmsis_dap.c:1738cmsis_dap_state_move()
tap_set_state(tap_get_end_state());
cmsis_dap.c:1745cmsis_dap_execute_scan()
LOG_DEBUG_IO("%s type:%d", cmd->cmd.scan->ir_scan ? "IRSCAN" : "DRSCAN",
cmsis_dap.c:1752cmsis_dap_execute_scan()
LOG_DEBUG("discarding trailing empty field");
cmsis_dap.c:1756cmsis_dap_execute_scan()
LOG_DEBUG("empty scan, doing nothing");
cmsis_dap.c:1779cmsis_dap_execute_scan()
LOG_DEBUG_IO("%s%s field %u/%u %u bits",
cmsis_dap.c:1787cmsis_dap_execute_scan()
LOG_DEBUG_IO("Last field and have to move out of SHIFT state");
cmsis_dap.c:1809cmsis_dap_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 1));
cmsis_dap.c:1819cmsis_dap_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 0));
cmsis_dap.c:1821cmsis_dap_execute_scan()
LOG_DEBUG_IO("Internal field, staying in SHIFT state afterwards");
cmsis_dap.c:1839cmsis_dap_execute_scan()
LOG_DEBUG_IO("%s scan, %i bits, end in %s",
cmsis_dap.c:1860cmsis_dap_pathmove()
tap_set_state(path[i]);
cmsis_dap.c:1868cmsis_dap_execute_pathmove()
LOG_DEBUG_IO("pathmove: %i states, end in %i",
cmsis_dap.c:1904cmsis_dap_execute_runtest()
LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles,
cmsis_dap.c:1913cmsis_dap_execute_stableclocks()
LOG_DEBUG_IO("stableclocks %u cycles", cmd->cmd.runtest->num_cycles);
cmsis_dap.c:1919cmsis_dap_execute_tms()
LOG_DEBUG_IO("TMS: %u bits", cmd->cmd.tms->num_bits);
cmsis_dap_usb_bulk.c:124cmsis_dap_usb_open()
LOG_DEBUG("could not open device 0x%04x:0x%04x: %s",
cmsis_dap_usb_bulk.c:145cmsis_dap_usb_open()
LOG_DEBUG(msg, dev_desc.idVendor, dev_desc.idProduct,
cmsis_dap_usb_bulk.c:169cmsis_dap_usb_open()
LOG_DEBUG("found product string of 0x%04x:0x%04x '%s'",
cmsis_dap_usb_bulk.c:189cmsis_dap_usb_open()
LOG_DEBUG("enumerating interfaces of 0x%04x:0x%04x",
cmsis_dap_usb_bulk.c:230cmsis_dap_usb_open()
LOG_DEBUG("could not read interface string %d for device 0x%04x:0x%04x: %s",
cmsis_dap_usb_bulk.c:236cmsis_dap_usb_open()
LOG_DEBUG("found interface %d string '%s'",
cmsis_dap_usb_bulk.c:249cmsis_dap_usb_open()
LOG_DEBUG("skipping interface %d, has only %d endpoints",
cmsis_dap_usb_bulk.c:256cmsis_dap_usb_open()
LOG_DEBUG("skipping interface %d, endpoint[0] is not bulk out",
cmsis_dap_usb_bulk.c:263cmsis_dap_usb_open()
LOG_DEBUG("skipping interface %d, endpoint[1] is not bulk in",
cmsis_dap_usb_bulk.c:295cmsis_dap_usb_open()
LOG_DEBUG("skipping interface %d, class %" PRId8
cmsis_dap_usb_hid.c:98cmsis_dap_hid_open()
LOG_DEBUG("Cannot read product string of device 0x%x:0x%x",
command.c:143script_debug()
if (debug_level < LOG_LVL_DEBUG)
command.c:153script_debug()
LOG_DEBUG("%s", dbg);
command.c:259register_command()
LOG_DEBUG("command '%s' is already registered", full_name);
command.c:271register_command()
LOG_DEBUG("registering '%s'...", full_name);
command.c:370unregister_commands_match()
LOG_DEBUG("delete command \"%s\"", name);
command.c:528exec_command()
LOG_DEBUG("Command '%s' failed with error code %d",
commands.c:199jtag_build_buffer()
LOG_DEBUG_IO("%s num_fields: %u",
commands.c:205jtag_build_buffer()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) {
commands.c:211jtag_build_buffer()
LOG_DEBUG("fields[%u].out_value[%u]: 0x%s", i,
commands.c:218jtag_build_buffer()
LOG_DEBUG_IO("fields[%u].out_value[%u]: NULL",
commands.c:247jtag_read_buffer()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) {
commands.c:253jtag_read_buffer()
LOG_DEBUG("fields[%u].in_value[%u]: 0x%s",
configuration.c:33add_script_search_dir()
LOG_DEBUG("adding %s", dir);
configuration.c:88find_file()
LOG_DEBUG("found %s", full_path);
core.c:314nand_probe()
LOG_DEBUG("controller initialization failed");
core.c:372nand_probe()
LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
core.c:474nand_probe()
LOG_DEBUG("controller initialization failed");
core.c:107flash_driver_read()
LOG_DEBUG("call flash_driver_read()");
core.c:156default_flash_verify()
LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
core.c:596flash_iterate_address_range()
LOG_DEBUG("iterating over more than one flash bank.");
core.c:856flash_write_unlock_verify()
LOG_DEBUG("Truncate flash run size to the current flash chip.");
core.c:939flash_write_unlock_verify()
LOG_DEBUG("image_read_section: section = %d, t_section_num = %d, "
core.c:328jtag_call_event_callbacks()
LOG_DEBUG("jtag event: %s", jtag_event_strings[event]);
core.c:556jtag_add_statemove()
LOG_DEBUG("cur_state=%s goal_state=%s",
core.c:636adapter_system_reset()
LOG_DEBUG("SRST line asserted");
core.c:640adapter_system_reset()
LOG_DEBUG("SRST line released");
core.c:714legacy_jtag_add_reset()
LOG_DEBUG("SRST line asserted");
core.c:718legacy_jtag_add_reset()
LOG_DEBUG("SRST line released");
core.c:731legacy_jtag_add_reset()
LOG_DEBUG("JTAG reset with TLR instead of TRST");
core.c:737legacy_jtag_add_reset()
LOG_DEBUG("TRST line asserted");
core.c:738legacy_jtag_add_reset()
tap_set_state(TAP_RESET);
core.c:742legacy_jtag_add_reset()
LOG_DEBUG("TRST line released");
core.c:826jtag_add_reset()
LOG_DEBUG("SRST line asserted");
core.c:830jtag_add_reset()
LOG_DEBUG("SRST line released");
core.c:843jtag_add_reset()
LOG_DEBUG("JTAG reset with TLR instead of TRST");
core.c:850jtag_add_reset()
LOG_DEBUG("TRST line asserted");
core.c:851jtag_add_reset()
tap_set_state(TAP_RESET);
core.c:855jtag_add_reset()
LOG_DEBUG("TRST line released");
core.c:957default_interface_jtag_execute_queue()
while (debug_level >= LOG_LVL_DEBUG_IO && cmd) {
core.c:960default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG %s SCAN to %s",
core.c:967default_interface_jtag_execute_queue()
LOG_DEBUG_IO(" %ub out: %s", field->num_bits, str);
core.c:972default_interface_jtag_execute_queue()
LOG_DEBUG_IO(" %ub in: %s", field->num_bits, str);
core.c:978default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG TLR RESET to %s",
core.c:982default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG RUNTEST %d cycles to %s",
core.c:991default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG RESET %s TRST, %s SRST",
core.c:997default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG PATHMOVE (TODO)");
core.c:1000default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG SLEEP (TODO)");
core.c:1003default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG STABLECLOCKS (TODO)");
core.c:1006default_interface_jtag_execute_queue()
LOG_DEBUG_IO("JTAG TMS (TODO)");
core.c:1235jtag_examine_chain()
LOG_DEBUG("DR scan interrogation for IDCODE/BYPASS");
core.c:1365jtag_validate_ircapture()
LOG_DEBUG("IR capture validation scan");
core.c:1422jtag_validate_ircapture()
LOG_DEBUG("%s: IR capture 0x%0*" PRIx64, jtag_tap_name(tap),
core.c:1475jtag_tap_init()
LOG_DEBUG("Created Tap: %s @ abs position %u, "
core.c:1510jtag_init_inner()
LOG_DEBUG("Init JTAG chain");
core.c:1592swd_init_reset()
LOG_DEBUG("Initializing with hard SRST reset");
core.c:1607jtag_init_reset()
LOG_DEBUG("Initializing with hard TRST+SRST reset");
cortex_a.c:193cortex_a_mmu_modify()
LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32,
cortex_a.c:292cortex_a_exec_opcode()
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
cortex_a.c:335cortex_a_write_dcc()
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
cortex_a.c:598cortex_a_bpwp_enable()
LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
cortex_a.c:628cortex_a_bpwp_disable()
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
cortex_a.c:764cortex_a_poll()
LOG_DEBUG("Target halted");
cortex_a.c:881cortex_a_internal_restore()
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
cortex_a.c:1012cortex_a_resume()
LOG_DEBUG("target resumed at " TARGET_ADDR_FMT, address);
cortex_a.c:1016cortex_a_resume()
LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT, address);
cortex_a.c:1030cortex_a_debug_entry()
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
cortex_a.c:1114cortex_a_post_debug_entry()
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
cortex_a.c:1141cortex_a_post_debug_entry()
LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
cortex_a.c:1258cortex_a_step()
LOG_DEBUG("target stepped");
cortex_a.c:1267cortex_a_restore_context()
LOG_DEBUG(" ");
cortex_a.c:1322cortex_a_set_breakpoint()
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1414cortex_a_set_context_breakpoint()
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1444cortex_a_set_hybrid_breakpoint()
LOG_DEBUG("brp(CTX) found num: %d", brp_1);
cortex_a.c:1454cortex_a_set_hybrid_breakpoint()
LOG_DEBUG("brp(IVA) found num: %d", brp_2);
cortex_a.c:1519cortex_a_unset_breakpoint()
LOG_DEBUG("Invalid BRP number in breakpoint");
cortex_a.c:1522cortex_a_unset_breakpoint()
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1538cortex_a_unset_breakpoint()
LOG_DEBUG("Invalid BRP number in breakpoint");
cortex_a.c:1541cortex_a_unset_breakpoint()
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
cortex_a.c:1563cortex_a_unset_breakpoint()
LOG_DEBUG("Invalid BRP number in breakpoint");
cortex_a.c:1566cortex_a_unset_breakpoint()
LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1784cortex_a_set_watchpoint()
LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
cortex_a.c:1813cortex_a_unset_watchpoint()
LOG_DEBUG("Invalid WRP number in watchpoint");
cortex_a.c:1816cortex_a_unset_watchpoint()
LOG_DEBUG("wrp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
cortex_a.c:1889cortex_a_assert_reset()
LOG_DEBUG(" ");
cortex_a.c:1930cortex_a_deassert_reset()
LOG_DEBUG(" ");
cortex_a.c:2254cortex_a_write_cpu_memory()
LOG_DEBUG("Writing CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
cortex_a.c:2571cortex_a_read_cpu_memory()
LOG_DEBUG("Reading CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
cortex_a.c:2720cortex_a_read_phys_memory()
LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2737cortex_a_read_memory()
LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2756cortex_a_write_phys_memory()
LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2773cortex_a_write_memory()
LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2928cortex_a_examine_first()
LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
cortex_a.c:2938cortex_a_examine_first()
LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
cortex_a.c:2950cortex_a_examine_first()
LOG_DEBUG("Examine %s failed", "DIDR");
cortex_a.c:2957cortex_a_examine_first()
LOG_DEBUG("Examine %s failed", "CPUID");
cortex_a.c:2961cortex_a_examine_first()
LOG_DEBUG("didr = 0x%08" PRIx32, didr);
cortex_a.c:2962cortex_a_examine_first()
LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
cortex_a.c:2971cortex_a_examine_first()
LOG_TARGET_DEBUG(target, "DBGPRSR 0x%" PRIx32, dbg_osreg);
cortex_a.c:2980cortex_a_examine_first()
LOG_TARGET_DEBUG(target, "was reset!");
cortex_a.c:2987cortex_a_examine_first()
LOG_TARGET_DEBUG(target, "DBGOSLSR 0x%" PRIx32, dbg_osreg);
cortex_a.c:2993cortex_a_examine_first()
LOG_TARGET_DEBUG(target, "OSLock set! Trying to unlock");
cortex_a.c:3017cortex_a_examine_first()
LOG_TARGET_DEBUG(target, "has security extensions");
cortex_a.c:3021cortex_a_examine_first()
LOG_TARGET_DEBUG(target, "has virtualization extensions");
cortex_a.c:3054cortex_a_examine_first()
LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
cortex_a.c:3068cortex_a_examine_first()
LOG_DEBUG("Configured %i hw watchpoints", cortex_a->wrp_num);
cortex_m.c:251cortex_m_slow_read_all_regs()
LOG_TARGET_DEBUG(target, "Switching back to fast register reads");
cortex_m.c:348cortex_m_fast_read_all_regs()
LOG_TARGET_DEBUG(target, "Register %u was not ready during fast read", i);
cortex_m.c:359cortex_m_fast_read_all_regs()
LOG_TARGET_DEBUG(target, "read %u 32-bit registers", wi);
cortex_m.c:557cortex_m_clear_halt()
LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
cortex_m.c:579cortex_m_single_step_core()
LOG_TARGET_DEBUG(target, "single step");
cortex_m.c:619cortex_m_endreset_event()
LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
cortex_m.c:800cortex_m_examine_exception_reason()
LOG_TARGET_DEBUG(target, "%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
cortex_m.c:823cortex_m_erratum_check_breakpoint()
LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint confirmed");
cortex_m.c:836cortex_m_erratum_check_breakpoint()
LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint embedded in code confirmed");
cortex_m.c:839cortex_m_erratum_check_breakpoint()
LOG_TARGET_DEBUG(target, "Erratum 3092511: breakpoint not found, proceed with resume");
cortex_m.c:852cortex_m_debug_entry()
LOG_TARGET_DEBUG(target, " ");
cortex_m.c:881cortex_m_debug_entry()
LOG_TARGET_DEBUG(target, "Switched to slow register read");
cortex_m.c:922cortex_m_debug_entry()
LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
cortex_m.c:1000cortex_m_poll_one()
LOG_TARGET_DEBUG(target, "Exit from reset with dcb_dhcsr 0x%" PRIx32,
cortex_m.c:1044cortex_m_poll_one()
LOG_TARGET_DEBUG(target, "postpone target event 'halted'");
cortex_m.c:1159cortex_m_poll_smp()
LOG_TARGET_DEBUG(curr, "sending postponed target event 'halted'");
cortex_m.c:1191cortex_m_halt_one()
LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
cortex_m.c:1199cortex_m_halt_one()
LOG_TARGET_DEBUG(target, "target was already halted");
cortex_m.c:1236cortex_m_soft_reset_halt()
LOG_TARGET_DEBUG(target, "soft_reset_halt is discouraged, please use 'reset halt' instead.");
cortex_m.c:1273cortex_m_soft_reset_halt()
LOG_TARGET_DEBUG(target, "system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
cortex_m.c:1279cortex_m_soft_reset_halt()
LOG_TARGET_DEBUG(target, "waiting for system reset-halt, "
cortex_m.c:1380cortex_m_restore_one()
LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
cortex_m.c:1444cortex_m_restore_smp()
LOG_TARGET_DEBUG(curr, "SMP resumed at " TARGET_ADDR_FMT, address);
cortex_m.c:1470cortex_m_resume()
LOG_TARGET_DEBUG(target, "%sresumed at " TARGET_ADDR_FMT,
cortex_m.c:1567cortex_m_step()
LOG_TARGET_DEBUG(target, "Stepping over next instruction with interrupts disabled");
cortex_m.c:1598cortex_m_step()
LOG_TARGET_DEBUG(target, "Starting core to serve pending interrupts");
cortex_m.c:1622cortex_m_step()
LOG_TARGET_DEBUG(target, "Interrupt handlers didn't complete within time, "
cortex_m.c:1657cortex_m_step()
LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
cortex_m.c:1666cortex_m_step()
LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
cortex_m.c:1838cortex_m_assert_reset()
LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
cortex_m.c:1872cortex_m_assert_reset()
LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
cortex_m.c:1957cortex_m_assert_reset()
LOG_TARGET_DEBUG(target, "Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
cortex_m.c:1970cortex_m_assert_reset()
LOG_TARGET_DEBUG(target, "Ignoring AP write error right after reset");
cortex_m.c:2000cortex_m_deassert_reset()
LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
cortex_m.c:2062cortex_m_set_breakpoint()
LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
cortex_m.c:2066cortex_m_set_breakpoint()
LOG_TARGET_DEBUG(target, "FPB wasn't enabled, do it now");
cortex_m.c:2098cortex_m_set_breakpoint()
LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (n=%u)",
cortex_m.c:2119cortex_m_unset_breakpoint()
LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (n=%u)",
cortex_m.c:2129cortex_m_unset_breakpoint()
LOG_TARGET_DEBUG(target, "Invalid FP Comparator number in breakpoint");
cortex_m.c:2152cortex_m_add_breakpoint()
LOG_TARGET_DEBUG(target, "Using a two byte breakpoint for 32bit Thumb-2 request");
cortex_m.c:2248cortex_m_set_watchpoint()
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
cortex_m.c:2269cortex_m_unset_watchpoint()
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%u address: 0x%08x clear",
cortex_m.c:2274cortex_m_unset_watchpoint()
LOG_TARGET_DEBUG(target, "Invalid DWT Comparator number in watchpoint");
cortex_m.c:2294cortex_m_add_watchpoint()
LOG_TARGET_DEBUG(target, "no comparators?");
cortex_m.c:2306cortex_m_add_watchpoint()
LOG_TARGET_DEBUG(target, "watchpoint value masks not supported");
cortex_m.c:2318cortex_m_add_watchpoint()
LOG_TARGET_DEBUG(target, "unsupported watchpoint length");
cortex_m.c:2322cortex_m_add_watchpoint()
LOG_TARGET_DEBUG(target, "watchpoint address is unaligned");
cortex_m.c:2327cortex_m_add_watchpoint()
LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
cortex_m.c:2346cortex_m_remove_watchpoint()
LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
cortex_m.c:2614cortex_m_dwt_setup()
LOG_TARGET_DEBUG(target, "DWT_CTRL: 0x%" PRIx32, dwtcr);
cortex_m.c:2616cortex_m_dwt_setup()
LOG_TARGET_DEBUG(target, "no DWT");
cortex_m.c:2621cortex_m_dwt_setup()
LOG_TARGET_DEBUG(target, "DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
cortex_m.c:2668cortex_m_dwt_setup()
LOG_TARGET_DEBUG(target, "DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
cortex_m.c:2820cortex_m_examine()
LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
cortex_m.c:2827cortex_m_examine()
LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found",
cortex_m.c:2838cortex_m_examine()
LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP + MVE-F found",
cortex_m.c:2842cortex_m_examine()
LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found",
cortex_m.c:2847cortex_m_examine()
LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found",
cortex_m.c:2851cortex_m_examine()
LOG_TARGET_DEBUG(target, "%s floating point feature MVE-I found",
cortex_m.c:2889cortex_m_examine()
LOG_TARGET_DEBUG(target, "reset happened some time ago, ignore");
cortex_m.c:2936cortex_m_examine()
LOG_TARGET_DEBUG(target, "FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
cortex_m.c:2969cortex_m_dcc_read()
LOG_TARGET_DEBUG(target, "data 0x%x ctrl 0x%x", *value, *ctrl);
dsp563xx.c:404dsp563xx_get_core_reg()
LOG_DEBUG("%s", __func__);
dsp563xx.c:414dsp563xx_set_core_reg()
LOG_DEBUG("%s", __func__);
dsp563xx.c:571dsp563xx_reg_pc_read()
LOG_DEBUG("%s conditional branch not supported yet (0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 ")",
dsp563xx.c:900dsp563xx_init_target()
LOG_DEBUG("%s", __func__);
dsp563xx.c:940dsp563xx_arch_state()
LOG_DEBUG("%s", __func__);
dsp563xx.c:1070dsp563xx_poll()
LOG_DEBUG("target->state: %s (%" PRIx32 ")", target_state_name(target), once_status);
dsp563xx.c:1098dsp563xx_halt()
LOG_DEBUG("%s", __func__);
dsp563xx.c:1101dsp563xx_halt()
LOG_DEBUG("target was already halted");
dsp563xx.c:1138dsp563xx_resume()
LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
dsp563xx.c:1186dsp563xx_step_ex()
LOG_DEBUG("target was not halted");
dsp563xx.c:1202dsp563xx_step_ex()
LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
dsp563xx.c:1263dsp563xx_step_ex()
LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff);
dsp563xx.c:1267dsp563xx_step_ex()
LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff);
dsp563xx.c:1271dsp563xx_step_ex()
LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff);
dsp563xx.c:1341dsp563xx_assert_reset()
LOG_DEBUG("%s", __func__);
dsp563xx.c:1369dsp563xx_deassert_reset()
LOG_DEBUG("%s", __func__);
dsp563xx.c:1519dsp563xx_read_memory_core()
LOG_DEBUG(
dsp563xx.c:1614dsp563xx_read_memory()
LOG_DEBUG("size is not aligned to 4 byte");
dsp563xx.c:1700dsp563xx_write_memory_core()
LOG_DEBUG(
dsp563xx.c:1788dsp563xx_write_memory()
LOG_DEBUG("size is not aligned to 4 byte");
dsp563xx_once.c:135dsp563xx_once_request_debug()
LOG_DEBUG("debug request: %02X", ir_in);
dsp563xx_once.c:156dsp563xx_once_request_debug()
LOG_DEBUG("enable once: %02X", ir_in);
dsp563xx_once.c:159dsp563xx_once_request_debug()
LOG_DEBUG("error");
dsp5680xx.c:97dsp5680xx_drscan()
LOG_DEBUG("Data read (%d bits): 0x%04X", len, *d_out);
dsp5680xx.c:99dsp5680xx_drscan()
LOG_DEBUG("Data read was discarded.");
dsp5680xx.c:177jtag_data_read()
LOG_DEBUG("Data read (%d bits): 0x%04X", num_bits, *data_read);
dsp5680xx.c:529dsp5680xx_read_core_reg()
LOG_DEBUG("Reg. data: 0x%02X.", *data_read);
dsp5680xx.c:676eonce_enter_debug_mode_without_reset()
LOG_DEBUG("EOnCE successfully entered debug mode.");
dsp5680xx.c:816eonce_enter_debug_mode()
LOG_DEBUG("EOnCE successfully entered debug mode.");
dsp5680xx.c:872dsp5680xx_init_target()
LOG_DEBUG("target initiated!");
dsp5680xx.c:1031dsp5680xx_resume()
LOG_DEBUG("EOnCE status: 0x%02X.", eonce_status);
dsp5680xx.c:1109dsp5680xx_read_16_single()
LOG_DEBUG("%s:Data read from 0x%06" PRIX32 ": 0x%02X%02X", __func__, address,
dsp5680xx.c:1731set_fm_ck_div()
LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",
dsp5680xx.c:1735set_fm_ck_div()
LOG_DEBUG
dsp5680xx.c:1756set_fm_ck_div()
LOG_DEBUG("HFM CLK divisor set to 0x%02x.", i[0] & 0x7f);
dsp5680xx_flash.c:157dsp5680xx_probe()
LOG_DEBUG("%s not implemented", __func__);
eCos.c:542ecos_check_app_info()
if (debug_level >= LOG_LVL_DEBUG) {
eCos.c:544ecos_check_app_info()
LOG_DEBUG("eCos: %s 0x%016" PRIX64 " %s",
efm32.c:433efm32x_wait_status()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
efm32.c:465efm32x_erase_page()
LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
efm32.c:480efm32x_erase_page()
LOG_DEBUG("status 0x%" PRIx32, status);
efm32.c:923efm32x_write_word()
LOG_DEBUG("status 0x%" PRIx32, status);
em357.c:118em357_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
embeddedice.c:505embeddedice_write_reg()
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
eneispif.c:51eneispif_flash_bank_command()
LOG_DEBUG("%s", __func__);
eneispif.c:85eneispif_read_reg()
LOG_DEBUG("Read address " TARGET_ADDR_FMT " = 0x%" PRIx32,
eneispif.c:95eneispif_write_reg()
LOG_DEBUG("Write address " TARGET_ADDR_FMT " = 0x%" PRIx32,
eneispif.c:166eneispif_erase()
LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
eneispif.c:219eneispif_write()
LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32, bank->size, offset,
eneispif.c:305eneispif_read_flash_id()
LOG_DEBUG("ISPCFG = (0x%08" PRIx32 ")", conf);
eneispif.c:321eneispif_read_flash_id()
LOG_DEBUG("ISPDAT = (0x%08" PRIx32 ")", value);
esirisc.c:163esirisc_disable_interrupts()
LOG_DEBUG("-");
esirisc.c:215esirisc_save_interrupts()
LOG_DEBUG("-");
esirisc.c:232esirisc_restore_interrupts()
LOG_DEBUG("-");
esirisc.c:268esirisc_restore_hwdc()
LOG_DEBUG("-");
esirisc.c:284esirisc_save_context()
LOG_DEBUG("-");
esirisc.c:301esirisc_restore_context()
LOG_DEBUG("-");
esirisc.c:319esirisc_flush_caches()
LOG_DEBUG("-");
esirisc.c:340esirisc_wait_debug_active()
LOG_DEBUG("-");
esirisc.c:362esirisc_read_memory()
LOG_DEBUG("-");
esirisc.c:411esirisc_write_memory()
LOG_DEBUG("-");
esirisc.c:463esirisc_next_breakpoint()
LOG_DEBUG("-");
esirisc.c:480esirisc_add_breakpoint()
LOG_DEBUG("-");
esirisc.c:531esirisc_add_breakpoints()
LOG_DEBUG("-");
esirisc.c:551esirisc_remove_breakpoint()
LOG_DEBUG("-");
esirisc.c:579esirisc_remove_breakpoints()
LOG_DEBUG("-");
esirisc.c:599esirisc_next_watchpoint()
LOG_DEBUG("-");
esirisc.c:616esirisc_add_watchpoint()
LOG_DEBUG("-");
esirisc.c:715esirisc_add_watchpoints()
LOG_DEBUG("-");
esirisc.c:735esirisc_remove_watchpoint()
LOG_DEBUG("-");
esirisc.c:763esirisc_remove_watchpoints()
LOG_DEBUG("-");
esirisc.c:782esirisc_halt()
LOG_DEBUG("-");
esirisc.c:805esirisc_disable_step()
LOG_DEBUG("-");
esirisc.c:831esirisc_enable_step()
LOG_DEBUG("-");
esirisc.c:858esirisc_resume_or_step()
LOG_DEBUG("-");
esirisc.c:924esirisc_resume()
LOG_DEBUG("-");
esirisc.c:933esirisc_step()
LOG_DEBUG("-");
esirisc.c:945esirisc_debug_step()
LOG_DEBUG("-");
esirisc.c:974esirisc_debug_reset()
LOG_DEBUG("-");
esirisc.c:1003esirisc_debug_enable()
LOG_DEBUG("-");
esirisc.c:1037esirisc_debug_entry()
LOG_DEBUG("-");
esirisc.c:1125esirisc_assert_reset()
LOG_DEBUG("-");
esirisc.c:1156esirisc_reset_entry()
LOG_DEBUG("-");
esirisc.c:1189esirisc_deassert_reset()
LOG_DEBUG("-");
esirisc.c:1255esirisc_get_gdb_arch()
LOG_DEBUG("-");
esirisc.c:1275esirisc_get_gdb_reg_list()
LOG_DEBUG("-");
esirisc.c:1305esirisc_read_reg()
LOG_DEBUG("-");
esirisc.c:1328esirisc_write_reg()
LOG_DEBUG("-");
esirisc.c:1350esirisc_read_csr()
LOG_DEBUG("-");
esirisc.c:1373esirisc_write_csr()
LOG_DEBUG("-");
esirisc.c:1393esirisc_get_reg()
LOG_DEBUG("-");
esirisc.c:1408esirisc_set_reg()
LOG_DEBUG("-");
esirisc.c:1432esirisc_build_reg_cache()
LOG_DEBUG("-");
esirisc.c:1522esirisc_identify()
LOG_DEBUG("-");
esirisc.c:1632esirisc_examine()
LOG_DEBUG("-");
esirisc_flash.c:421esirisc_flash_init()
LOG_DEBUG("TIMING0: 0x%" PRIx32, value);
esirisc_flash.c:426esirisc_flash_init()
LOG_DEBUG("TIMING1: 0x%" PRIx32, value);
esirisc_flash.c:433esirisc_flash_init()
LOG_DEBUG("TIMING2: 0x%" PRIx32, value);
esirisc_jtag.c:260esirisc_jtag_read_byte()
LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx8, address, *data);
esirisc_jtag.c:288esirisc_jtag_read_hword()
LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx16, address, *data);
esirisc_jtag.c:316esirisc_jtag_read_word()
LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, *data);
esirisc_jtag.c:326esirisc_jtag_write_byte()
LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx8, address, data);
esirisc_jtag.c:346esirisc_jtag_write_hword()
LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx16, address, data);
esirisc_jtag.c:367esirisc_jtag_write_word()
LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data);
esirisc_jtag.c:404esirisc_jtag_read_reg()
LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, *data);
esirisc_jtag.c:414esirisc_jtag_write_reg()
LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, data);
esirisc_jtag.c:452esirisc_jtag_read_csr()
LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, *data);
esirisc_jtag.c:462esirisc_jtag_write_csr()
LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, data);
esp.c:33esp_dbgstubs_table_read()
LOG_TARGET_DEBUG(target, "Read debug stubs info %" PRIx32 " / %d", dbg_stubs->base, dbg_stubs->entries_count);
esp.c:77esp_dbgstubs_table_read()
LOG_DEBUG("Check dbg stub %d - %x", i, dbg_stubs->entries[i]);
esp.c:79esp_dbgstubs_table_read()
LOG_DEBUG("New dbg stub %d at %x", dbg_stubs->entries_count, dbg_stubs->entries[i]);
esp32.c:102esp32_soc_reset()
LOG_DEBUG("start");
esp32.c:105esp32_soc_reset()
LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
esp32.c:109esp32_soc_reset()
LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
esp32.c:145esp32_soc_reset()
LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
esp32.c:158esp32_soc_reset()
LOG_DEBUG("Loading stub code into RTC RAM");
esp32.c:175esp32_soc_reset()
LOG_DEBUG("Resuming the target");
esp32.c:184esp32_soc_reset()
LOG_DEBUG("resume done, waiting for the target to come alive");
esp32.c:202esp32_soc_reset()
LOG_DEBUG("halting the target");
esp32.c:206esp32_soc_reset()
LOG_DEBUG("restoring RTC_SLOW_MEM");
esp32_apptrace.c:222esp32_apptrace_tcp_dest_init()
LOG_DEBUG("apptrace: Failed to create socket (%d, %d, %d) (%s)",
esp32_apptrace.c:353esp32_apptrace_ready_block_put()
LOG_DEBUG("esp32_apptrace_ready_block_put");
esp32_apptrace.c:386esp32_apptrace_wait_tracing_finished()
int64_t timeout = timeval_ms() + (LOG_LEVEL_IS(LOG_LVL_DEBUG) ? 70000 : 5000);
esp32_apptrace.c:667esp32_apptrace_safe_halt_targets()
LOG_DEBUG("Halt all targets!");
esp32_apptrace.c:688esp32_apptrace_safe_halt_targets()
LOG_DEBUG("Read current block statuses");
esp32_apptrace.c:792esp32_apptrace_connect_targets()
LOG_DEBUG("Resume targets");
esp32_apptrace.c:864esp32_apptrace_get_data_info()
LOG_TARGET_DEBUG(ctx->cpus[i], "Block %" PRId32 ", len %" PRId32 " bytes on fired",
esp32_apptrace.c:881esp32_apptrace_process_data()
LOG_DEBUG("Got block %" PRId32 " bytes [%x %x...%x %x]", data_len, data[12], data[13],
esp32_apptrace.c:922esp32_apptrace_handle_trace_block()
LOG_DEBUG("Got block %" PRId32 " bytes", block->data_len);
esp32_apptrace.c:925esp32_apptrace_handle_trace_block()
LOG_DEBUG("Process usr block %" PRId32 "/%" PRId32, processed, block->data_len);
esp32_apptrace.c:1069esp32_apptrace_poll()
LOG_TARGET_DEBUG(ctx->cpus[i], "Ack empty block %" PRId32 "!", max_block_id);
esp32_apptrace.c:1173esp32_apptrace_poll()
LOG_TARGET_DEBUG(ctx->cpus[i], "Ack block %" PRId32, ctx->last_blk_id);
esp32_apptrace.c:1425esp32_sysview_stop()
const float stop_tmo = LOG_LEVEL_IS(LOG_LVL_DEBUG) ? 30.0 : 0.5;
esp32_sysview.c:321esp_sysview_parse_packet()
LOG_DEBUG("sysview: evt %d len %d plen %d dlen %d",
esp32_sysview.c:421esp32_sysview_process_packet()
LOG_DEBUG("sysview: Redirect %d bytes of event %d to dest %d", wr_len, event_id, i);
esp32_sysview.c:449esp32_sysview_process_data()
LOG_DEBUG("sysview: Read from target %d bytes [%x %x %x %x]",
esp32_sysview.c:469esp32_sysview_process_data()
LOG_DEBUG("sysview: Process %d sync bytes", SYSVIEW_SYNC_LEN);
esp32_sysview.c:513esp32_sysview_process_data()
LOG_DEBUG("sysview: Process packet: core %d, %d id, %d bytes [%x %x %x %x]",
esp32s2.c:88esp32s2_deassert_reset()
LOG_TARGET_DEBUG(target, "begin");
esp32s2.c:106esp32s2_soft_reset_halt()
LOG_TARGET_DEBUG(target, "begin");
esp32s2.c:134esp32s2_stall_set()
LOG_TARGET_DEBUG(target, "begin");
esp32s2.c:183esp32s2_soc_reset()
LOG_DEBUG("start");
esp32s2.c:187esp32s2_soc_reset()
LOG_TARGET_DEBUG(target, "Target not halted before SoC reset, trying to halt it first");
esp32s2.c:191esp32s2_soc_reset()
LOG_TARGET_DEBUG(target, "Couldn't halt target before SoC reset, trying to do reset-halt");
esp32s3.c:99esp32s3_soc_reset()
LOG_DEBUG("start");
esp32s3.c:102esp32s3_soc_reset()
LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
esp32s3.c:106esp32s3_soc_reset()
LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
esp32s3.c:142esp32s3_soc_reset()
LOG_TARGET_DEBUG(head->target, "Unstall CPUs before SW reset!");
esp32s3.c:155esp32s3_soc_reset()
LOG_DEBUG("Loading stub code into RTC RAM");
esp32s3.c:175esp32s3_soc_reset()
LOG_DEBUG("Resuming the target");
esp32s3.c:184esp32s3_soc_reset()
LOG_DEBUG("resume done, waiting for the target to come alive");
esp32s3.c:203esp32s3_soc_reset()
LOG_DEBUG("halting the target");
esp32s3.c:207esp32s3_soc_reset()
LOG_DEBUG("restoring RTC_SLOW_MEM");
esp_algorithm.c:95esp_algorithm_run_image()
LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT,
esp_algorithm.c:117esp_algorithm_run_image()
LOG_DEBUG("Wait algorithm completion");
esp_algorithm.c:136esp_algorithm_run_image()
LOG_DEBUG("Got algorithm RC 0x%" PRIx32, run->ret_code);
esp_algorithm.c:165esp_algorithm_run_debug_stub()
LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT,
esp_algorithm.c:180esp_algorithm_run_debug_stub()
LOG_DEBUG("Wait algorithm completion");
esp_algorithm.c:195esp_algorithm_run_debug_stub()
LOG_DEBUG("Got algorithm RC 0x%" PRIx32, run->ret_code);
esp_algorithm.c:321esp_algorithm_load_func_image()
LOG_DEBUG("stub: base 0x%x, start 0x%" PRIx32 ", %d sections",
esp_algorithm.c:352esp_algorithm_load_func_image()
LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64,
esp_algorithm.c:408esp_algorithm_load_func_image()
LOG_DEBUG("Write reversed tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, al_tramp_size);
esp_algorithm.c:411esp_algorithm_load_func_image()
LOG_DEBUG("Write tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, tramp_sz);
esp_algorithm.c:422esp_algorithm_load_func_image()
LOG_DEBUG("Tramp mapped to addr " TARGET_ADDR_FMT, run->stub.tramp_mapped_addr);
esp_algorithm.c:446esp_algorithm_load_func_image()
LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64, section->base_address, section->size,
esp_algorithm.c:451esp_algorithm_load_func_image()
LOG_DEBUG("DATA sec size %" PRIu32 " -> %" PRIu32, section->size, data_sec_sz);
esp_algorithm.c:453esp_algorithm_load_func_image()
LOG_DEBUG("BSS sec size %" PRIu32 " -> %" PRIu32, run->image.bss_size, bss_sec_sz);
esp_algorithm.c:494esp_algorithm_load_func_image()
LOG_DEBUG("Stub loaded in %g ms", duration_elapsed(&algo_time) * 1000);
esp_algorithm.c:579esp_algorithm_load_onboard_func()
LOG_DEBUG("Stub loaded in %g ms", duration_elapsed(&algo_time) * 1000);
esp_semihosting.c:34esp_semihosting_sys_seek()
LOG_TARGET_DEBUG(target, "lseek(%" PRIx64 ", %" PRIu32 " %" PRId64 ")=%d", fd, pos, semihosting->result, errno);
esp_semihosting.c:57esp_semihosting_common()
LOG_TARGET_DEBUG(target, "op=0x%x, param=0x%" PRIx64, semihosting->op, semihosting->param);
esp_xtensa.c:89esp_xtensa_target_deinit()
LOG_DEBUG("start");
esp_xtensa.c:113esp_xtensa_poll()
LOG_TARGET_DEBUG(target, "Clear debug stubs info");
esp_xtensa_algorithm.c:47esp_xtensa_algo_regs_init_start()
LOG_TARGET_DEBUG(target, "Check stack addr 0x%x", stack_addr);
esp_xtensa_algorithm.c:50esp_xtensa_algo_regs_init_start()
LOG_TARGET_DEBUG(target, "Adjust stack addr to 0x%x", stack_addr);
esp_xtensa_algorithm.c:98esp_xtensa_algo_init()
LOG_DEBUG("reg params count %d (%d/%d).",
esp_xtensa_algorithm.c:116esp_xtensa_algo_init()
LOG_DEBUG("Set arg[0] = %d (%s)", arg, run->reg_args.params[run->reg_args.first_user_param + 0].reg_name);
esp_xtensa_algorithm.c:125esp_xtensa_algo_init()
LOG_DEBUG("Set arg[%d] = %d (%s)", i, arg, run->reg_args.params[run->reg_args.first_user_param + i].reg_name);
esp_xtensa_apptrace.c:83esp_xtensa_apptrace_block_max_size_get()
LOG_DEBUG("ctrl=0x%" PRIx32 " memadrstart=0x%" PRIx32 " memadrend=0x%" PRIx32 " traxadr=0x%" PRIx32,
esp_xtensa_apptrace.c:169esp_xtensa_apptrace_data_read()
LOG_DEBUG("Read data on target (%s)", target_name(target));
esp_xtensa_apptrace.c:177esp_xtensa_apptrace_data_read()
LOG_DEBUG("Ack block %" PRIu32 " target (%s)!", block_id, target_name(target));
esp_xtensa_apptrace.c:487esp_xtensa_apptrace_buffs_write()
LOG_DEBUG("Ack block %" PRId32 " on target (%s)!", block_id, target_name(target));
esp_xtensa_semihosting.c:26esp_xtensa_semihosting_setup()
LOG_TARGET_DEBUG(target, "semihosting enable=%d", enable);
esp_xtensa_semihosting.c:77esp_xtensa_semihosting()
LOG_TARGET_DEBUG(target, "Semihosting call 0x%" PRIx32 " 0x%" PRIx32 " Base dir '%s'",
esp_xtensa_smp.c:75esp_xtensa_smp_deassert_reset()
LOG_TARGET_DEBUG(target, "begin");
esp_xtensa_smp.c:94esp_xtensa_smp_soft_reset_halt()
LOG_TARGET_DEBUG(target, "begin");
esp_xtensa_smp.c:186esp_xtensa_smp_poll()
LOG_TARGET_DEBUG(target, "Check for unexamined cores after reset");
esp_xtensa_smp.c:194esp_xtensa_smp_poll()
LOG_DEBUG("Failed to examine!");
esp_xtensa_smp.c:259esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG("GDB target '%s'", target_name(target->gdb_service->target));
esp_xtensa_smp.c:273esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG("Check target '%s'", target_name(curr));
esp_xtensa_smp.c:287esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG("Poll target '%s'", target_name(curr));
esp_xtensa_smp.c:318esp_xtensa_smp_update_halt_gdb()
LOG_DEBUG("exit");
esp_xtensa_smp.c:343esp_xtensa_smp_resume_cores()
LOG_TARGET_DEBUG(target, "begin");
esp_xtensa_smp.c:370esp_xtensa_smp_resume()
LOG_TARGET_DEBUG(target, "smp_break=0x%" PRIx32, smp_break);
esp_xtensa_smp.c:378esp_xtensa_smp_resume()
LOG_TARGET_DEBUG(target, "Fake resume");
etb.c:209etb_read_reg_w_check()
LOG_DEBUG("%i", (int)(etb_reg->addr));
etb.c:290etb_write_reg()
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
etm.c:325etm_build_reg_cache()
LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
etm.c:501etm_read_reg_w_check()
LOG_DEBUG("%s (%u)", r->name, reg_addr);
etm.c:588etm_write_reg()
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
etm.c:1402handle_etm_config_command()
LOG_DEBUG("out of memory");
etm.c:1498handle_etm_info_command()
LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
fa526.c:126fa526_write_xpsr()
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
fa526.c:163fa526_write_xpsr_im8()
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
feroceon.c:240feroceon_write_xpsr()
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
feroceon.c:282feroceon_write_xpsr_im8()
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
feroceon.c:331feroceon_branch_resume_thumb()
LOG_DEBUG("-");
fespi.c:137fespi_flash_bank_command()
LOG_DEBUG("%s", __func__);
fespi.c:153fespi_flash_bank_command()
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
fespi.c:363fespi_erase()
LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
fespi.c:489fespi_write()
LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32,
fespi.c:586fespi_write()
LOG_DEBUG("Failed to write %d bytes to " TARGET_ADDR_FMT ": %d",
fespi.c:591fespi_write()
LOG_DEBUG("write(ctrl_base=0x%" TARGET_PRIxADDR ", page_size=0x%x, "
fespi.c:750fespi_probe()
LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
fespi.c:754fespi_probe()
LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
fm3.c:188fm3_busy_wait()
LOG_DEBUG("fm3_busy_wait(%" PRIx32 ") needs about %d ms", offset, ms);
fm4.c:121fm4_flash_erase()
LOG_DEBUG("Spansion FM4 erase sectors %u to %u", first, last);
fm4.c:216fm4_flash_write()
LOG_DEBUG("Spansion FM4 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
fm4.c:276fm4_flash_write()
LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
fm4.c:287fm4_flash_write()
LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
fm4.c:372mb9bf_probe()
LOG_DEBUG("%u sectors", bank->num_sectors);
fm4.c:439s6e2cc_probe()
LOG_DEBUG("%u sectors", bank->num_sectors);
ftdi.c:255move_to_state()
LOG_DEBUG_IO("start=%s goal=%s", tap_state_name(start_state), tap_state_name(goal_state));
ftdi.c:259move_to_state()
tap_set_state(tap_state_transition(tap_get_state(), (tms_bits >> i) & 1));
ftdi.c:294ftdi_khz()
LOG_DEBUG("RCLK not supported");
ftdi.c:316ftdi_execute_runtest()
LOG_DEBUG_IO("runtest %u cycles, end in %s",
ftdi.c:337ftdi_execute_runtest()
LOG_DEBUG_IO("runtest: %u, end in %s",
ftdi.c:344ftdi_execute_statemove()
LOG_DEBUG_IO("statemove end in %s",
ftdi.c:360ftdi_execute_tms()
LOG_DEBUG_IO("TMS: %u bits", cmd->cmd.tms->num_bits);
ftdi.c:376ftdi_execute_pathmove()
LOG_DEBUG_IO("pathmove: %u states, current: %s end: %s", num_states,
ftdi.c:384ftdi_execute_pathmove()
LOG_DEBUG_IO("-");
ftdi.c:406ftdi_execute_pathmove()
tap_set_state(path[state_count]);
ftdi.c:424ftdi_execute_scan()
LOG_DEBUG_IO("%s type:%d", cmd->cmd.scan->ir_scan ? "IRSCAN" : "DRSCAN",
ftdi.c:431ftdi_execute_scan()
LOG_DEBUG_IO("discarding trailing empty field");
ftdi.c:435ftdi_execute_scan()
LOG_DEBUG_IO("empty scan, doing nothing");
ftdi.c:454ftdi_execute_scan()
LOG_DEBUG_IO("%s%s field %u/%u %u bits",
ftdi.c:487ftdi_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 1));
ftdi.c:495ftdi_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 1));
ftdi.c:496ftdi_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 0));
ftdi.c:504ftdi_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 0));
ftdi.c:519ftdi_execute_scan()
LOG_DEBUG_IO("%s scan, %i bits, end in %s",
ftdi.c:529ftdi_reset()
LOG_DEBUG_IO("reset trst: %i srst %i", trst, srst);
ftdi.c:564ftdi_execute_sleep()
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
ftdi.c:568ftdi_execute_sleep()
LOG_DEBUG_IO("sleep %" PRIu32 " usec while in %s",
ftdi.c:592ftdi_execute_stableclocks()
LOG_DEBUG_IO("clocks %u while in %s",
ftdi.c:652ftdi_initialize()
LOG_DEBUG("ftdi interface using 7 step jtag state transitions");
ftdi.c:654ftdi_initialize()
LOG_DEBUG("ftdi interface using shortest path jtag state transitions");
ftdi.c:1061ftdi_swd_run_queue()
LOG_DEBUG_IO("Executing %zu queued transactions", swd_cmd_queue_length);
ftdi.c:1066ftdi_swd_run_queue()
LOG_DEBUG_IO("Skipping due to previous errors: %d", queued_retval);
ftdi.c:1090ftdi_swd_run_queue()
LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK) ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO,
ftdi.c:1142ftdi_swd_queue_cmd()
LOG_DEBUG("Increased SWD command queue to %zu elements", swd_cmd_queue_alloced);
ftdi.c:1200ftdi_swd_switch_seq()
LOG_DEBUG("SWD line reset");
ftdi.c:1205ftdi_swd_switch_seq()
LOG_DEBUG("JTAG-to-SWD");
ftdi.c:1210ftdi_swd_switch_seq()
LOG_DEBUG("JTAG-to-DORMANT");
ftdi.c:1215ftdi_swd_switch_seq()
LOG_DEBUG("SWD-to-JTAG");
ftdi.c:1220ftdi_swd_switch_seq()
LOG_DEBUG("SWD-to-DORMANT");
ftdi.c:1225ftdi_swd_switch_seq()
LOG_DEBUG("DORMANT-to-SWD");
ftdi.c:1230ftdi_swd_switch_seq()
LOG_DEBUG("DORMANT-to-JTAG");
gdb_server.c:154gdb_last_signal()
LOG_TARGET_DEBUG(target, "Debug reason is: %s",
gdb_server.c:238gdb_get_char_inner()
LOG_DEBUG("GDB connection closed by the remote client");
gdb_server.c:342gdb_write()
LOG_DEBUG("GDB socket marked as closed, cannot write to it.");
gdb_server.c:356gdb_log_incoming_packet()
if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
gdb_server.c:375gdb_log_incoming_packet()
LOG_TARGET_DEBUG(target, "{%d} received packet: %.*s<binary-data-%u-bytes>",
gdb_server.c:378gdb_log_incoming_packet()
LOG_TARGET_DEBUG(target, "{%d} received packet: <binary-data-%u-bytes>",
gdb_server.c:383gdb_log_incoming_packet()
LOG_TARGET_DEBUG(target, "{%d} received packet: %s", gdb_connection->unique_index, packet);
gdb_server.c:390gdb_log_outgoing_packet()
if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
gdb_server.c:397gdb_log_outgoing_packet()
LOG_TARGET_DEBUG(target, "{%d} sending packet: $<binary-data-%u-bytes>#%2.2x",
gdb_server.c:400gdb_log_outgoing_packet()
LOG_TARGET_DEBUG(target, "{%d} sending packet: $%.*s#%2.2x",
gdb_server.c:687gdb_get_packet_inner()
LOG_DEBUG("Received first acknowledgment after entering noack mode. Ignoring it.");
gdb_server.c:795gdb_signal_reply()
LOG_TARGET_DEBUG(target, "Responding with signal 2 (SIGINT) to debugger due to Ctrl-C");
gdb_server.c:908gdb_fileio_reply()
LOG_DEBUG("Unknown syscall: %s", target->fileio_info->identifier);
gdb_server.c:1105gdb_connection_closed()
LOG_TARGET_DEBUG(target, "{%d} GDB Close, state: %s, gdb_actual_connections=%d",
gdb_server.c:1283gdb_get_registers_packet()
LOG_DEBUG("Couldn't get register %s.", reg_list[i]->name);
gdb_server.c:1351gdb_set_registers_packet()
LOG_DEBUG("Couldn't set register %s.", reg_list[i]->name);
gdb_server.c:1403gdb_get_register_packet()
LOG_DEBUG("Couldn't get register %s.", reg_list[reg_num]->name);
gdb_server.c:1473gdb_set_register_packet()
LOG_DEBUG("Couldn't set register %s.", reg_list[reg_num]->name);
gdb_server.c:1493gdb_error()
LOG_DEBUG("Reporting %i to GDB as generic error", retval);
gdb_server.c:1531gdb_read_memory_packet()
LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
gdb_server.c:1603gdb_write_memory_packet()
LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
gdb_server.c:1679gdb_write_memory_binary_packet()
LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
gdb_server.c:1711gdb_step_continue_packet()
LOG_DEBUG("-");
gdb_server.c:1737gdb_step_continue_packet()
LOG_DEBUG("continue");
gdb_server.c:1741gdb_step_continue_packet()
LOG_DEBUG("step");
gdb_server.c:1760gdb_breakpoint_watchpoint_packet()
LOG_DEBUG("[%s]", target_name(target));
gdb_server.c:2399smp_reg_list_noread()
LOG_TARGET_DEBUG(target, "%s not found in combined list", a->name);
gdb_server.c:3060gdb_handle_vcont_packet()
LOG_TARGET_DEBUG(target, "target continue");
gdb_server.c:3070gdb_handle_vcont_packet()
LOG_TARGET_DEBUG(target, "error polling target after failed resume");
gdb_server.c:3140gdb_handle_vcont_packet()
LOG_DEBUG("request to step current core only");
gdb_server.c:3148gdb_handle_vcont_packet()
LOG_TARGET_DEBUG(ct, "single-step thread %" PRIx64, thread_id);
gdb_server.c:3164gdb_handle_vcont_packet()
LOG_DEBUG("fake step thread %"PRIx64, thread_id);
gdb_server.c:3179gdb_handle_vcont_packet()
LOG_DEBUG("stepi ignored. GDB will now fetch the register state "
gdb_server.c:3196gdb_handle_vcont_packet()
LOG_TARGET_DEBUG(ct, "error polling target after successful step");
gdb_server.c:3458gdb_v_packet()
LOG_DEBUG("wrote %u bytes from vFlash image to flash", (unsigned)written);
gdb_server.c:3498gdb_fileio_response_packet()
LOG_DEBUG("-");
gdb_server.c:3511gdb_fileio_response_packet()
LOG_DEBUG("File-I/O response, retcode: 0x%x, errno: 0x%x, ctrl-c: %s",
gdb_server.c:3676gdb_input_inner()
LOG_DEBUG("stepi ignored. GDB will now fetch the register state "
gdb_server.c:3772gdb_input_inner()
LOG_DEBUG("ignoring 0x%2.2x packet", packet[0]);
gdb_server.c:3919gdb_target_add_one()
LOG_TARGET_DEBUG(target, "skip gdb server");
hla_interface.c:43hl_interface_open()
LOG_DEBUG("hl_interface_open");
hla_interface.c:68hl_interface_init_target()
LOG_DEBUG("hl_interface_init_target");
hla_interface.c:110hl_interface_init()
LOG_DEBUG("hl_interface_init");
hla_interface.c:118hl_interface_quit()
LOG_DEBUG("hl_interface_quit");
hla_interface.c:216hl_interface_handle_device_desc_command()
LOG_DEBUG("hl_interface_handle_device_desc_command");
hla_interface.c:229hl_interface_handle_layout_command()
LOG_DEBUG("hl_interface_handle_layout_command");
hla_layout.c:28hl_layout_open()
LOG_DEBUG("hl_layout_open");
hla_layout.c:35hl_layout_open()
LOG_DEBUG("failed");
hla_layout.c:83hl_layout_init()
LOG_DEBUG("hl_layout_init");
hla_target.c:77hl_dcc_read()
LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
hla_target.c:163adapter_init_arch_info()
LOG_DEBUG("%s", __func__);
hla_target.c:183adapter_init_target()
LOG_DEBUG("%s", __func__);
hla_target.c:193adapter_target_create()
LOG_DEBUG("%s", __func__);
hla_target.c:278adapter_debug_entry()
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
hla_target.c:323adapter_poll()
LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
hla_target.c:336hl_assert_reset()
LOG_DEBUG("%s", __func__);
hla_target.c:353hl_assert_reset()
LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
hla_target.c:402hl_deassert_reset()
LOG_DEBUG("%s", __func__);
hla_target.c:417adapter_halt()
LOG_DEBUG("%s", __func__);
hla_target.c:420adapter_halt()
LOG_DEBUG("target was already halted");
hla_target.c:448adapter_resume()
LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
hla_target.c:496adapter_resume()
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
hla_target.c:538adapter_step()
LOG_DEBUG("%s", __func__);
hla_target.c:601adapter_read_memory()
LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
hla_target.c:616adapter_write_memory()
LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
hla_transport.c:26hl_transport_jtag_command()
LOG_DEBUG("hl_transport_jtag_command");
hla_transport.c:163hl_transport_init()
LOG_DEBUG("hl_transport_init");
hla_transport.c:180hl_transport_init()
LOG_DEBUG("current transport %s", transport->name);
hla_transport.c:200hl_jtag_transport_select()
LOG_DEBUG("hl_jtag_transport_select");
hla_transport.c:211hl_swd_transport_select()
LOG_DEBUG("hl_swd_transport_select");
hwthread.c:209hwthread_update_threads()
LOG_DEBUG("%s current_thread=%i", __func__, (int)rtos->current_thread);
image.c:58autodetect_image_type()
LOG_DEBUG("Less than 9 bytes in the image file found.");
image.c:59autodetect_image_type()
LOG_DEBUG("BIN image detected.");
image.c:69autodetect_image_type()
LOG_DEBUG("ELF image detected.");
image.c:80autodetect_image_type()
LOG_DEBUG("IHEX image detected.");
image.c:87autodetect_image_type()
LOG_DEBUG("S19 image detected.");
image.c:90autodetect_image_type()
LOG_DEBUG("BIN image detected.");
image.c:638image_elf_read_headers()
LOG_DEBUG("ELF32 image detected.");
image.c:643image_elf_read_headers()
LOG_DEBUG("ELF64 image detected.");
image.c:667image_elf32_read_section()
LOG_DEBUG("load segment %d at 0x%" TARGET_PRIxADDR " (sz = 0x%" PRIx32 ")", section, offset, size);
image.c:673image_elf32_read_section()
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
image.c:710image_elf64_read_section()
LOG_DEBUG("load segment %d at 0x%" TARGET_PRIxADDR " (sz = 0x%" PRIx32 ")", section, offset, size);
image.c:716image_elf64_read_section()
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
image.c:1090image_read_section()
LOG_DEBUG(
image.c:1271image_calculate_checksum()
LOG_DEBUG("Calculating checksum");
image.c:1303image_calculate_checksum()
LOG_DEBUG("Calculating checksum done; checksum=0x%" PRIx32, crc);
interface.c:391jtag_debug_state_machine_()
LOG_DEBUG_IO("TAP/SM: START state: %s", tap_state_name(next_state));
interface.c:397jtag_debug_state_machine_()
LOG_DEBUG_IO("TAP/SM: TMS bits: %u (bytes: %u)", tap_bits, tap_bytes);
interface.c:428jtag_debug_state_machine_()
JTAG_DEBUG_STATE_PRINT(last_state, next_state, tms_str, tdi_str);
interface.c:439jtag_debug_state_machine_()
JTAG_DEBUG_STATE_PRINT(last_state, next_state, tms_str, tdi_str);
interface.c:442jtag_debug_state_machine_()
LOG_DEBUG_IO("TAP/SM: FINAL state: %s", tap_state_name(next_state));
interface.h:164jtag_debug_state_machine()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO))
jep106.c:22jep106_table_manufacturer()
LOG_DEBUG("BUG: Caller passed out-of-range JEP106 ID!");
jlink.c:120jlink_execute_stableclocks()
LOG_DEBUG_IO("stableclocks %i cycles", cmd->cmd.runtest->num_cycles);
jlink.c:126jlink_execute_runtest()
LOG_DEBUG_IO("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles,
jlink.c:135jlink_execute_statemove()
LOG_DEBUG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
jlink.c:143jlink_execute_pathmove()
LOG_DEBUG_IO("pathmove: %u states, end in %i",
jlink.c:152jlink_execute_scan()
LOG_DEBUG_IO("%s type:%d", cmd->cmd.scan->ir_scan ? "IRSCAN" : "DRSCAN",
jlink.c:159jlink_execute_scan()
LOG_DEBUG("discarding trailing empty field");
jlink.c:163jlink_execute_scan()
LOG_DEBUG("empty scan, doing nothing");
jlink.c:186jlink_execute_scan()
LOG_DEBUG_IO("%s%s field %u/%u %u bits",
jlink.c:214jlink_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 1));
jlink.c:222jlink_execute_scan()
tap_set_state(tap_state_transition(tap_get_state(), 0));
jlink.c:238jlink_execute_scan()
LOG_DEBUG_IO("%s scan, %i bits, end in %s",
jlink.c:245jlink_execute_sleep()
LOG_DEBUG_IO("sleep %" PRIu32 "", cmd->cmd.sleep->us);
jlink.c:479adjust_swd_buffer_size()
LOG_DEBUG("Adjusted SWD transaction buffer size to %u bytes",
jlink.c:899jlink_state_move()
tap_set_state(tap_get_end_state());
jlink.c:917jlink_path_move()
tap_set_state(path[i]);
jlink.c:953jlink_reset()
LOG_DEBUG("TRST: %i, SRST: %i", trst, srst);
jlink.c:1406config_trace()
LOG_DEBUG("Using %" PRIu32 " bytes device memory for trace capturing",
jlink.c:2065jlink_flush()
LOG_DEBUG_IO("Pending scan result, length = %d", p->length);
jlink.c:2115jlink_swd_switch_seq()
LOG_DEBUG_IO("SWD line reset");
jlink.c:2120jlink_swd_switch_seq()
LOG_DEBUG("JTAG-to-SWD");
jlink.c:2125jlink_swd_switch_seq()
LOG_DEBUG("JTAG-to-DORMANT");
jlink.c:2130jlink_swd_switch_seq()
LOG_DEBUG("SWD-to-JTAG");
jlink.c:2135jlink_swd_switch_seq()
LOG_DEBUG("SWD-to-DORMANT");
jlink.c:2140jlink_swd_switch_seq()
LOG_DEBUG("DORMANT-to-SWD");
jlink.c:2145jlink_swd_switch_seq()
LOG_DEBUG("DORMANT-to-JTAG");
jlink.c:2164jlink_swd_run_queue()
LOG_DEBUG_IO("Executing %d queued transactions", pending_scan_results_length);
jlink.c:2167jlink_swd_run_queue()
LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
jlink.c:2189jlink_swd_run_queue()
LOG_DEBUG("SWD ack not OK: %d %s", ack,
jtagspi.c:88jtagspi_set_user_ir()
LOG_DEBUG("loading jtagspi ir(0x%" PRIx32 ")", info->ir);
jtagspi.c:111jtagspi_cmd()
LOG_DEBUG("cmd=0x%02x write_len=%d data_len=%d", cmd, write_len, data_len);
jtagspi.c:218jtagspi_handle_set()
LOG_DEBUG("%s", __func__);
jtagspi.c:366jtagspi_handle_cmd()
LOG_DEBUG("%s", __func__);
jtagspi.c:417jtagspi_handle_always_4byte()
LOG_DEBUG("%s", __func__);
jtagspi.c:523jtagspi_read_status()
LOG_DEBUG("status=0x%02" PRIx32, *status);
jtagspi.c:542jtagspi_wait()
LOG_DEBUG("waited %" PRId64 " ms", dt);
jtagspi.c:630jtagspi_erase()
LOG_DEBUG("erase from sector %u to sector %u", first, last);
jtagspi.c:652jtagspi_erase()
LOG_DEBUG("Trying bulk erase.");
jtagspi.c:715jtagspi_read()
LOG_DEBUG("read page at 0x%08" PRIx32, offset);
jtagspi.c:768jtagspi_write()
LOG_DEBUG("wrote page at 0x%08" PRIx32, offset);
kinetis.c:430kinetis_mdm_write_register()
LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
kinetis.c:434kinetis_mdm_write_register()
LOG_DEBUG("MDM: failed to get AP");
kinetis.c:440kinetis_mdm_write_register()
LOG_DEBUG("MDM: failed to queue a write request");
kinetis.c:448kinetis_mdm_write_register()
LOG_DEBUG("MDM: dap_run failed");
kinetis.c:460kinetis_mdm_read_register()
LOG_DEBUG("MDM: failed to get AP");
kinetis.c:466kinetis_mdm_read_register()
LOG_DEBUG("MDM: failed to queue a read request");
kinetis.c:474kinetis_mdm_read_register()
LOG_DEBUG("MDM: dap_run failed");
kinetis.c:478kinetis_mdm_read_register()
LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
kinetis.c:497kinetis_mdm_poll_register()
LOG_DEBUG("MDM: polling timed out");
kinetis.c:531kinetis_mdm_halt()
LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
kinetis.c:548kinetis_mdm_halt()
LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
kinetis.c:841kinetis_check_flash_security_status()
LOG_DEBUG("MDM: dap_run failed when validating secured state");
kinetis.c:1557kinetis_ftfx_command()
LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
kinetis.c:1741kinetis_erase()
LOG_DEBUG("Generated FCF written");
kinetis.c:1827kinetis_write_sections()
LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
kinetis.c:1834kinetis_write_sections()
LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
kinetis.c:1899kinetis_write_inner()
LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
kinetis.c:1945kinetis_write_inner()
LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
kinetis.c:2723kinetis_probe_chip()
LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
kinetis.c:2938kinetis_probe()
LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
kinetis.c:2973kinetis_probe()
LOG_DEBUG("FlexNVM bank %u limited to 0x%08" PRIx32 " due to active EEPROM backup",
kinetis.c:2978kinetis_probe()
LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
kinetis.c:3120kinetis_blank_check()
LOG_DEBUG("Ignoring error on PFlash sector blank-check");
kinetis_ke.c:139kinetis_ke_mdm_write_register()
LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
kinetis_ke.c:143kinetis_ke_mdm_write_register()
LOG_DEBUG("MDM: failed to get AP");
kinetis_ke.c:149kinetis_ke_mdm_write_register()
LOG_DEBUG("MDM: failed to queue a write request");
kinetis_ke.c:157kinetis_ke_mdm_write_register()
LOG_DEBUG("MDM: dap_run failed");
kinetis_ke.c:168kinetis_ke_mdm_read_register()
LOG_DEBUG("MDM: failed to get AP");
kinetis_ke.c:174kinetis_ke_mdm_read_register()
LOG_DEBUG("MDM: failed to queue a read request");
kinetis_ke.c:182kinetis_ke_mdm_read_register()
LOG_DEBUG("MDM: dap_run failed");
kinetis_ke.c:186kinetis_ke_mdm_read_register()
LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
kinetis_ke.c:204kinetis_ke_mdm_poll_register()
LOG_DEBUG("MDM: polling timed out");
kinetis_ke.c:1197kinetis_ke_blank_check()
LOG_DEBUG("Ignoring error on PFlash sector blank-check");
kitprog.c:336kitprog_hid_command()
LOG_DEBUG("HID write returned %i", ret);
kitprog.c:424kitprog_set_protocol()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:429kitprog_set_protocol()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:452kitprog_get_status()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:457kitprog_get_status()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:476kitprog_set_unknown()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:481kitprog_set_unknown()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:501kitprog_acquire_psoc()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:506kitprog_acquire_psoc()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:525kitprog_reset_target()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:530kitprog_reset_target()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:549kitprog_swd_sync()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:554kitprog_swd_sync()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:573kitprog_swd_seq()
LOG_DEBUG("Zero bytes transferred");
kitprog.c:578kitprog_swd_seq()
LOG_DEBUG("Programmer did not respond OK");
kitprog.c:608kitprog_generic_acquire()
LOG_DEBUG("Acquisition function failed for device 0x%02x.", devices[j]);
kitprog.c:651kitprog_swd_switch_seq()
LOG_DEBUG("JTAG to SWD");
kitprog.c:656kitprog_swd_switch_seq()
LOG_DEBUG("JTAG to SWD not supported");
kitprog.c:661kitprog_swd_switch_seq()
LOG_DEBUG("SWD line reset");
kitprog.c:683kitprog_swd_run_queue()
LOG_DEBUG_IO("Executing %d queued transactions", pending_transfer_count);
kitprog.c:686kitprog_swd_run_queue()
LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
kitprog.c:712kitprog_swd_run_queue()
LOG_DEBUG("refusing to enable sticky overrun detection");
kitprog.c:716kitprog_swd_run_queue()
LOG_DEBUG_IO("%s %s reg %x %"PRIx32,
kitprog.c:773kitprog_swd_run_queue()
LOG_DEBUG_IO("Read result: %"PRIx32, data);
kitprog.c:783kitprog_swd_run_queue()
LOG_DEBUG("SWD ack not OK: %d %s", i,
lakemont.c:280drscan()
LOG_DEBUG("dr in 0x%02" PRIx8, *in);
lakemont.c:335lakemont_get_core_reg()
LOG_DEBUG("reg=%s, value=0x%08" PRIx32, reg->name,
lakemont.c:345lakemont_set_core_reg()
LOG_DEBUG("reg=%s, newval=0x%08" PRIx32, reg->name, value);
lakemont.c:439enter_probemode()
LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
lakemont.c:441enter_probemode()
LOG_DEBUG("core already in probemode");
lakemont.c:453enter_probemode()
LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
lakemont.c:466exit_probemode()
LOG_DEBUG("TS before PM exit = 0x%08" PRIx32, tapstatus);
lakemont.c:487halt_prep()
LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSB].name, PM_DSB);
lakemont.c:490halt_prep()
LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSL].name, PM_DSL);
lakemont.c:493halt_prep()
LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR);
lakemont.c:496halt_prep()
LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSB].name, PM_DSB);
lakemont.c:499halt_prep()
LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSL].name, PM_DSL);
lakemont.c:502halt_prep()
LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7);
lakemont.c:510halt_prep()
LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags,
lakemont.c:517halt_prep()
LOG_DEBUG("EFLAGS now = 0x%08" PRIx32 ", VM86 = %d, IF = %d",
lakemont.c:528halt_prep()
LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
lakemont.c:534halt_prep()
LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
lakemont.c:539halt_prep()
LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0);
lakemont.c:544halt_prep()
LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:552halt_prep()
LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:612read_all_core_hw_regs()
LOG_DEBUG("read_all_core_hw_regs read %u registers ok", i);
lakemont.c:631write_all_core_hw_regs()
LOG_DEBUG("write_all_core_hw_regs wrote %u registers ok", i);
lakemont.c:662read_hw_reg()
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
lakemont.c:680write_hw_reg()
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
lakemont.c:779submit_reg_pir()
LOG_DEBUG("reg %s op=0x%016" PRIx64, regs[num].name, regs[num].op);
lakemont.c:790submit_instruction_pir()
LOG_DEBUG("%s op=0x%016" PRIx64, instructions[num].name,
lakemont.c:875lakemont_poll()
LOG_DEBUG("redirect to PM, tapstatus=0x%08" PRIx32, get_tapstatus(t));
lakemont.c:1055lakemont_step()
LOG_DEBUG("modifying PMCR = 0x%08" PRIx32 " and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
lakemont.c:1059lakemont_step()
LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
lakemont.c:1117lakemont_reset_break()
LOG_DEBUG("issuing port 0xcf9 reset");
lakemont.c:1171lakemont_reset_assert()
LOG_DEBUG(" ");
lakemont.c:1174lakemont_reset_assert()
LOG_DEBUG("target must be halted first");
lakemont.c:1212lakemont_reset_deassert()
LOG_DEBUG(" ");
libusb_helper.c:113string_descriptor_equal()
LOG_DEBUG("Device serial number '%s' doesn't match requested serial '%s'",
libusb_helper.c:141jtag_libusb_match_serial()
LOG_DEBUG("Device alternate serial number '%s' doesn't match requested serial '%s'",
libusb_helper.c:342jtag_libusb_choose_interface()
LOG_DEBUG("usb ep %s %02x",
libusb_helper.c:351jtag_libusb_choose_interface()
LOG_DEBUG("Claiming interface %d", (int)interdesc->bInterfaceNumber);
log.c:104log_puts()
if (debug_level >= LOG_LVL_DEBUG) {
log.c:145log_printf()
if (level > debug_level)
log.c:166log_vprintf_lf()
if (level > debug_level)
log.c:206handle_debug_level_command()
debug_level = new_level;
log.c:210handle_debug_level_command()
command_print(CMD, "debug_level: %i", debug_level);
log.c:276log_init()
debug_level >= LOG_LVL_SILENT &&
log.c:277log_init()
debug_level <= LOG_LVL_DEBUG_IO)
log.c:278log_init()
debug_level = value;
log.c:408gdb_timeout_warning()
LOG_DEBUG("keep_alive() was not invoked in the "
lpc2000.c:839lpc2000_iap_call()
LOG_DEBUG("IAP command = %i (0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32
lpc2000.c:1079lpc2000_write()
LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);
lpc2000.c:1086lpc2000_write()
LOG_DEBUG("Vector 0x%2.2x: 0x%8.8" PRIx32, i * 4, buf_get_u32(buffer + (i * 4), 0, 32));
lpc2000.c:1091lpc2000_write()
LOG_DEBUG("checksum: 0x%8.8" PRIx32, checksum);
lpc2000.c:1180lpc2000_write()
LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
lpc288x.c:104lpc288x_wait_status_busy()
LOG_DEBUG("Timedout!");
lpc2900.c:194lpc2900_wait_status()
LOG_DEBUG("Timeout!");
lpc2900.c:1223lpc2900_write()
LOG_DEBUG("Skip secured sector %u",
lpc3180.c:120lpc3180_cycle_time()
LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
lpc3180.c:167lpc3180_init()
LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
lpc3180.c:1160lpc3180_controller_ready()
LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
lpc3180.c:1170lpc3180_controller_ready()
LOG_DEBUG("lpc3180_controller_ready count=%d",
lpc3180.c:1181lpc3180_controller_ready()
LOG_DEBUG("lpc3180_controller_ready count=%d",
lpc3180.c:1203lpc3180_nand_ready()
LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
lpc3180.c:1213lpc3180_nand_ready()
LOG_DEBUG("lpc3180_nand_ready count end=%d",
lpc3180.c:1224lpc3180_nand_ready()
LOG_DEBUG("lpc3180_nand_ready count end=%d",
lpc3180.c:1246lpc3180_tc_ready()
LOG_DEBUG("lpc3180_tc_ready count start=%d",
lpc3180.c:1256lpc3180_tc_ready()
LOG_DEBUG("lpc3180_tc_ready count=%d",
lpc32xx.c:170lpc32xx_cycle_time()
LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
lpc32xx.c:213lpc32xx_init()
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
lpc32xx.c:955lpc32xx_dma_ready()
LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
lpc32xx.c:975lpc32xx_dma_ready()
LOG_DEBUG("lpc32xx_dma_ready count=%d",
lpc32xx.c:1009lpc32xx_dump_oob()
LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
lpc32xx.c:1028lpc32xx_write_page_slc()
LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
lpc32xx.c:1439lpc32xx_read_page_slc()
LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
lpc32xx.c:1615lpc32xx_controller_ready()
LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
lpc32xx.c:1629lpc32xx_controller_ready()
LOG_DEBUG("lpc32xx_controller_ready count=%d",
lpc32xx.c:1644lpc32xx_controller_ready()
LOG_DEBUG("lpc32xx_controller_ready count=%d",
lpc32xx.c:1668lpc32xx_nand_ready()
LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
lpc32xx.c:1683lpc32xx_nand_ready()
LOG_DEBUG("lpc32xx_nand_ready count end=%d",
lpc32xx.c:1698lpc32xx_nand_ready()
LOG_DEBUG("lpc32xx_nand_ready count end=%d",
lpc32xx.c:1714lpc32xx_tc_ready()
LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
lpc32xx.c:1726lpc32xx_tc_ready()
LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
lpcspifi.c:133lpcspifi_set_hw_mode()
LOG_DEBUG("Uninitializing LPC43xx SSP");
lpcspifi.c:164lpcspifi_set_hw_mode()
LOG_DEBUG("Allocating working area for SPIFI init algorithm");
lpcspifi.c:178lpcspifi_set_hw_mode()
LOG_DEBUG("Writing algorithm to working area at " TARGET_ADDR_FMT,
lpcspifi.c:207lpcspifi_set_hw_mode()
LOG_DEBUG("Running SPIFI init algorithm");
lpcspifi.c:416lpcspifi_erase()
LOG_DEBUG("erase from sector %u to sector %u", first, last);
lpcspifi.c:444lpcspifi_erase()
LOG_DEBUG("Chip supports the bulk erase command."
lpcspifi.c:582lpcspifi_write()
LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
lpcspifi.c:773lpcspifi_read_flash_id()
LOG_DEBUG("Getting ID");
ls1_sap.c:32ls1_sap_init_target()
LOG_DEBUG("%s", __func__);
ls1_sap.c:38ls1_sap_arch_state()
LOG_DEBUG("%s", __func__);
ls1_sap.c:54ls1_sap_halt()
LOG_DEBUG("%s", __func__);
ls1_sap.c:61ls1_sap_resume()
LOG_DEBUG("%s", __func__);
ls1_sap.c:68ls1_sap_step()
LOG_DEBUG("%s", __func__);
ls1_sap.c:76ls1_sap_assert_reset()
LOG_DEBUG("%s", __func__);
ls1_sap.c:84ls1_sap_deassert_reset()
LOG_DEBUG("%s", __func__);
ls1_sap.c:175ls1_sap_read_memory()
LOG_DEBUG("Reading memory at physical address 0x%" TARGET_PRIxADDR
ls1_sap.c:197ls1_sap_write_memory()
LOG_DEBUG("Writing memory at physical address 0x%" TARGET_PRIxADDR
max32xxx.c:369max32xxx_write_block()
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
max32xxx.c:374max32xxx_write_block()
LOG_DEBUG("no working area for block memory writes");
max32xxx.c:391max32xxx_write_block()
LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
max32xxx.c:444max32xxx_write()
LOG_DEBUG("bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
max32xxx.c:477max32xxx_write()
LOG_DEBUG("writing flash word-at-a-time");
max32xxx.c:531max32xxx_write()
LOG_DEBUG("Writing @ 0x%08" PRIx32, address);
max32xxx.c:658max32xxx_probe()
LOG_DEBUG("arm_pid = 0x%x", arm_pid);
max32xxx.c:663max32xxx_probe()
LOG_DEBUG("max326xx_id = 0x%" PRIx32, max326xx_id);
max32xxx.c:668max32xxx_probe()
LOG_DEBUG("info->max326xx = %d", info->max326xx);
mem_ap.c:61mem_ap_init_target()
LOG_DEBUG("%s", __func__);
mem_ap.c:71mem_ap_deinit_target()
LOG_DEBUG("%s", __func__);
mem_ap.c:83mem_ap_arch_state()
LOG_DEBUG("%s", __func__);
mem_ap.c:99mem_ap_halt()
LOG_DEBUG("%s", __func__);
mem_ap.c:109mem_ap_resume()
LOG_DEBUG("%s", __func__);
mem_ap.c:118mem_ap_step()
LOG_DEBUG("%s", __func__);
mem_ap.c:130mem_ap_assert_reset()
LOG_DEBUG("%s", __func__);
mem_ap.c:166mem_ap_deassert_reset()
LOG_DEBUG("%s", __func__);
mem_ap.c:241mem_ap_read_memory()
LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
mem_ap.c:256mem_ap_write_memory()
LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
mips32.c:358mips32_read_core_reg()
LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
mips32.c:398mips32_write_core_reg()
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
mips32.c:588mips32_run_and_wait()
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
mips32.c:607mips32_run_algorithm()
LOG_DEBUG("Running algorithm");
mips32.c:697mips32_run_algorithm()
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
mips32.c:831mips32_configure_break_unit()
LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
mips32.c:1024mips32_cpu_probe()
LOG_DEBUG("CPU: %s (PRId %08x)", entry->cpu_name, mips32->prid);
mips32.c:1146mips32_read_config_regs()
LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
mips32_pracc.c:86wait_for_pracc_rw()
LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
mips32_pracc.c:178mips32_pracc_exec()
LOG_DEBUG("restarting code");
mips32_pracc.c:189mips32_pracc_exec()
LOG_DEBUG("unexpected write at address %" PRIx32, ejtag_info->pa_addr);
mips32_pracc.c:199mips32_pracc_exec()
LOG_DEBUG("writing at unexpected address %" PRIx32, ejtag_info->pa_addr);
mips32_pracc.c:218mips32_pracc_exec()
LOG_DEBUG("reading at unexpected address %" PRIx32 ", expected %x",
mips32_pracc.c:224mips32_pracc_exec()
LOG_DEBUG("restarting, without clean jump");
mips32_pracc.c:255mips32_pracc_exec()
LOG_DEBUG("unexpected second pass through pracc text");
mips32_pracc.c:260mips32_pracc_exec()
LOG_DEBUG("unexpected read address in final check: %"
mips32_pracc.c:268mips32_pracc_exec()
LOG_DEBUG("failed to jump back to pracc text");
mips32_pracc.c:273mips32_pracc_exec()
LOG_DEBUG("execution abandoned, store pending: %d", store_pending);
mips32_pracc.c:291mips32_pracc_exec()
LOG_DEBUG("warning: store access pass pracc text");
mips32_pracc.c:682mips32_pracc_synchronize_cache()
LOG_DEBUG("clsiz must be power of 2");
mips32_pracc.c:848mips32_pracc_write_mem()
LOG_DEBUG("Unsupported MIPS Release ( > 5)");
mips32_pracc.c:1210mips32_pracc_fastdata_xfer_synchronize_cache()
LOG_DEBUG("Unsupported MIPS Release ( > 5)");
mips32_pracc.c:1276mips32_pracc_fastdata_xfer()
LOG_DEBUG("%s using 0x%.8" TARGET_PRIxADDR " for write handler", __func__, source->address);
mips64.c:286mips64_write_core_reg()
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
mips64.c:583mips64_configure_break_unit()
LOG_DEBUG("DCR 0x%" PRIx64 " numinst %i numdata %i", dcr,
mips64_pracc.c:55wait_for_pracc_rw()
LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n");
mips64_pracc.c:89mips64_pracc_exec_read()
LOG_DEBUG("Reading %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:101mips64_pracc_exec_read()
LOG_DEBUG("Reading %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:111mips64_pracc_exec_read()
LOG_DEBUG("Running commands %" PRIx64 " at %" PRIx64, data,
mips64_pracc.c:123mips64_pracc_exec_read()
LOG_DEBUG("Reading %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:178mips64_pracc_exec_write()
LOG_DEBUG("Writing %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:225mips64_pracc_exec()
LOG_DEBUG("%08" PRIx32, code[i]);
mips64_pracc.c:240mips64_pracc_exec()
LOG_DEBUG("ERROR wait_for_pracc_rw");
mips64_pracc.c:251mips64_pracc_exec()
LOG_DEBUG("-> %08" PRIx32, address32);
mips64_pracc.c:295mips64_pracc_exec()
LOG_DEBUG("@MIPS64_PRACC_TEXT, address_prev=%" PRIx64, address_prev);
mips64_pracc.c:351mips64_pracc_read_u64()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:409mips64_pracc_read_u32()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:469mips64_pracc_read_u16()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:529mips64_pracc_read_u8()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:609mips64_pracc_write_u64()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:671mips64_pracc_write_u32()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:731mips64_pracc_write_u16()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:792mips64_pracc_write_u8()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:1032mips64_pracc_write_regs()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:1258mips64_pracc_read_regs()
LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:1351mips64_pracc_fastdata_xfer()
LOG_DEBUG("%s using " TARGET_ADDR_FMT " for write handler", __func__,
mips64_pracc.c:1353mips64_pracc_fastdata_xfer()
LOG_DEBUG("daddiu: %08" PRIx32, handler_code[11]);
mips64_pracc.c:1373mips64_pracc_fastdata_xfer()
LOG_DEBUG("start: " TARGET_ADDR_FMT, val);
mips64_pracc.c:1383mips64_pracc_fastdata_xfer()
LOG_DEBUG("stop: " TARGET_ADDR_FMT, val);
mips64_pracc.c:1391mips64_pracc_fastdata_xfer()
LOG_DEBUG("num_clocks=%d", num_clocks);
mips_ejtag.c:248mips_ejtag_enter_debug()
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
mips_ejtag.c:314ejtag_v20_print_imp()
LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
mips_ejtag.c:323ejtag_v20_print_imp()
LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
mips_ejtag.c:330ejtag_v26_print_imp()
LOG_DEBUG("EJTAG v2.6: features:%s%s",
mips_ejtag.c:337ejtag_main_print_imp()
LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
mips_ejtag.c:373mips_ejtag_init()
LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
mips_ejtag.c:376mips_ejtag_init()
LOG_DEBUG("EJTAG: Version 2.5 Detected");
mips_ejtag.c:379mips_ejtag_init()
LOG_DEBUG("EJTAG: Version 2.6 Detected");
mips_ejtag.c:382mips_ejtag_init()
LOG_DEBUG("EJTAG: Version 3.1 Detected");
mips_ejtag.c:385mips_ejtag_init()
LOG_DEBUG("EJTAG: Version 4.1 Detected");
mips_ejtag.c:388mips_ejtag_init()
LOG_DEBUG("EJTAG: Version 5.1 Detected");
mips_ejtag.c:391mips_ejtag_init()
LOG_DEBUG("EJTAG: Unknown Version Detected");
mips_ejtag.c:397mips_ejtag_init()
LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
mips_ejtag.c:515mips64_ejtag_exit_debug()
LOG_DEBUG("enter mips64_pracc_exec");
mips_m4k.c:114mips_m4k_debug_entry()
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
mips_m4k.c:203mips_m4k_poll()
LOG_DEBUG("Reset Detected");
mips_m4k.c:211mips_m4k_poll()
LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
mips_m4k.c:260mips_m4k_halt()
LOG_DEBUG("target->state: %s", target_state_name(target));
mips_m4k.c:263mips_m4k_halt()
LOG_DEBUG("target was already halted");
mips_m4k.c:304mips_m4k_assert_reset()
LOG_DEBUG("target->state: %s",
mips_m4k.c:340mips_m4k_assert_reset()
LOG_DEBUG("Using MTAP reset to reset processor...");
mips_m4k.c:352mips_m4k_assert_reset()
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_m4k.c:374mips_m4k_deassert_reset()
LOG_DEBUG("target->state: %s", target_state_name(target));
mips_m4k.c:466mips_m4k_internal_restore()
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
mips_m4k.c:487mips_m4k_internal_restore()
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
mips_m4k.c:491mips_m4k_internal_restore()
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
mips_m4k.c:572mips_m4k_step()
LOG_DEBUG("target stepped ");
mips_m4k.c:639mips_m4k_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
mips_m4k.c:643mips_m4k_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
mips_m4k.c:743mips_m4k_unset_breakpoint()
LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
mips_m4k.c:747mips_m4k_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
mips_m4k.c:760mips_m4k_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
mips_m4k.c:929mips_m4k_set_watchpoint()
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
mips_m4k.c:949mips_m4k_unset_watchpoint()
LOG_DEBUG("Invalid FP Comparator number in watchpoint");
mips_m4k.c:1013mips_m4k_read_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1078mips_m4k_write_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1183mips_m4k_examine()
LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
mips_m4k.c:1205mips_m4k_bulk_write_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1271mips_m4k_bulk_read_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:64mips_mips64_debug_entry()
LOG_DEBUG("entered debug state at PC 0x%" PRIx64 ", target->state: %s",
mips_mips64.c:90mips_mips64_poll()
LOG_DEBUG("Reset Detected");
mips_mips64.c:121mips_mips64_halt()
LOG_DEBUG("target->state: %s",
mips_mips64.c:125mips_mips64_halt()
LOG_DEBUG("target was already halted");
mips_mips64.c:160mips_mips64_assert_reset()
LOG_DEBUG("target->state: %s",
mips_mips64.c:199mips_mips64_deassert_reset()
LOG_DEBUG("target->state: %s",
mips_mips64.c:244mips_mips64_set_hwbp()
LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %" PRIu32 ")",
mips_mips64.c:271mips_mips64_set_hwbp()
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx64, bp->unique_id,
mips_mips64.c:351mips_mips64_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
mips_mips64.c:476mips_mips64_set_watchpoint()
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx64 "", wp_num, c->bp_value);
mips_mips64.c:507mips_mips64_unset_hwbp()
LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
mips_mips64.c:512mips_mips64_unset_hwbp()
LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d", bp->unique_id, bp_num);
mips_mips64.c:572mips_mips64_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
mips_mips64.c:645mips_mips64_resume()
LOG_DEBUG("unset breakpoint at 0x%16.16" PRIx64 "",
mips_mips64.c:685mips_mips64_resume()
LOG_DEBUG("target resumed at 0x%" PRIx64 "", resume_pc);
mips_mips64.c:693mips_mips64_resume()
LOG_DEBUG("target debug resumed at 0x%" PRIx64 "", resume_pc);
mips_mips64.c:770mips_mips64_step()
LOG_DEBUG("target stepped ");
mips_mips64.c:834mips_mips64_unset_watchpoint()
LOG_DEBUG("Invalid FP Comparator number in watchpoint");
mips_mips64.c:914mips_mips64_read_memory()
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:952mips_mips64_bulk_write_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:1069mips_mips64_write_memory()
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mpsse.c:427mpsse_purge()
LOG_DEBUG("-");
mpsse.c:460buffer_write_byte()
LOG_DEBUG_IO("%02x", data);
mpsse.c:468buffer_write()
LOG_DEBUG_IO("%d bits", bit_count);
mpsse.c:478buffer_add_read()
LOG_DEBUG_IO("%d bits, offset %d", bit_count, offset);
mpsse.c:502mpsse_clock_data()
LOG_DEBUG_IO("%s%s %d bits", in ? "in" : "", out ? "out" : "", length);
mpsse.c:505mpsse_clock_data()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:578mpsse_clock_tms_cs()
LOG_DEBUG_IO("%sout %d bits, tdi=%d", in ? "in" : "", length, tdi);
mpsse.c:582mpsse_clock_tms_cs()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:628mpsse_set_data_bits_low_byte()
LOG_DEBUG_IO("-");
mpsse.c:631mpsse_set_data_bits_low_byte()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:645mpsse_set_data_bits_high_byte()
LOG_DEBUG_IO("-");
mpsse.c:648mpsse_set_data_bits_high_byte()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:662mpsse_read_data_bits_low_byte()
LOG_DEBUG_IO("-");
mpsse.c:665mpsse_read_data_bits_low_byte()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:678mpsse_read_data_bits_high_byte()
LOG_DEBUG_IO("-");
mpsse.c:681mpsse_read_data_bits_high_byte()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:696single_byte_boolean_helper()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:708mpsse_loopback_config()
LOG_DEBUG("%s", enable ? "on" : "off");
mpsse.c:714mpsse_set_divisor()
LOG_DEBUG("%d", divisor);
mpsse.c:717mpsse_set_divisor()
LOG_DEBUG_IO("Ignoring command due to previous error");
mpsse.c:734mpsse_divide_by_5_config()
LOG_DEBUG("%s", enable ? "on" : "off");
mpsse.c:745mpsse_rtck_config()
LOG_DEBUG("%s", enable ? "on" : "off");
mpsse.c:753mpsse_set_frequency()
LOG_DEBUG("target %d Hz", frequency);
mpsse.c:777mpsse_set_frequency()
LOG_DEBUG("actually %d Hz", frequency);
mpsse.c:796read_cb()
DEBUG_PRINT_BUF(transfer->buffer, transfer->actual_length);
mpsse.c:819read_cb()
LOG_DEBUG_IO("raw chunk %d, transferred %d of %d", transfer->actual_length, res->transferred,
mpsse.c:834write_cb()
LOG_DEBUG_IO("transferred %d of %d", res->transferred, ctx->write_count);
mpsse.c:836write_cb()
DEBUG_PRINT_BUF(transfer->buffer, transfer->actual_length);
mpsse.c:853mpsse_flush()
LOG_DEBUG_IO("Ignoring flush due to previous error");
mpsse.c:859mpsse_flush()
LOG_DEBUG_IO("write %d%s, read %d", ctx->write_count, ctx->read_count ? "+1" : "",
mrvlqspi.c:150mrvlqspi_set_ss_state()
LOG_DEBUG("status: 0x%08" PRIx32, regval);
mrvlqspi.c:205mrvlqspi_stop_transfer()
LOG_DEBUG("status: 0x%08" PRIx32, regval);
mrvlqspi.c:234mrvlqspi_stop_transfer()
LOG_DEBUG("status: 0x%08" PRIx32, regval);
mrvlqspi.c:275mrvlqspi_fifo_flush()
LOG_DEBUG("status: 0x%08" PRIX32, val);
mrvlqspi.c:299mrvlqspi_read_byte()
LOG_DEBUG("status: 0x%08" PRIx32, val);
mrvlqspi.c:407mrvlqspi_read_id()
LOG_DEBUG("Getting ID");
mrvlqspi.c:444mrvlqspi_read_id()
LOG_DEBUG("ID is 0x%02" PRIx8 " 0x%02" PRIx8 " 0x%02" PRIx8,
mrvlqspi.c:526mrvlqspi_flash_erase()
LOG_DEBUG("erase from sector %u to sector %u", first, last);
mrvlqspi.c:555mrvlqspi_flash_erase()
LOG_DEBUG("Chip supports the bulk erase command."
mrvlqspi.c:590mrvlqspi_flash_write()
LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
mx3.c:409imx31_write_page()
LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
mx3.c:672do_data_output()
LOG_DEBUG("main area read with 1 (correctable) error");
mx3.c:675do_data_output()
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
mx3.c:680do_data_output()
LOG_DEBUG("spare area read with 1 (correctable) error");
mx3.c:683do_data_output()
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
mxc.c:132mxc_nand_device_command()
LOG_DEBUG("BI-swap enabled");
mxc.c:241mxc_init()
LOG_DEBUG("MXC_NF : bus is 16-bit width");
mxc.c:243mxc_init()
LOG_DEBUG("MXC_NF : bus is 8-bit width");
mxc.c:255mxc_init()
LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
mxc.c:497mxc_write_page()
LOG_DEBUG("part of spare block will be overridden "
mxc.c:709initialize_nf_controller()
LOG_DEBUG("MXC_NF : work in Big Endian mode");
mxc.c:712initialize_nf_controller()
LOG_DEBUG("MXC_NF : work in Little Endian mode");
mxc.c:714initialize_nf_controller()
LOG_DEBUG("MXC_NF : work with ECC mode");
mxc.c:717initialize_nf_controller()
LOG_DEBUG("MXC_NF : work without ECC mode");
nrf5.c:401nrf5_wait_for_nvmc()
LOG_DEBUG("Timed out waiting for NVMC_READY");
nrf5.c:721nrf5_read_ficr_info_part()
LOG_DEBUG("Couldn't read FICR INFO.PART register");
nrf5.c:755nrf51_52_partno_check()
LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
nrf5.c:774nrf53_91_partno_check()
LOG_DEBUG("Invalid FICR INFO PART value 0x%08"
nrf5.c:813nrf51_get_ram_size()
LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
nrf5.c:818nrf51_get_ram_size()
LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
nrf5.c:826nrf51_get_ram_size()
LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
nrf5.c:830nrf51_get_ram_size()
LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
nrf5.c:916nrf5_probe_chip()
LOG_DEBUG("Couldn't read some of FICR INFO registers");
nrf5.c:933nrf5_probe_chip()
LOG_DEBUG("Couldn't read FICR CONFIGID register, using FICR INFO");
nrf5.c:1070nrf5_erase_page()
LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
nrf5.c:1143nrf5_ll_flash_write()
LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
numicro.c:548numicro_get_arm_arch()
LOG_DEBUG("NuMicro arm architecture: armv7m\n");
numicro.c:552numicro_get_arm_arch()
LOG_DEBUG("NuMicro arm architecture: armv6m\n");
numicro.c:570numicro_reg_unlock()
LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected);
numicro.c:589numicro_reg_unlock()
LOG_DEBUG("protection removed");
numicro.c:591numicro_reg_unlock()
LOG_DEBUG("still protected!!");
numicro.c:669numicro_fmc_cmd()
LOG_DEBUG("timed out waiting for flash");
numicro.c:831numicro_protect_check()
LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]);
numicro.c:879numicro_erase()
LOG_DEBUG("erasing sector %u at address " TARGET_ADDR_FMT, i, bank->base + bank->sectors[i].offset);
numicro.c:900numicro_erase()
LOG_DEBUG("timed out waiting for flash");
numicro.c:911numicro_erase()
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
numicro.c:920numicro_erase()
LOG_DEBUG("Erase done.");
numicro.c:996numicro_write()
LOG_DEBUG("timed out waiting for flash");
numicro.c:1010numicro_write()
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
numicro.c:1018numicro_write()
LOG_DEBUG("Write OK");
numicro.c:1022numicro_write()
LOG_DEBUG("Write done.");
numicro.c:1103numicro_probe()
LOG_DEBUG("Nuvoton NuMicro: Probed ...");
numicro.c:1126numicro_flash_bank_command()
LOG_DEBUG("add flash_bank numicro %s", bank->name);
nuttx.c:216nuttx_update_threads()
LOG_DEBUG("Hash table size (g_npidhash) = %" PRId32, npidhash);
nuttx.c:224nuttx_update_threads()
LOG_DEBUG("Hash table address (g_pidhash) = %" PRIx32, pidhashaddr);
opendous.c:251opendous_execute_queue()
LOG_DEBUG_IO("runtest %u cycles, end in %i", cmd->cmd.runtest->num_cycles,
opendous.c:260opendous_execute_queue()
LOG_DEBUG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
opendous.c:268opendous_execute_queue()
LOG_DEBUG_IO("pathmove: %u states, end in %i",
opendous.c:276opendous_execute_queue()
LOG_DEBUG_IO("scan end in %i", cmd->cmd.scan->end_state);
opendous.c:282opendous_execute_queue()
LOG_DEBUG_IO("scan input, length = %d", scan_size);
opendous.c:292opendous_execute_queue()
LOG_DEBUG_IO("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
opendous.c:297opendous_execute_queue()
tap_set_state(TAP_RESET);
opendous.c:302opendous_execute_queue()
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
opendous.c:419opendous_state_move()
tap_set_state(tap_get_end_state());
opendous.c:435opendous_path_move()
tap_set_state(path[i]);
opendous.c:483opendous_scan()
tap_set_state(ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE);
opendous.c:491opendous_reset()
LOG_DEBUG("trst: %i, srst: %i", trst, srst);
opendous.c:515opendous_simple_command()
LOG_DEBUG_IO("0x%02x 0x%02x", command, _data);
opendous.c:584opendous_tap_append_scan()
LOG_DEBUG_IO("append scan, length = %d", length);
opendous.c:666opendous_tap_execute()
LOG_DEBUG_IO("pending scan result, length = %d", length);
opendous.c:760opendous_usb_write()
LOG_DEBUG_IO("opendous_usb_write, out_length = %d, result = %d", out_length, result);
opendous.c:792opendous_usb_read()
LOG_DEBUG_IO("opendous_usb_read, result = %d", result);
openocd.c:133handle_init_command()
LOG_DEBUG("Debug Adapter init complete");
openocd.c:150handle_init_command()
LOG_DEBUG("Examining targets...");
openocd.c:152handle_init_command()
LOG_DEBUG("target examination failed");
openocd.c:238setup_command_handler()
LOG_DEBUG("log_init: complete");
openocd.c:268setup_command_handler()
LOG_DEBUG("command registration: complete");
options.c:122find_exe_path()
LOG_DEBUG("BINDIR = %s", BINDIR);
options.c:234add_default_dirs()
LOG_DEBUG("bindir=%s", BINDIR);
options.c:235add_default_dirs()
LOG_DEBUG("pkgdatadir=%s", PKGDATADIR);
options.c:236add_default_dirs()
LOG_DEBUG("exepath=%s", exepath);
options.c:237add_default_dirs()
LOG_DEBUG("bin2data=%s", bin2data);
options.c:355parse_cmdline_args()
LOG_DEBUG("ARGV[%d] = \"%s\"", i, argv[i]);
or1k.c:246or1k_create_reg_list()
LOG_DEBUG("-");
or1k.c:311or1k_jtag_read_regs()
LOG_DEBUG("-");
or1k.c:322or1k_jtag_write_regs()
LOG_DEBUG("-");
or1k.c:336or1k_save_context()
LOG_DEBUG("-");
or1k.c:370or1k_restore_context()
LOG_DEBUG("-");
or1k.c:407or1k_read_core_reg()
LOG_DEBUG("-");
or1k.c:415or1k_read_core_reg()
LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num, reg_value);
or1k.c:427or1k_read_core_reg()
LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num, reg_value);
or1k.c:437or1k_write_core_reg()
LOG_DEBUG("-");
or1k.c:444or1k_write_core_reg()
LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num, reg_value);
or1k.c:456or1k_get_core_reg()
LOG_DEBUG("-");
or1k.c:472or1k_set_core_reg()
LOG_DEBUG("-");
or1k.c:509or1k_build_reg_cache()
LOG_DEBUG("-");
or1k.c:546or1k_debug_entry()
LOG_DEBUG("-");
or1k.c:570or1k_halt()
LOG_DEBUG("target->state: %s",
or1k.c:574or1k_halt()
LOG_DEBUG("Target was already halted");
or1k.c:714or1k_assert_reset()
LOG_DEBUG("-");
or1k.c:730or1k_deassert_reset()
LOG_DEBUG("-");
or1k.c:746or1k_soft_reset_halt()
LOG_DEBUG("-");
or1k.c:769is_any_soft_breakpoint()
LOG_DEBUG("-");
or1k.c:788or1k_resume_or_step()
LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
or1k.c:853or1k_resume_or_step()
LOG_DEBUG("Unset breakpoint at 0x%08" TARGET_PRIxADDR, breakpoint->address);
or1k.c:878or1k_resume_or_step()
LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
or1k.c:882or1k_resume_or_step()
LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
or1k.c:915or1k_add_breakpoint()
LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, id: %" PRIu32,
or1k.c:973or1k_remove_breakpoint()
LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, id: %" PRIu32,
or1k.c:1026or1k_read_memory()
LOG_DEBUG("Read memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
or1k.c:1053or1k_write_memory()
LOG_DEBUG("Write memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
or1k.c:1140or1k_examine()
LOG_DEBUG("Target is halted");
or1k.c:1357or1k_addreg_command_handler()
LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
or1k_du_adv.c:183or1k_adv_jtag_init()
LOG_DEBUG("Init done");
or1k_du_adv.c:202adbg_select_module()
LOG_DEBUG("Select module: %s", chain_name[chain]);
or1k_du_adv.c:285adbg_ctrl_write()
LOG_DEBUG("Write control register %" PRId8 ": 0x%08" PRIx32, regidx, cmd_data[0]);
or1k_du_adv.c:421adbg_wb_burst_read()
LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32,
or1k_du_adv.c:518adbg_wb_burst_read()
LOG_DEBUG("CRC OK!");
or1k_du_adv.c:575adbg_wb_burst_write()
LOG_DEBUG("Doing burst write, word size %d, word count %d,"
or1k_du_adv.c:588adbg_wb_burst_write()
LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
or1k_du_adv.c:597adbg_wb_burst_write()
LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
or1k_du_adv.c:606adbg_wb_burst_write()
LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
or1k_du_adv.c:662adbg_wb_burst_write()
LOG_DEBUG("CRC OK!\n");
or1k_du_adv.c:839or1k_adv_jtag_read_memory()
LOG_DEBUG("Reading WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
or1k_du_adv.c:894or1k_adv_jtag_write_memory()
LOG_DEBUG("Writing WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
or1k_du_adv.c:965or1k_adv_jtag_jsp_xfer()
LOG_DEBUG("JSP transfer");
or1k_tap_mohor.c:21or1k_tap_mohor_init()
LOG_DEBUG("Initialising OpenCores JTAG TAP");
or1k_tap_vjtag.c:80or1k_tap_vjtag_init()
LOG_DEBUG("Initialising Altera Virtual JTAG TAP");
or1k_tap_vjtag.c:205or1k_tap_vjtag_init()
LOG_DEBUG("SLD HUB Configuration register");
or1k_tap_vjtag.c:206or1k_tap_vjtag_init()
LOG_DEBUG("------------------------------");
or1k_tap_vjtag.c:207or1k_tap_vjtag_init()
LOG_DEBUG("m_width = %d", m_width);
or1k_tap_vjtag.c:208or1k_tap_vjtag_init()
LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(hub_info));
or1k_tap_vjtag.c:209or1k_tap_vjtag_init()
LOG_DEBUG("nb_of_node = %d", nb_nodes);
or1k_tap_vjtag.c:210or1k_tap_vjtag_init()
LOG_DEBUG("version = %" PRIu32, VER(hub_info));
or1k_tap_vjtag.c:211or1k_tap_vjtag_init()
LOG_DEBUG("VIR length = %d", guess_addr_width(nb_nodes) + m_width);
or1k_tap_vjtag.c:247or1k_tap_vjtag_init()
LOG_DEBUG("Node info register");
or1k_tap_vjtag.c:248or1k_tap_vjtag_init()
LOG_DEBUG("--------------------");
or1k_tap_vjtag.c:249or1k_tap_vjtag_init()
LOG_DEBUG("instance_id = %" PRIu32, ID(node_info));
or1k_tap_vjtag.c:250or1k_tap_vjtag_init()
LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(node_info));
or1k_tap_vjtag.c:251or1k_tap_vjtag_init()
LOG_DEBUG("node_id = %" PRIu32 " (%s)", ID(node_info),
or1k_tap_vjtag.c:253or1k_tap_vjtag_init()
LOG_DEBUG("version = %" PRIu32, VER(node_info));
or1k_tap_xilinx_bscan.c:21or1k_tap_xilinx_bscan_init()
LOG_DEBUG("Initialising Xilinx Internal JTAG TAP");
osbdm.c:407osbdm_add_pathmove()
tap_set_state(path[i]);
osbdm.c:448osbdm_add_statemove()
tap_set_state(tap_get_end_state());
osbdm.c:669osbdm_init()
LOG_DEBUG("OSBDM init");
pic32mm.c:235pic32mm_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32, status);
pic32mm.c:239pic32mm_wait_status_busy()
LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
pic32mm.c:398pic32mm_erase()
LOG_DEBUG("Erasing entire program flash");
pic32mm.c:1040pic32mm_handle_unlock_command()
LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
pic32mx.c:225pic32mx_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32, status);
pic32mx.c:229pic32mx_wait_status_busy()
LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
pic32mx.c:327pic32mx_erase()
LOG_DEBUG("Erasing entire program flash");
pic32mx.c:610pic32mx_write()
LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
pic32mx.c:903pic32mx_handle_unlock_command()
LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
picoprobe.c:113picoprobe_flush()
LOG_DEBUG_IO("Flush %d transactions", (int)picoprobe_queue_length);
picoprobe.c:182picoprobe_flush()
LOG_DEBUG_IO("Read %d bytes from probe", ret);
picoprobe.c:208picoprobe_flush()
LOG_DEBUG_IO("Processing read of %d bits", read_hdr->bits);
picoprobe.c:233picoprobe_read_write_bits()
LOG_DEBUG_IO("Picoprobe queue len %d -> %d", (int)picoprobe_queue_length,
picoprobe.c:249picoprobe_write_bits()
LOG_DEBUG_IO("Write %d bits @ offset %d", length, offset);
picoprobe.c:255picoprobe_read_bits()
LOG_DEBUG_IO("Read %d bits @ offset %d", length, offset);
picoprobe.c:265picoprobe_swd_run_queue()
LOG_DEBUG_IO("Executing %zu queued transactions", swd_cmd_queue_length);
picoprobe.c:271picoprobe_swd_run_queue()
LOG_DEBUG_IO("Skipping due to previous errors: %d", queued_retval);
picoprobe.c:283picoprobe_swd_run_queue()
LOG_DEBUG_IO("trn_ack_data_parity_trn:");
picoprobe.c:285picoprobe_swd_run_queue()
LOG_DEBUG_IO("BYTE %d 0x%x", (int)y, swd_cmd_queue[i].trn_ack_data_parity_trn[y]);
picoprobe.c:289picoprobe_swd_run_queue()
LOG_DEBUG_IO("%s %s %s reg %X = %08"PRIx32,
picoprobe.c:363picoprobe_swd_queue_cmd()
LOG_DEBUG("Add %d idle cycles", ap_delay_clk);
picoprobe.c:440picoprobe_swd_switch_seq()
LOG_DEBUG_IO("SWD line reset");
picoprobe.c:444picoprobe_swd_switch_seq()
LOG_DEBUG("JTAG-to-SWD");
picoprobe.c:448picoprobe_swd_switch_seq()
LOG_DEBUG("SWD-to-JTAG");
picoprobe.c:452picoprobe_swd_switch_seq()
LOG_DEBUG("DORMANT-to-SWD");
picoprobe.c:456picoprobe_swd_switch_seq()
LOG_DEBUG("SWD-to-DORMANT");
pld.c:337handle_pld_init_command()
LOG_DEBUG("Initializing PLDs...");
program.c:35riscv_program_write()
LOG_DEBUG("debug_buffer[%02x] = DASM(0x%08x)", i, program->debug_buffer[i]);
program.c:51riscv_program_exec()
LOG_DEBUG("Saving register %d as used by program", (int)i);
program.c:70riscv_program_exec()
LOG_DEBUG("Unable to execute program %p", p);
psoc4.c:252psoc4_sysreq()
LOG_DEBUG("no working area for sysreq code");
psoc4.c:268psoc4_sysreq()
LOG_DEBUG("SYSREQ %02" PRIx8 " %04" PRIx16 " %08" PRIx32 " size %" PRIu32,
psoc4.c:295psoc4_sysreq()
LOG_DEBUG("SYSREQ %02" PRIx8 " %04" PRIx16 " %08" PRIx32,
psoc4.c:661psoc4_write()
LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32 "",
psoc4.c:772psoc4_probe()
LOG_DEBUG("SPCIF geometry: %" PRIu32 " KiB flash, row %" PRIu32 " bytes.",
psoc4.c:816psoc4_probe()
LOG_DEBUG("flash bank set %" PRIu32 " rows", num_rows);
psoc5lp.c:256psoc5lp_find_device()
LOG_DEBUG("PANTHER_DEVICE_ID = 0x%08" PRIX32, device_id);
psoc5lp.c:870psoc5lp_eeprom_write()
LOG_DEBUG("Get_Temp: sign 0x%02" PRIx8 ", magnitude 0x%02" PRIx8,
psoc5lp.c:895psoc5lp_eeprom_write()
LOG_DEBUG("Padding %" PRIu32 " bytes", EEPROM_ROW_SIZE - byte_count);
psoc5lp.c:1033psoc5lp_erase()
LOG_DEBUG("Skipping duplicate erase of sectors %u to %u",
psoc5lp.c:1152psoc5lp_write()
LOG_DEBUG("Get_Temp: sign 0x%02" PRIx8 ", magnitude 0x%02" PRIx8,
psoc5lp.c:1188psoc5lp_write()
LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT,
psoc5lp.c:1211psoc5lp_write()
LOG_DEBUG("Padding %d bytes", ROW_SIZE - len);
psoc5lp.c:1345psoc5lp_protect_check()
LOG_DEBUG("row[%u][%02u] = 0x%02" PRIx8, i, k, row_data[k]);
psoc5lp.c:1434psoc5lp_probe()
LOG_DEBUG("NVL[%d] = 0x%02" PRIx8, 3, nvl[3]);
psoc6.c:644psoc6_erase_sector()
LOG_DEBUG("Erasing SECTOR @%08" PRIX32, addr);
psoc6.c:673psoc6_erase_row()
LOG_DEBUG("Erasing ROW @%08" PRIX32, addr);
psoc6.c:772psoc6_program_row()
LOG_DEBUG("Programming ROW @%08" PRIX32, addr);
qn908x.c:246qn908x_update_reg()
LOG_DEBUG("Error reading reg at " TARGET_ADDR_FMT
qn908x.c:254qn908x_update_reg()
LOG_DEBUG("Error writing reg at " TARGET_ADDR_FMT " with 0x%08"
qn908x.c:259qn908x_update_reg()
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08"
qn908x.c:262qn908x_update_reg()
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32
qn908x.c:291qn908x_load_lock_stat()
LOG_DEBUG("LOCK_STAT_%d = 0x%08" PRIx32, i, lock_stat);
qn908x.c:307qn908x_init_flash()
LOG_DEBUG("Clock clk_sel=0x%08" PRIu32, clk_sel);
qn908x.c:338qn908x_init_flash()
LOG_DEBUG("Core freq: %" PRIu32 " Hz | AHB freq: %" PRIu32 " Hz",
qn908x.c:409qn908x_read_page_lock()
LOG_DEBUG("Flash protection = 0x%02" PRIx8,
qn908x.c:547qn908x_erase()
LOG_DEBUG("Erasing page %" PRIu32 " of block %" PRIu32,
qn908x.c:646qn908x_protect()
LOG_DEBUG("protect set=%d bits[%d] with mask=0x%02x", set, i, mask);
qn908x.c:691qn908x_write()
LOG_DEBUG("computed image checksum: 0x%8.8" PRIx32, checksum);
qn908x.c:713qn908x_write()
LOG_DEBUG("Code Read Protection = 0x%08" PRIx32, crp);
qn908x.c:920qn908x_auto_probe()
LOG_DEBUG("auto_probe");
qn908x.c:1062qn908x_handle_mass_erase_command()
LOG_DEBUG("LOCK_STAT_8 before erasing: 0x%" PRIx32, lock_stat_8);
qn908x.c:1083qn908x_handle_mass_erase_command()
LOG_DEBUG("Erasing both blocks with command 0x%" PRIx32, erase_cmd);
renesas_rpchf.c:616rpchf_read()
LOG_DEBUG("reading buffer of %" PRIu32 " byte at 0x%8.8" PRIx32,
riscv-011.c:307dtmcontrol_scan()
LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
riscv-011.c:334idcode_scan()
LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
riscv-011.c:343increase_dbus_busy_delay()
LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
riscv-011.c:354increase_interrupt_high_delay()
LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
riscv-011.c:397dump_field()
if (debug_level < LOG_LVL_DEBUG)
riscv-011.c:772cache_set32()
LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
riscv-011.c:775cache_set32()
LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
riscv-011.c:864cache_write()
LOG_DEBUG("enter");
riscv-011.c:986cache_write()
LOG_DEBUG("exit");
riscv-011.c:1046read_remote_csr()
LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
riscv-011.c:1061write_remote_csr()
LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
riscv-011.c:1114execute_resume()
LOG_DEBUG("step=%d", step);
riscv-011.c:1213reg_cache_get()
LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
riscv-011.c:1221reg_cache_set()
LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
riscv-011.c:1265register_read()
LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
riscv-011.c:1392halt()
LOG_DEBUG("riscv_halt()");
riscv-011.c:1410deinit_target()
LOG_DEBUG("riscv_deinit_target()");
riscv-011.c:1421strict_step()
LOG_DEBUG("enter");
riscv-011.c:1473examine()
LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
riscv-011.c:1474examine()
LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
riscv-011.c:1475examine()
LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
riscv-011.c:1476examine()
LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
riscv-011.c:1500examine()
LOG_DEBUG("dminfo: 0x%08x", dminfo);
riscv-011.c:1501examine()
LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
riscv-011.c:1502examine()
LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
riscv-011.c:1503examine()
LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
riscv-011.c:1504examine()
LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
riscv-011.c:1505examine()
LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
riscv-011.c:1506examine()
LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
riscv-011.c:1507examine()
LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
riscv-011.c:1508examine()
LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
riscv-011.c:1509examine()
LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
riscv-011.c:1510examine()
LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
riscv-011.c:1511examine()
LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
riscv-011.c:1512examine()
LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
riscv-011.c:1569examine()
LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
riscv-011.c:1905poll_target()
int old_debug_level = debug_level;
riscv-011.c:1906poll_target()
if (debug_level >= LOG_LVL_DEBUG)
riscv-011.c:1907poll_target()
debug_level = LOG_LVL_INFO;
riscv-011.c:1909poll_target()
debug_level = old_debug_level;
riscv-011.c:1913poll_target()
LOG_DEBUG("debug running");
riscv-011.c:1919poll_target()
LOG_DEBUG("halting");
riscv-011.c:2092read_memory()
LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
riscv-011.c:2172write_memory()
LOG_DEBUG("t0 is 0x%" PRIx64, t0);
riscv-011.c:2374init_target()
LOG_DEBUG("init");
riscv-013.c:251get_dm()
LOG_DEBUG("[%d] Allocating new DM", target->coreid);
riscv-013.c:377dump_field()
if (debug_level < LOG_LVL_DEBUG)
riscv-013.c:445dtmcontrol_scan()
LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
riscv-013.c:454increase_dmi_busy_delay()
LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
riscv-013.c:715increase_ac_busy_delay()
LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
riscv-013.c:775execute_abstract_command()
if (debug_level >= LOG_LVL_DEBUG) {
riscv-013.c:778execute_abstract_command()
LOG_DEBUG("command=0x%x; access register, size=%d, postexec=%d, "
riscv-013.c:788execute_abstract_command()
LOG_DEBUG("command=0x%x", command);
riscv-013.c:801execute_abstract_command()
LOG_DEBUG("command 0x%x failed; abstractcs=0x%x", command, abstractcs);
riscv-013.c:1299register_write_direct()
LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target),
riscv-013.c:1488register_read_direct()
LOG_DEBUG("{%d} %s = 0x%" PRIx64, riscv_current_hartid(target),
riscv-013.c:1522deinit_target()
LOG_DEBUG("riscv_deinit_target()");
riscv-013.c:1567examine()
LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
riscv-013.c:1568examine()
LOG_DEBUG(" dmireset=%d", get_field(dtmcontrol, DTM_DTMCS_DMIRESET));
riscv-013.c:1569examine()
LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTM_DTMCS_IDLE));
riscv-013.c:1570examine()
LOG_DEBUG(" dmistat=%d", get_field(dtmcontrol, DTM_DTMCS_DMISTAT));
riscv-013.c:1571examine()
LOG_DEBUG(" abits=%d", get_field(dtmcontrol, DTM_DTMCS_ABITS));
riscv-013.c:1572examine()
LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTM_DTMCS_VERSION));
riscv-013.c:1617examine()
LOG_DEBUG("dmstatus: 0x%08x", dmstatus);
riscv-013.c:1633examine()
LOG_DEBUG("hartsellen=%d", info->hartsellen);
riscv-013.c:1702examine()
LOG_DEBUG("Detected %d harts.", dm->hart_count);
riscv-013.c:1752examine()
LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
riscv-013.c:2277init_target()
LOG_DEBUG("init");
riscv-013.c:2417deassert_reset()
LOG_DEBUG("Waiting for hart %d to come out of reset.", index);
riscv-013.c:2472execute_fence()
LOG_DEBUG("Unable to execute pre-fence");
riscv-013.c:2481log_memory_access()
if (debug_level < LOG_LVL_DEBUG)
riscv-013.c:2502log_memory_access()
LOG_DEBUG(fmt, value);
riscv-013.c:2596read_memory_bus_v0()
LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
riscv-013.c:2618read_memory_bus_v0()
LOG_DEBUG("\r\nread_memory: sab: access: 0x%08x", access);
riscv-013.c:2624read_memory_bus_v0()
LOG_DEBUG("\r\nread_memory: sab: value: 0x%08x", value);
riscv-013.c:2633read_memory_bus_v0()
LOG_DEBUG("reading block until final address 0x%" PRIx64, fin_addr);
riscv-013.c:2644read_memory_bus_v0()
LOG_DEBUG("\r\naccess: 0x%08x", access);
riscv-013.c:2648read_memory_bus_v0()
LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08"
riscv-013.c:2843log_mem_access_result()
LOG_DEBUG("%s", msg);
riscv-013.c:2852mem_should_skip_progbuf()
LOG_DEBUG("Skipping mem %s via progbuf - insufficient progbuf size.",
riscv-013.c:2858mem_should_skip_progbuf()
LOG_DEBUG("Skipping mem %s via progbuf - target not halted.",
riscv-013.c:2864mem_should_skip_progbuf()
LOG_DEBUG("Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
riscv-013.c:2870mem_should_skip_progbuf()
LOG_DEBUG("Skipping mem %s via progbuf - unsupported size.",
riscv-013.c:2876mem_should_skip_progbuf()
LOG_DEBUG("Skipping mem %s via progbuf - progbuf only supports %u-bit address.",
riscv-013.c:2892mem_should_skip_sysbus()
LOG_DEBUG("Skipping mem %s via system bus - unsupported size.",
riscv-013.c:2899mem_should_skip_sysbus()
LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.",
riscv-013.c:2905mem_should_skip_sysbus()
LOG_DEBUG("Skipping mem read via system bus - "
riscv-013.c:2922mem_should_skip_abstract()
LOG_DEBUG("Skipping mem %s via abstract access - unsupported size: %d bits",
riscv-013.c:2928mem_should_skip_abstract()
LOG_DEBUG("Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
riscv-013.c:2956read_memory_abstract()
LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
riscv-013.c:2990read_memory_abstract()
LOG_DEBUG("aampostincrement is supported on this target.");
riscv-013.c:3001read_memory_abstract()
LOG_DEBUG("aampostincrement is not supported on this target.");
riscv-013.c:3034write_memory_abstract()
LOG_DEBUG("writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
riscv-013.c:3073write_memory_abstract()
LOG_DEBUG("aampostincrement is supported on this target.");
riscv-013.c:3084write_memory_abstract()
LOG_DEBUG("aampostincrement is not supported on this target.");
riscv-013.c:3151read_memory_progbuf_inner()
LOG_DEBUG("i=%d, count=%d, read_addr=0x%" PRIx64, index, count, read_addr);
riscv-013.c:3193read_memory_progbuf_inner()
LOG_DEBUG("successful (partial?) memory read");
riscv-013.c:3197read_memory_progbuf_inner()
LOG_DEBUG("memory read resulted in busy response");
riscv-013.c:3250read_memory_progbuf_inner()
LOG_DEBUG("error when reading memory, abstractcs=0x%08lx", (long)abstractcs);
riscv-013.c:3263read_memory_progbuf_inner()
LOG_DEBUG("index=%d, reads=%d, next_index=%d, ignore_last=%d, j=%d",
riscv-013.c:3427read_memory_progbuf()
LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
riscv-013.c:3510read_memory_progbuf()
LOG_DEBUG("error reading single word of %d bytes from 0x%" TARGET_PRIxADDR,
riscv-013.c:3600write_memory_bus_v0()
LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
riscv-013.c:3616write_memory_bus_v0()
LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
riscv-013.c:3617write_memory_bus_v0()
LOG_DEBUG("\r\nwrite_memory:SAB: ONE OFF: value 0x%08" PRIx64, value);
riscv-013.c:3627write_memory_bus_v0()
LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
riscv-013.c:3638write_memory_bus_v0()
LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
riscv-013.c:3664write_memory_bus_v1()
LOG_DEBUG("transferring burst starting at address 0x%" TARGET_PRIxADDR,
riscv-013.c:3725write_memory_bus_v1()
LOG_DEBUG("DMI busy encountered during system bus write.");
riscv-013.c:3742write_memory_bus_v1()
LOG_DEBUG("Sbbusyerror encountered during system bus write.");
riscv-013.c:3755write_memory_bus_v1()
LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
riscv-013.c:3771write_memory_bus_v1()
LOG_DEBUG("System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")",
riscv-013.c:3776write_memory_bus_v1()
LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
riscv-013.c:3800write_memory_progbuf()
LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address);
riscv-013.c:3857write_memory_progbuf()
LOG_DEBUG("writing until final address 0x%016" PRIx64, fin_addr);
riscv-013.c:3859write_memory_progbuf()
LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64,
riscv-013.c:3940write_memory_progbuf()
LOG_DEBUG("successful (partial?) memory write");
riscv-013.c:3943write_memory_progbuf()
LOG_DEBUG("Memory write resulted in abstract command busy response.");
riscv-013.c:3945write_memory_progbuf()
LOG_DEBUG("Memory write resulted in DMI busy response.");
riscv-013.c:4070riscv013_get_register()
LOG_DEBUG("[%s] reading register %s", target_name(target),
riscv-013.c:4080riscv013_get_register()
LOG_DEBUG("[%d] read PC from DPC: 0x%" PRIx64, target->coreid, *value);
riscv-013.c:4099riscv013_set_register()
LOG_DEBUG("[%d] writing 0x%" PRIx64 " to register %s",
riscv-013.c:4105riscv013_set_register()
LOG_DEBUG("[%d] writing PC to DPC: 0x%" PRIx64, target->coreid, value);
riscv-013.c:4109riscv013_set_register()
LOG_DEBUG("[%d] actual DPC written: 0x%016" PRIx64, target->coreid, actual_value);
riscv-013.c:4175select_prepped_harts()
LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped);
riscv-013.c:4214riscv013_halt_go()
LOG_DEBUG("halting hart %d", r->current_hartid);
riscv-013.c:4323riscv013_halt_reason()
LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
riscv-013.c:4333riscv013_halt_reason()
LOG_DEBUG("{%d} halted because of trigger", target->coreid);
riscv-013.c:4359riscv013_write_debug_buffer()
LOG_DEBUG("cache hit for 0x%" PRIx32 " @%d", data, index);
riscv-013.c:4441riscv013_step_or_resume_current_hart()
LOG_DEBUG("resuming hart %d (for step?=%d)", r->current_hartid, step);
riscv.c:372dtmcontrol_scan_via_bscan()
LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
riscv.c:406dtmcontrol_scan()
LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
riscv.c:432riscv_create_target()
LOG_DEBUG("riscv_create_target()");
riscv.c:445riscv_init_target()
LOG_DEBUG("riscv_init_target()");
riscv.c:491riscv_deinit_target()
LOG_DEBUG("riscv_deinit_target()");
riscv.c:572maybe_add_trigger_t1()
LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
riscv.c:575maybe_add_trigger_t1()
LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
riscv.c:622maybe_add_trigger_t2()
LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
riscv.c:625maybe_add_trigger_t2()
LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
riscv.c:674maybe_add_trigger_t6()
LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
riscv.c:677maybe_add_trigger_t6()
LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
riscv.c:724add_trigger()
LOG_DEBUG("trigger %d has unknown type %d", i, type);
riscv.c:731add_trigger()
LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
riscv.c:867riscv_add_breakpoint()
LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
riscv.c:930remove_trigger()
LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
riscv.c:1004riscv_remove_watchpoint()
LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
riscv.c:1027riscv_hit_watchpoint()
LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
riscv.c:1036riscv_hit_watchpoint()
LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
riscv.c:1048riscv_hit_watchpoint()
LOG_DEBUG("Next byte is %x", buffer[i]);
riscv.c:1051riscv_hit_watchpoint()
LOG_DEBUG("Full instruction is %x", instruction);
riscv.c:1065riscv_hit_watchpoint()
LOG_DEBUG("%x is store instruction", instruction);
riscv.c:1068riscv_hit_watchpoint()
LOG_DEBUG("%x is load instruction", instruction);
riscv.c:1075riscv_hit_watchpoint()
LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
riscv.c:1077riscv_hit_watchpoint()
LOG_DEBUG("%x is not a RV32I load or store", instruction);
riscv.c:1085riscv_hit_watchpoint()
LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
riscv.c:1111old_or_new_riscv_step()
LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
riscv.c:1121riscv_examine()
LOG_DEBUG("riscv_examine()");
riscv.c:1123riscv_examine()
LOG_DEBUG("Target was already examined.");
riscv.c:1131riscv_examine()
LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
riscv.c:1133riscv_examine()
LOG_DEBUG(" version=0x%x", info->dtm_version);
riscv.c:1170halt_prep()
LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
riscv.c:1175halt_prep()
LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
riscv.c:1193riscv_halt_go_all_harts()
LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
riscv.c:1235riscv_halt()
LOG_DEBUG("[%d] halting all harts", target->coreid);
riscv.c:1275riscv_assert_reset()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:1283riscv_deassert_reset()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:1292riscv_resume_prep_all_harts()
LOG_DEBUG("[%s] prep hart", target_name(target));
riscv.c:1299riscv_resume_prep_all_harts()
LOG_DEBUG("[%s] hart requested resume, but was already resumed",
riscv.c:1303riscv_resume_prep_all_harts()
LOG_DEBUG("[%s] mark as prepped", target_name(target));
riscv.c:1314disable_triggers()
LOG_DEBUG("deal with triggers");
riscv.c:1344disable_triggers()
LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set);
riscv.c:1382enable_triggers()
LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
riscv.c:1402resume_prep()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:1427resume_prep()
LOG_DEBUG("[%d] mark as prepped", target->coreid);
riscv.c:1474riscv_resume()
LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
riscv.c:1546riscv_mmu()
LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
riscv.c:1553riscv_mmu()
LOG_DEBUG("Couldn't read SATP.");
riscv.c:1560riscv_mmu()
LOG_DEBUG("MMU is disabled.");
riscv.c:1563riscv_mmu()
LOG_DEBUG("MMU is enabled.");
riscv.c:1607riscv_address_translate()
LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
riscv.c:1639riscv_address_translate()
LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
riscv.c:1671riscv_address_translate()
LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
riscv.c:1764riscv_get_gdb_reg_list_internal()
LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
riscv.c:1852riscv_run_algorithm()
LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
riscv.c:1856riscv_run_algorithm()
LOG_DEBUG("save %s", reg_params[i].reg_name);
riscv.c:1889riscv_run_algorithm()
LOG_DEBUG("Disabling Interrupts");
riscv.c:1906riscv_run_algorithm()
LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
riscv.c:1912riscv_run_algorithm()
LOG_DEBUG("poll()");
riscv.c:1959riscv_run_algorithm()
LOG_DEBUG("Restoring Interrupts");
riscv.c:1979riscv_run_algorithm()
LOG_DEBUG("restore %s", reg_params[i].reg_name);
riscv.c:1999riscv_checksum_memory()
LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
riscv.c:2072riscv_checksum_memory()
LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
riscv.c:2091riscv_poll_hart()
LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
riscv.c:2097riscv_poll_hart()
LOG_DEBUG(" triggered a halt");
riscv.c:2101riscv_poll_hart()
LOG_DEBUG(" triggered running");
riscv.c:2132set_debug_reason()
LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
riscv.c:2143sample_memory()
LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
riscv.c:2186riscv_openocd_poll()
LOG_DEBUG("polling all harts");
riscv.c:2237riscv_openocd_poll()
LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
riscv.c:2244riscv_openocd_poll()
LOG_DEBUG("halt all");
riscv.c:2247riscv_openocd_poll()
LOG_DEBUG("resume all");
riscv.c:2274riscv_openocd_poll()
LOG_DEBUG(" hart %d halted", halted_hart);
riscv.c:2306riscv_openocd_step()
LOG_DEBUG("stepping rtos hart");
riscv.c:3153riscv_resume_go_all_harts()
LOG_DEBUG("[%s] resuming hart", target_name(target));
riscv.c:3160riscv_resume_go_all_harts()
LOG_DEBUG("[%s] hart requested resume, but was already resumed",
riscv.c:3175riscv_step_rtos_hart()
LOG_DEBUG("[%s] stepping", target_name(target));
riscv.c:3221riscv_set_current_hartid()
LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
riscv.c:3231riscv_invalidate_register_cache()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:3311riscv_set_register()
LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
riscv.c:3329riscv_set_register()
LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
riscv.c:3343riscv_get_register()
LOG_DEBUG("[%s] %s does not exist.",
riscv.c:3350riscv_get_register()
LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
riscv.c:3367riscv_get_register()
LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
riscv.c:3462riscv_enumerate_triggers()
LOG_DEBUG("[%s] Cannot access tselect register. "
riscv.c:3721register_get()
LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
riscv.c:3734register_set()
LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
riscv.c:3808riscv_init_registers()
LOG_DEBUG("create register cache for %d registers",
riscv.c:4350riscv_init_registers()
LOG_DEBUG("Exposing additional CSR %d (name=%s)",
riscv.c:4395riscv_init_registers()
LOG_DEBUG("Exposing additional custom register %d (name=%s)",
riscv_semihosting.c:60riscv_semihosting()
LOG_DEBUG(" -> NONE (!semihosting)");
riscv_semihosting.c:65riscv_semihosting()
LOG_DEBUG(" -> NONE (!semihosting->is_active)");
riscv_semihosting.c:95riscv_semihosting()
LOG_DEBUG("check %08x %08x %08x from 0x%" PRIx64 "-4", pre, ebreak, post, pc);
riscv_semihosting.c:99riscv_semihosting()
LOG_DEBUG(" -> NONE (no magic)");
riscv_semihosting.c:114riscv_semihosting()
LOG_DEBUG(" -> ERROR (couldn't read a0)");
riscv_semihosting.c:120riscv_semihosting()
LOG_DEBUG(" -> ERROR (couldn't read a1)");
riscv_semihosting.c:139riscv_semihosting()
LOG_DEBUG(" -> NONE (unknown operation number)");
riscv_semihosting.c:154riscv_semihosting()
LOG_DEBUG(" -> HANDLED");
riscv_semihosting.c:158riscv_semihosting()
LOG_DEBUG(" -> WAITING");
riscv_semihosting.c:171riscv_semihosting_setup()
LOG_DEBUG("[%s] enable=%d", target_name(target), enable);
riscv_semihosting.c:188riscv_semihosting_post_result()
LOG_DEBUG("0x%" PRIx64, semihosting->result);
rlink.c:472dtc_run_download()
LOG_DEBUG("%d/%d", command_buffer_size, reply_buffer_size);
rlink.c:867rlink_state_move()
tap_set_state(tap_get_end_state());
rlink.c:891rlink_path_move()
tap_set_state(cmd->path[state_count]);
rlink.c:1256rlink_scan()
tap_set_state(ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE);
rlink.c:1300rlink_execute_queue()
LOG_DEBUG_IO("reset trst: %i srst %i",
rlink.c:1306rlink_execute_queue()
tap_set_state(TAP_RESET);
rlink.c:1310rlink_execute_queue()
LOG_DEBUG_IO("runtest %i cycles, end in %i",
rlink.c:1318rlink_execute_queue()
LOG_DEBUG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
rlink.c:1324rlink_execute_queue()
LOG_DEBUG_IO("pathmove: %u states, end in %i",
rlink.c:1330rlink_execute_queue()
LOG_DEBUG_IO("%s scan end in %i",
rlink.c:1341rlink_execute_queue()
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
rlink.c:1471rlink_init()
LOG_DEBUG("Opened device, hdev = %p", hdev);
rlink.c:1485rlink_init()
LOG_DEBUG("interface claimed!");
rlink.c:1531rlink_init()
LOG_DEBUG(INTERFACE_NAME " firmware version: %d.%d.%d",
rp2040.c:106rp2040_call_rom_func()
LOG_TARGET_DEBUG(target, "Calling ROM func @0x%" PRIx16 " with %u arguments", func_offset, n_args);
rp2040.c:124rp2040_call_rom_func()
LOG_DEBUG("Set %s = 0x%" PRIx32, args[i].reg_name, buf_get_u32(args[i].value, 0, 32));
rp2040.c:161rp2040_finalize_stack_free()
LOG_DEBUG("Flushing flash cache after write behind");
rp2040.c:168rp2040_finalize_stack_free()
LOG_DEBUG("Configuring SSI for execute-in-place");
rp2040.c:197rp2040_stack_grab_and_prep()
LOG_DEBUG("Connecting internal flash");
rp2040.c:204rp2040_stack_grab_and_prep()
LOG_DEBUG("Kicking flash out of XIP mode");
rp2040.c:216rp2040_flash_write()
LOG_DEBUG("Writing %d bytes starting at 0x%" PRIx32, count, offset);
rp2040.c:243rp2040_flash_write()
LOG_DEBUG("Allocated flash bounce buffer @" TARGET_ADDR_FMT, bounce->address);
rp2040.c:247rp2040_flash_write()
LOG_DEBUG("Writing %d bytes to offset 0x%" PRIx32, write_size, offset);
rp2040.c:290rp2040_flash_erase()
LOG_DEBUG("RP2040 erase %d bytes starting at 0x%" PRIx32, length, start_addr);
rp2040.c:296rp2040_flash_erase()
LOG_DEBUG("Remote call flash_range_erase");
rp2040.c:442rp2040_flash_probe()
LOG_DEBUG("SPI flash autodetection disabled, using configured size");
rs14100.c:167rs14100_init()
LOG_DEBUG("Running flash init algorithm");
rs14100.c:280rs14100_erase()
LOG_DEBUG("Running flash erase algorithm");
rsl10.c:345rsl10_ll_flash_erase()
LOG_DEBUG("erasing buffer flash address=0x%" PRIx32, address);
rsl10.c:405rsl10_ll_flash_write()
LOG_DEBUG("Writing 0x%" PRIx32 " to flash address=0x%" PRIx32 " bytes=0x%" PRIx32, data, address, bytes);
rsl10.c:407rsl10_ll_flash_write()
LOG_DEBUG("Writing buffer to flash address=0x%" PRIx32 " bytes=0x%" PRIx32, address, bytes);
rsl10.c:463rsl10_ll_flash_write()
LOG_DEBUG(
rtkernel.c:131rtkernel_add_task()
LOG_DEBUG("task name at 0x%" PRIx32 ", value \"%s\"", name, tmp_str);
rtkernel.c:146rtkernel_add_task()
LOG_DEBUG("task state 0x%" PRIx16, state);
rtkernel.c:227rtkernel_update_threads()
LOG_DEBUG("current task is 0x%" PRIx32, current_task);
rtkernel.c:237rtkernel_update_threads()
LOG_DEBUG("chain start at 0x%" PRIx32, chain);
rtkernel.c:246rtkernel_update_threads()
LOG_DEBUG("next entry at 0x%" PRIx32, next);
rtkernel.c:248rtkernel_update_threads()
LOG_DEBUG("end of chain detected");
rtkernel.c:252rtkernel_update_threads()
LOG_DEBUG("found task at 0x%" PRIx32, task);
rtkernel.c:291rtkernel_get_thread_reg_list()
LOG_DEBUG("stack pointer at 0x%" PRIx64 ", value 0x%" PRIx32,
rtkernel.c:321rtkernel_get_thread_reg_list()
LOG_DEBUG("cm3 stacking");
rtkernel.c:334rtkernel_get_thread_reg_list()
LOG_DEBUG("cm4f_fpu stacking");
rtkernel.c:338rtkernel_get_thread_reg_list()
LOG_DEBUG("cm4f stacking");
rtos.c:274rtos_qsymbol()
LOG_DEBUG("RTOS: Address of symbol '%s%s' is 0x%" PRIx64, cur_sym, cur_suffix, addr);
rtos.c:316rtos_qsymbol()
LOG_DEBUG("RTOS: Requesting symbol lookup of '%s%s' from the debugger", next_sym->symbol_name, next_suffix);
rtos.c:465rtos_thread_packet()
LOG_DEBUG("RTOS: GDB requested to set current thread to 0x%" PRIx64, threadid);
rtos.c:514rtos_get_gdb_reg()
LOG_DEBUG("getting register %d for thread 0x%" PRIx64
rtos.c:566rtos_get_gdb_reg_list()
LOG_DEBUG("RTOS: getting register list for thread 0x%" PRIx64
rtos.c:629rtos_generic_stack_read()
LOG_DEBUG("RTOS: Read stack frame at 0x%" PRIx32, address);
rtos_standard_stackings.c:165rtos_cortex_m_stack_align()
LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
rtt.c:216rtt_register_sink()
LOG_DEBUG("rtt: Registering sink for channel %u", channel_index);
rtt.c:237rtt_unregister_sink()
LOG_DEBUG("rtt: Unregistering sink for channel %u", channel_index);
rtt.c:214target_rtt_write_callback()
LOG_DEBUG("rtt: Wrote %zu bytes into down-channel %u", *length,
rtt_server.c:62rtt_new_connection()
LOG_DEBUG("rtt: New connection for channel %u", service->channel);
rtt_server.c:82rtt_connection_closed()
LOG_DEBUG("rtt: Connection for channel %u closed", service->channel);
semihosting_common.c:107semihosting_common_init()
LOG_DEBUG(" ");
semihosting_common.c:390semihosting_common()
LOG_DEBUG("op=0x%x (%s), param=0x%" PRIx64, semihosting->op,
semihosting_common.c:452semihosting_common()
LOG_DEBUG("ignoring semihosting attempt to close %s",
semihosting_common.c:468semihosting_common()
LOG_DEBUG("close(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:693semihosting_common()
LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:696semihosting_common()
LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:753semihosting_common()
LOG_DEBUG("SYS_GET_CMDLINE=[%s], %" PRId64, arg, semihosting->result);
semihosting_common.c:847semihosting_common()
LOG_DEBUG("isatty(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:966semihosting_common()
LOG_DEBUG("dup(STDIN)=%d", fd);
semihosting_common.c:970semihosting_common()
LOG_DEBUG("dup(STDOUT)=%d", fd);
semihosting_common.c:974semihosting_common()
LOG_DEBUG("dup(STDERR)=%d", fd);
semihosting_common.c:988semihosting_common()
LOG_DEBUG("open('%s')=%" PRId64, fn, semihosting->result);
semihosting_common.c:1051semihosting_common()
LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%" PRId64,
semihosting_common.c:1091semihosting_common()
LOG_DEBUG("getchar()=%" PRId64, semihosting->result);
semihosting_common.c:1138semihosting_common()
LOG_DEBUG("remove('%s')=%" PRId64, fn, semihosting->result);
semihosting_common.c:1209semihosting_common()
LOG_DEBUG("rename('%s', '%s')=%" PRId64 " %d", fn1, fn2, semihosting->result, errno);
semihosting_common.c:1255semihosting_common()
LOG_DEBUG("lseek(%d, %d)=%" PRId64, fd, (int)pos, semihosting->result);
semihosting_common.c:1314semihosting_common()
LOG_DEBUG("system('%s')=%" PRId64, cmd, semihosting->result);
semihosting_common.c:1392semihosting_common()
LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%" PRId64,
server.c:608sig_handler()
LOG_DEBUG("Terminating on Signal %d", sig);
server.c:610sig_handler()
LOG_DEBUG("Ignored extra Signal %d", sig);
sfdp.c:76spi_sfdp()
LOG_DEBUG("header 0x%08" PRIx32 " 0x%08" PRIx32, header.signature, header.revision);
sfdp.c:89spi_sfdp()
LOG_DEBUG("parameter headers: %d", nph);
sfdp.c:106spi_sfdp()
LOG_DEBUG("pheader %d len=0x%02" PRIx8 " id=0x%04" PRIx16
sfdp.c:121spi_sfdp()
LOG_DEBUG("word %02d 0x%08X", j + 1, ptable[j]);
sfdp.c:133spi_sfdp()
LOG_DEBUG("basic flash parameter table");
sfdp.c:233spi_sfdp()
LOG_DEBUG("unimplemented parameter table id=0x%04" PRIx16, id);
sh_qspi.c:448sh_qspi_erase()
LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
sh_qspi.c:498sh_qspi_write()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
sh_qspi.c:531sh_qspi_write()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
sh_qspi.c:602sh_qspi_read()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
sh_qspi.c:776sh_qspi_probe()
LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
sh_qspi.c:878sh_qspi_flash_bank_command()
LOG_DEBUG("%s", __func__);
sim3x.c:864ap_write_register()
LOG_DEBUG("DAP_REG[0x%02x] <- %08" PRIX32, reg, value);
sim3x.c:868ap_write_register()
LOG_DEBUG("DAP: failed to get AP");
sim3x.c:874ap_write_register()
LOG_DEBUG("DAP: failed to queue a write request");
sim3x.c:882ap_write_register()
LOG_DEBUG("DAP: dap_run failed");
sim3x.c:893ap_read_register()
LOG_DEBUG("DAP: failed to get AP");
sim3x.c:899ap_read_register()
LOG_DEBUG("DAP: failed to queue a read request");
sim3x.c:907ap_read_register()
LOG_DEBUG("DAP: dap_run failed");
sim3x.c:911ap_read_register()
LOG_DEBUG("DAP_REG[0x%02x]: %08" PRIX32, reg, *result);
sim3x.c:928ap_poll_register()
LOG_DEBUG("DAP: polling timed out");
stellaris.c:529stellaris_set_flash_timing()
LOG_DEBUG("usecrl = %i", (int)(usecrl));
stellaris.c:576stellaris_read_clock_info()
LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
stellaris.c:579stellaris_read_clock_info()
LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
stellaris.c:582stellaris_read_clock_info()
LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
stellaris.c:662stellaris_read_part_info()
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
stellaris.c:1038stellaris_write_block()
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
stellaris.c:1044stellaris_write_block()
LOG_DEBUG("no working area for block memory writes");
stellaris.c:1059stellaris_write_block()
LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
stellaris.c:1118stellaris_write()
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
stellaris.c:1151stellaris_write()
LOG_DEBUG("writing flash word-at-a-time");
stellaris.c:1168stellaris_write()
LOG_DEBUG("0x%" PRIx32 "", address);
stellaris.c:1192stellaris_write()
LOG_DEBUG("0x%" PRIx32 "", address);
stellaris.c:1208stellaris_write()
LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
stlink_usb.c:669jtag_libusb_bulk_transfer_n()
LOG_DEBUG("ERROR, failed to alloc usb transfers");
stlink_usb.c:686jtag_libusb_bulk_transfer_n()
LOG_DEBUG("ERROR, failed to submit transfer %zu, error %d", i, retval);
stlink_usb.c:709jtag_libusb_bulk_transfer_n()
LOG_DEBUG("ERROR, transfer %zu failed, error %d", i, retval);
stlink_usb.c:904stlink_usb_usb_xfer_noerrcheck()
LOG_DEBUG("get sense");
stlink_usb.c:927stlink_tcp_send_cmd()
LOG_DEBUG("socket send error: %s (errno %d)", strerror(errno), errno);
stlink_usb.c:929stlink_tcp_send_cmd()
LOG_DEBUG("sent size %d (expected %d)", sent_size, send_size);
stlink_usb.c:941stlink_tcp_send_cmd()
LOG_DEBUG("received size %d (expected %d)", recv_size - remaining_bytes, recv_size);
stlink_usb.c:950stlink_tcp_send_cmd()
LOG_DEBUG("socket recv error: %s (errno %d)", strerror(errno), errno);
stlink_usb.c:968stlink_tcp_send_cmd()
LOG_DEBUG("TCP busy");
stlink_usb.c:1066stlink_usb_error_check()
LOG_DEBUG("unknown/unexpected STLINK status code 0x%x", h->databuf[0]);
stlink_usb.c:1079stlink_usb_error_check()
LOG_DEBUG("SWD fault response (0x%x)", STLINK_DEBUG_ERR_FAULT);
stlink_usb.c:1082stlink_usb_error_check()
LOG_DEBUG("wait status SWD_AP_WAIT (0x%x)", STLINK_SWD_AP_WAIT);
stlink_usb.c:1085stlink_usb_error_check()
LOG_DEBUG("wait status SWD_DP_WAIT (0x%x)", STLINK_SWD_DP_WAIT);
stlink_usb.c:1088stlink_usb_error_check()
LOG_DEBUG("STLINK_JTAG_GET_IDCODE_ERROR");
stlink_usb.c:1091stlink_usb_error_check()
LOG_DEBUG("Write error");
stlink_usb.c:1094stlink_usb_error_check()
LOG_DEBUG("Write verify error, ignoring");
stlink_usb.c:1102stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_AP_FAULT");
stlink_usb.c:1105stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_AP_ERROR");
stlink_usb.c:1108stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_AP_PARITY_ERROR");
stlink_usb.c:1111stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_DP_FAULT");
stlink_usb.c:1114stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_DP_ERROR");
stlink_usb.c:1117stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_DP_PARITY_ERROR");
stlink_usb.c:1120stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_AP_WDATA_ERROR");
stlink_usb.c:1123stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_AP_STICKY_ERROR");
stlink_usb.c:1126stlink_usb_error_check()
LOG_DEBUG("STLINK_SWD_AP_STICKYORUN_ERROR");
stlink_usb.c:1129stlink_usb_error_check()
LOG_DEBUG("STLINK_BAD_AP_ERROR");
stlink_usb.c:1132stlink_usb_error_check()
LOG_DEBUG("unknown/unexpected STLINK status code 0x%x", h->databuf[0]);
stlink_usb.c:1183stlink_cmd_allow_retry()
LOG_DEBUG("stlink_cmd_allow_retry ERROR_WAIT, retry %d, delaying %u microseconds", retries, delay_us);
stlink_usb.c:1696stlink_usb_exit_mode()
LOG_DEBUG("MODE: 0x%02X", mode);
stlink_usb.c:1764stlink_usb_init_mode()
LOG_DEBUG("MODE: 0x%02X", mode);
stlink_usb.c:1824stlink_usb_init_mode()
LOG_DEBUG("MODE: 0x%02X", mode);
stlink_usb.c:2057stlink_usb_idcode()
LOG_DEBUG("IDCODE: 0x%08" PRIX32, *idcode);
stlink_usb.c:2230stlink_usb_trace_disable()
LOG_DEBUG("Tracing: disable");
stlink_usb.c:2264stlink_usb_trace_enable()
LOG_DEBUG("Tracing: recording at %" PRIu32 "Hz", h->trace.source_hz);
stlink_usb.c:2502stlink_usb_read_mem8()
LOG_DEBUG("max buffer (%d) length exceeded", stlink_usb_block(h));
stlink_usb.c:2546stlink_usb_write_mem8()
LOG_DEBUG("max buffer length (%d) exceeded", stlink_usb_block(h));
stlink_usb.c:2586stlink_usb_read_mem16()
LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2592stlink_usb_read_mem16()
LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2634stlink_usb_write_mem16()
LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2640stlink_usb_write_mem16()
LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2677stlink_usb_read_mem32()
LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2683stlink_usb_read_mem32()
LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2722stlink_usb_write_mem32()
LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2728stlink_usb_write_mem32()
LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2763stlink_usb_read_mem32_noaddrinc()
LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2769stlink_usb_read_mem32_noaddrinc()
LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2805stlink_usb_write_mem32_noaddrinc()
LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2811stlink_usb_write_mem32_noaddrinc()
LOG_DEBUG("Invalid data alignment");
stlink_usb.c:3130stlink_dump_speed_map()
LOG_DEBUG("Supported clock speeds are:");
stlink_usb.c:3133stlink_dump_speed_map()
LOG_DEBUG("%d kHz", map[i].speed);
stlink_usb.c:3418stlink_usb_usb_open()
LOG_DEBUG("claim interface failed");
stlink_usb.c:3427stlink_usb_usb_open()
LOG_DEBUG("libusb_get_pid failed");
stlink_usb.c:3540stlink_tcp_open()
LOG_DEBUG("socket : %x", h->tcp_backend_priv.fd);
stlink_usb.c:3614stlink_tcp_open()
LOG_DEBUG("%d ST-LINK detected", connected_stlinks);
stlink_usb.c:3676stlink_tcp_open()
LOG_DEBUG("Device serial number '%s' doesn't match requested serial '%s'",
stlink_usb.c:3698stlink_tcp_open()
LOG_DEBUG("transport: vid: 0x%04x pid: 0x%04x serial: %s", h->vid, h->pid, serial);
stlink_usb.c:3732stlink_open()
LOG_DEBUG("stlink_open");
stlink_usb.c:3737stlink_open()
LOG_DEBUG("malloc failed");
stlink_usb.c:3744stlink_open()
LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x serial: %s",
stlink_usb.c:3820stlink_open()
LOG_DEBUG("Using TAR autoincrement: %" PRIu32, h->max_mem_packet);
stlink_usb.c:3910stlink_usb_init_access_port()
LOG_DEBUG_IO("init ap_num = %d", ap_num);
stlink_usb.c:3929stlink_usb_close_access_port()
LOG_DEBUG_IO("close ap_num = %d", ap_num);
stlink_usb.c:3948stlink_usb_rw_misc_out()
LOG_DEBUG_IO("%s(%" PRIu32 ")", __func__, items);
stlink_usb.c:3969stlink_usb_rw_misc_in()
LOG_DEBUG_IO("%s(%" PRIu32 ")", __func__, items);
stlink_usb.c:4010stlink_read_dap_register()
LOG_DEBUG_IO("dap_port_read = %d, addr = 0x%x, value = 0x%" PRIx32, dap_port, addr, *val);
stlink_usb.c:4025stlink_write_dap_register()
LOG_DEBUG_IO("dap_write port = %d, addr = 0x%x, value = 0x%" PRIx32, dap_port, addr, val);
stlink_usb.c:4127stlink_usb_open_ap()
LOG_DEBUG("AP %d enabled", apsel);
stlink_usb.c:4297stlink_dap_dp_write()
LOG_DEBUG("Ignoring DPBANKSEL while write SELECT");
stlink_usb.c:4377stlink_usb_misc_rw_segment()
LOG_DEBUG("Queue: %u commands in %u items", len, items);
stlink_usb.c:4921stlink_swim_op_read_mem()
LOG_DEBUG_IO("read at 0x%08" PRIx32 " len %" PRIu32 "*0x%08" PRIx32, addr, size, count);
stlink_usb.c:4944stlink_swim_op_write_mem()
LOG_DEBUG_IO("write at 0x%08" PRIx32 " len %" PRIu32 "*0x%08" PRIx32, addr, size, count);
stlink_usb.c:5120stlink_dap_init()
LOG_DEBUG("stlink_dap_init()");
stlink_usb.c:5155stlink_dap_quit()
LOG_DEBUG("stlink_dap_quit()");
stlink_usb.c:5163stlink_dap_reset()
LOG_DEBUG("stlink_dap_reset(%d)", req_srst);
stm32f1x.c:173stm32x_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32f2x.c:284stm32x_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32, status);
stm32f2x.c:573stm32x_protect_check()
LOG_DEBUG("unable to read option bytes");
stm32f2x.c:677stm32x_protect()
LOG_DEBUG("unable to read option bytes");
stm32f2x.c:902setup_sector()
LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
stm32f2x.c:1150stm32x_probe()
LOG_DEBUG("unable to read option bytes");
stm32f2x.c:1167stm32x_probe()
LOG_DEBUG("unable to read option bytes");
stm32f2x.c:1192stm32x_probe()
LOG_DEBUG("allocated %u sectors", num_pages);
stm32f2x.c:1202stm32x_probe()
LOG_DEBUG("allocated %u prot blocks", num_prot_blocks);
stm32g0x.c:207stm32x_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32g4x.c:387stm32l4_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32h7x.c:453stm32x_protect_check()
LOG_DEBUG("unable to read WPSN_CUR register");
stm32h7x.c:490stm32x_erase()
LOG_DEBUG("erase sector %u", i);
stm32h7x.c:534stm32x_protect()
LOG_DEBUG("unable to read WPSN_CUR register");
stm32h7x.c:548stm32x_protect()
LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
stm32h7x.c:604stm32x_write_block()
LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
stm32h7x.c:768stm32x_probe()
LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
stm32h7x.c:792stm32x_probe()
LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
stm32h7x.c:973stm32x_set_rdp()
LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
stm32l4x.c:878stm32l4_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32l4x.c:924stm32l4_set_secbb()
LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
stm32l4x.c:1355stm32l4_protect_same_bank()
LOG_DEBUG("current protected areas: %s", ranges_str);
stm32l4x.c:1358stm32l4_protect_same_bank()
LOG_DEBUG("current protected areas: none");
stm32l4x.c:1374stm32l4_protect_same_bank()
LOG_DEBUG("requested areas for protection: %s", ranges_str);
stm32l4x.c:1377stm32l4_protect_same_bank()
LOG_DEBUG("requested areas for protection: none");
stm32l4x.c:1647stm32l4_write()
LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
stm32l4x.c:2129stm32l4_probe()
LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
stm32l5x.c:247stm32l4_wait_status_busy()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32lx.c:444stm32lx_write_half_pages()
LOG_DEBUG("no working area for block memory writes");
stm32lx.c:748stm32lx_probe()
LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
stm32lx.c:1207stm32lx_wait_until_bsy_clear_timeout()
LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm8.c:326stm8_set_hwbreak()
LOG_DEBUG("DM_BKR1E=%" PRIx32, data);
stm8.c:329stm8_set_hwbreak()
LOG_DEBUG("DM_BKR2E=%" PRIx32, data);
stm8.c:331stm8_set_hwbreak()
LOG_DEBUG("addr=%" PRIu32, addr);
stm8.c:340stm8_set_hwbreak()
LOG_DEBUG("DM_CR1=%" PRIx8, buf[0]);
stm8.c:418stm8_configure_break_unit()
LOG_DEBUG("hw breakpoints: numinst %i numdata %i", stm8->num_hw_bpoints,
stm8.c:433stm8_examine_debug_reason()
LOG_DEBUG("csr1 = 0x%02X csr2 = 0x%02X", csr1, csr2);
stm8.c:473stm8_debug_entry()
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
stm8.c:742stm8_write_memory()
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR
stm8.c:773stm8_read_memory()
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR
stm8.c:795stm8_speed()
LOG_DEBUG("stm8_speed: %d", speed);
stm8.c:801stm8_speed()
LOG_DEBUG("writing B0 to SWIM_CSR (SAFE_MASK + SWIM_DM + HS:%d)", csr & HS ? 1 : 0);
stm8.c:836stm8_poll()
LOG_DEBUG("stm8_read_dm_csrx failed retval=%d", retval);
stm8.c:848stm8_poll()
LOG_DEBUG("DM_CSR2_STALL already set during server startup.");
stm8.c:852stm8_poll()
LOG_DEBUG("stm8_debug_entry failed retval=%d", retval);
stm8.c:874stm8_halt()
LOG_DEBUG("target->state: %s", target_state_name(target));
stm8.c:877stm8_halt()
LOG_DEBUG("target was already halted");
stm8.c:921stm8_reset_assert()
LOG_DEBUG("Hardware srst not supported, falling back to swim reset");
stm8.c:993stm8_resume()
LOG_DEBUG("%d " TARGET_ADDR_FMT " %d %d", current, address,
stm8.c:1032stm8_resume()
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT,
stm8.c:1054stm8_resume()
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
stm8.c:1058stm8_resume()
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
stm8.c:1134stm8_read_core_reg()
LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num, reg_value);
stm8.c:1154stm8_write_core_reg()
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
stm8.c:1298stm8_step()
LOG_DEBUG("%x " TARGET_ADDR_FMT " %x",
stm8.c:1345stm8_step()
LOG_DEBUG("target stepped ");
stm8.c:1399stm8_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
stm8.c:1403stm8_set_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
stm8.c:1476stm8_unset_breakpoint()
LOG_DEBUG("Invalid comparator number in breakpoint (bpid: %" PRIu32 ")",
stm8.c:1480stm8_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
stm8.c:1489stm8_unset_breakpoint()
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
stm8.c:1587stm8_set_watchpoint()
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "",
stm8.c:1639stm8_unset_watchpoint()
LOG_DEBUG("Invalid hw comparator number in watchpoint");
stm8.c:1812stm8_run_and_wait()
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
stm8.c:1829stm8_run_algorithm()
LOG_DEBUG("Running algorithm");
stm8.c:1923stm8_run_algorithm()
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
stm8.c:1959stm8_jim_configure()
LOG_DEBUG("blocksize=%8.8" PRIx32, stm8->blocksize);
stm8.c:1978stm8_jim_configure()
LOG_DEBUG("flashstart=%8.8" PRIx32, stm8->flashstart);
stm8.c:1997stm8_jim_configure()
LOG_DEBUG("flashend=%8.8" PRIx32, stm8->flashend);
stm8.c:2016stm8_jim_configure()
LOG_DEBUG("eepromstart=%8.8" PRIx32, stm8->eepromstart);
stm8.c:2035stm8_jim_configure()
LOG_DEBUG("eepromend=%8.8" PRIx32, stm8->eepromend);
stm8.c:2054stm8_jim_configure()
LOG_DEBUG("optionstart=%8.8" PRIx32, stm8->optionstart);
stm8.c:2073stm8_jim_configure()
LOG_DEBUG("optionend=%8.8" PRIx32, stm8->optionend);
stm8.c:2082stm8_jim_configure()
LOG_DEBUG("enable_step_irq=%8.8x", stm8->enable_step_irq);
stm8.c:2091stm8_jim_configure()
LOG_DEBUG("enable_stm8l=%8.8x", stm8->enable_stm8l);
stmqspi.c:210stmqspi_flash_bank_command()
LOG_DEBUG("%s", __func__);
stmqspi.c:253poll_busy()
LOG_DEBUG("busy: 0x%08X", spi_sr);
stmqspi.c:388read_status_reg()
LOG_DEBUG("flash status regs: 0x%04" PRIx16, *status);
stmqspi.c:496stmqspi_handle_mass_erase_command()
LOG_DEBUG("%s", __func__);
stmqspi.c:617stmqspi_handle_set()
LOG_DEBUG("%s", __func__);
stmqspi.c:727stmqspi_handle_set()
LOG_DEBUG("FSIZE = 0x%04x", fsize);
stmqspi.c:729stmqspi_handle_set()
LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
stmqspi.c:731stmqspi_handle_set()
LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
stmqspi.c:781stmqspi_handle_cmd()
LOG_DEBUG("%s", __func__);
stmqspi.c:960qspi_erase_sector()
LOG_DEBUG("erase status regs: 0x%04" PRIx16, status);
stmqspi.c:986qspi_erase_sector()
LOG_DEBUG("erasing sector %4u", sector);
stmqspi.c:1002stmqspi_erase()
LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
stmqspi.c:1193stmqspi_blank_check()
LOG_DEBUG("checking sectors %u to %u", sector, sector + count - 1);
stmqspi.c:1220stmqspi_blank_check()
LOG_DEBUG("Flash sector %u checked: 0x%04x", sector + index, result & 0xFFFFU);
stmqspi.c:1346qspi_verify()
LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
stmqspi.c:1381qspi_read_write_block()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
stmqspi.c:1576stmqspi_read()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmqspi.c:1616stmqspi_write()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmqspi.c:1677stmqspi_verify()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmqspi.c:1731find_sfdp_dummy()
LOG_DEBUG("%s: len=%d, dual=%u, flash1=%d",
stmqspi.c:1782find_sfdp_dummy()
LOG_DEBUG("start of SFDP header for flash%c after %u dummy bytes",
stmqspi.c:1799find_sfdp_dummy()
LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count);
stmqspi.c:1851read_sfdp_block()
LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08x dummy=%u",
stmqspi.c:1923read_sfdp_block()
LOG_DEBUG("raw SFDP data 0x%08" PRIx32, *buffer);
stmqspi.c:2110stmqspi_probe()
LOG_DEBUG("QSPI_ABR register present");
stmqspi.c:2118stmqspi_probe()
LOG_DEBUG("OCTOSPI_MAGIC present");
stmqspi.c:2162stmqspi_probe()
LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
stmqspi.c:2167stmqspi_probe()
LOG_DEBUG("QSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", QSPI_CR 0x%08"
stmqspi.c:2189stmqspi_probe()
LOG_DEBUG("id1 0x%06" PRIx32 ", id2 0x%06" PRIx32, id1, id2);
stmqspi.c:2325stmqspi_probe()
LOG_DEBUG("FSIZE = 0x%04x", fsize);
stmqspi.c:2327stmqspi_probe()
LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
stmqspi.c:2329stmqspi_probe()
LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
stmsmi.c:130stmsmi_flash_bank_command()
LOG_DEBUG("%s", __func__);
stmsmi.c:312stmsmi_erase()
LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
stmsmi.c:367smi_write_buffer()
LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
stmsmi.c:393stmsmi_write()
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmsmi.c:553stmsmi_probe()
LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
str7x.c:338str7x_erase()
LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
str9xpec.c:109str9xpec_isc_status()
LOG_DEBUG("status: 0x%2.2x", status);
str9xpec.c:137str9xpec_isc_enable()
LOG_DEBUG("ISC_MODE Enabled");
str9xpec.c:165str9xpec_isc_disable()
LOG_DEBUG("ISC_MODE Disabled");
str9xpec.c:181str9xpec_read_config()
LOG_DEBUG("ISC_CONFIGURATION");
str9xpec.c:316str9xpec_blank_check()
LOG_DEBUG("blank check: first_bank: %u, last_bank: %u", first, last);
str9xpec.c:397str9xpec_erase_area()
LOG_DEBUG("erase: first_bank: %u, last_bank: %u", first, last);
str9xpec.c:411str9xpec_erase_area()
LOG_DEBUG("ISC_ERASE");
str9xpec.c:509str9xpec_protect()
LOG_DEBUG("protect: first_bank: %u, last_bank: %u", first, last);
str9xpec.c:607str9xpec_write()
LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);
str9xpec.c:611str9xpec_write()
LOG_DEBUG("ISC_PROGRAM");
svf.c:1024svf_run_command()
LOG_DEBUG("\tIR end_state = %s",
svf.c:1028svf_run_command()
LOG_DEBUG("\tDR end_state = %s",
svf.c:1058svf_run_command()
LOG_DEBUG("\tfrequency = %f", svf_para.frequency);
svf.c:1117svf_run_command()
LOG_DEBUG("\tlength = %d", xxr_para_tmp->len);
svf.c:1403svf_run_command()
LOG_DEBUG("\trun_state = %s", tap_state_name(i_tmp));
svf.c:1416svf_run_command()
LOG_DEBUG("\trun_count@TCK = %d", run_count);
svf.c:1426svf_run_command()
LOG_DEBUG("\tmin_time = %fs", min_time);
svf.c:1434svf_run_command()
LOG_DEBUG("\tmax_time = %fs", max_time);
svf.c:1443svf_run_command()
LOG_DEBUG("\tend_state = %s", tap_state_name(i_tmp));
svf.c:1534svf_run_command()
LOG_DEBUG("\tmove to %s by path_move",
svf.c:1551svf_run_command()
LOG_DEBUG("\tmove to %s by svf_add_statemove",
svf.c:1591svf_run_command()
LOG_DEBUG("\ttrst_mode = %s", svf_trst_mode_name[svf_para.trst_mode]);
svf.c:1607svf_run_command()
if (debug_level >= LOG_LVL_DEBUG) {
swim.c:81handle_swim_newtap_command()
LOG_DEBUG("Creating new SWIM \"tap\", Chip: %s, Tap: %s, Dotted: %s",
swim.c:116swim_transport_select()
LOG_DEBUG(__func__);
swim.c:125swim_transport_init()
LOG_DEBUG(__func__);
target.c:674target_examine_one()
LOG_TARGET_DEBUG(target, "Examination started");
target.c:681target_examine_one()
LOG_TARGET_DEBUG(target, "examine() returned error code %d", retval);
target.c:986target_run_flash_async_algorithm()
LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
target.c:1141target_run_read_async_algorithm()
LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
target.c:1598handle_target_init_command()
LOG_DEBUG("Initializing targets...");
target.c:1784target_call_event_callbacks()
LOG_DEBUG("target event %i (%s) for core %s", event,
target.c:1803target_call_reset_callbacks()
LOG_DEBUG("target reset %i (%s)", reset_mode,
target.c:1910print_wa_layout()
LOG_DEBUG("%c%c " TARGET_ADDR_FMT "-" TARGET_ADDR_FMT " (%" PRIu32 " bytes)",
target.c:1989target_alloc_working_area_try()
LOG_DEBUG("MMU disabled, using physical "
target.c:2000target_alloc_working_area_try()
LOG_DEBUG("MMU enabled, using virtual "
target.c:2043target_alloc_working_area_try()
LOG_DEBUG("allocated new working area of %" PRIu32 " bytes at address " TARGET_ADDR_FMT,
target.c:2111target_free_working_area_restore()
LOG_DEBUG("freed %" PRIu32 " bytes of working area at address " TARGET_ADDR_FMT,
target.c:2140target_free_all_working_areas_restore()
LOG_DEBUG("freeing all working areas");
target.c:2354target_write_buffer()
LOG_DEBUG("writing buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
target.c:2419target_read_buffer()
LOG_DEBUG("reading buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
target.c:2548target_read_u64()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2553target_read_u64()
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2572target_read_u32()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2577target_read_u32()
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2596target_read_u16()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%4.4" PRIx16,
target.c:2601target_read_u16()
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2618target_read_u8()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2623target_read_u8()
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2639target_write_u64()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2646target_write_u64()
LOG_DEBUG("failed: %i", retval);
target.c:2660target_write_u32()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2667target_write_u32()
LOG_DEBUG("failed: %i", retval);
target.c:2681target_write_u16()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16,
target.c:2688target_write_u16()
LOG_DEBUG("failed: %i", retval);
target.c:2701target_write_u8()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2706target_write_u8()
LOG_DEBUG("failed: %i", retval);
target.c:2720target_write_phys_u64()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2727target_write_phys_u64()
LOG_DEBUG("failed: %i", retval);
target.c:2741target_write_phys_u32()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2748target_write_phys_u32()
LOG_DEBUG("failed: %i", retval);
target.c:2762target_write_phys_u16()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16,
target.c:2769target_write_phys_u16()
LOG_DEBUG("failed: %i", retval);
target.c:2782target_write_phys_u8()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2787target_write_phys_u8()
LOG_DEBUG("failed: %i", retval);
target.c:3033handle_reg_command()
LOG_DEBUG("-");
target.c:3240target_wait_state()
LOG_DEBUG("waiting for target %s...",
target.c:3262handle_halt_command()
LOG_DEBUG("-");
target.c:3339handle_step_command()
LOG_DEBUG("-");
target.c:4591handle_target_read_memory()
LOG_DEBUG("read_memory: read at " TARGET_ADDR_FMT " with width=%u and count=%zu failed",
target.c:4781target_handle_event()
LOG_DEBUG("target: %s (%s) event: %d (%s) action: %s",
target.c:5985target_create()
LOG_DEBUG("target_create failed");
target.c:6085create_target_list_node()
LOG_DEBUG("%s ", targetname);
target.c:6123handle_target_smp()
LOG_DEBUG("Empty SMP target");
target.c:6126handle_target_smp()
LOG_DEBUG("%d", CMD_ARGC);
target_request.c:45target_asciimsg()
LOG_DEBUG("%s", msg);
target_request.c:70target_hexmsg()
LOG_DEBUG("size: %i, length: %i", (int)size, (int)length);
target_request.c:89target_hexmsg()
LOG_DEBUG("%s", line);
tcl.c:484handle_nand_init_command()
LOG_DEBUG("Initializing NAND devices...");
tcl.c:549create_nand_device()
LOG_DEBUG("'%s' driver usage field missing", controller->name);
tcl.c:1307handle_flash_bank_command()
LOG_DEBUG("'%s' driver usage field missing", driver_name);
tcl.c:1364handle_flash_init_command()
LOG_DEBUG("Initializing flash devices...");
tcl.c:404handle_jtag_newtap_args()
LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
tcl.c:546jtag_tap_handle_event()
LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s",
tcl.c:685handle_jtag_init_command()
LOG_DEBUG("Initializing jtag devices...");
telnet_server.c:822telnet_input()
LOG_DEBUG("unhandled nonprintable: %2.2x", *buf_p);
ti_icdi_usb.c:154icdi_send_packet()
LOG_DEBUG("Error TX Data %d", result);
ti_icdi_usb.c:162icdi_send_packet()
LOG_DEBUG("Error RX Data %d", result);
ti_icdi_usb.c:171icdi_send_packet()
LOG_DEBUG("Resending packet %d", ++retry);
ti_icdi_usb.c:174icdi_send_packet()
LOG_DEBUG("Unexpected Reply from ICDI: %c", h->read_buffer[0]);
ti_icdi_usb.c:179icdi_send_packet()
LOG_DEBUG("maximum nack retries attempted");
ti_icdi_usb.c:201icdi_send_packet()
LOG_DEBUG("Error RX timeout %d", result);
ti_icdi_usb.c:203icdi_send_packet()
LOG_DEBUG("Error RX Data %d", result);
ti_icdi_usb.c:221icdi_send_packet()
LOG_DEBUG("maximum data retries attempted");
ti_icdi_usb.c:372icdi_usb_query()
LOG_DEBUG("max packet supported : %i bytes", h->max_packet);
ti_icdi_usb.c:671icdi_usb_open()
LOG_DEBUG("icdi_usb_open");
ti_icdi_usb.c:681icdi_usb_open()
LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x serial: %s", param->transport,
ti_icdi_usb.c:694icdi_usb_open()
LOG_DEBUG("claim interface failed");
ti_icdi_usb.c:724icdi_usb_open()
LOG_DEBUG("malloc failed");
tms470.c:503tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
tms470.c:511tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
tms470.c:517tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmtcreg = 0x2fc0");
tms470.c:523tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmmaxpp = 50");
tms470.c:529tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
tms470.c:538tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmptr3 = 0x9964");
tms470.c:542tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmptr3 = 0x9b64");
tms470.c:545tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
tms470.c:551tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmptr4 = 0xa000");
tms470.c:565tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
tms470.c:572tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
tms470.c:579tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
tms470.c:581tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
tms470.c:583tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
tms470.c:590tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
tms470.c:597tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
tms470.c:604tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
tms470.c:610tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
tms470.c:612tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
tms470.c:614tms470_flash_initialize_internal_state_machine()
LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
tms470.c:628tms470_flash_status()
LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
tms470.c:683tms470_erase_sector()
LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
tms470.c:688tms470_erase_sector()
LOG_DEBUG("set fmregopt = 0x%08x", 0);
tms470.c:700tms470_erase_sector()
LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
tms470.c:704tms470_erase_sector()
LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
tms470.c:712tms470_erase_sector()
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flash_addr);
tms470.c:714tms470_erase_sector()
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flash_addr);
tms470.c:716tms470_erase_sector()
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flash_addr);
tms470.c:732tms470_erase_sector()
LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
tms470.c:736tms470_erase_sector()
LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
tms470.c:740tms470_erase_sector()
LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
tms470.c:742tms470_erase_sector()
LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
tms470.c:1096tms470_protect_check()
LOG_DEBUG("bank %u sector %u is %s",
trace.c:20trace_point()
LOG_DEBUG("tracepoint: %i", (int)number);
transport.c:146transport_register()
LOG_DEBUG("register '%s'", new_transport->name);
transport.c:219handle_transport_init()
LOG_DEBUG("%s", __func__);
ublast2_access_libusb.c:76ublast2_write_firmware_section()
LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04x)", section_index, addr,
ulink.c:442ulink_write_firmware_section()
LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04x)", section_index, addr,
ulink.c:694ulink_execute_queued_commands()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO))
ulink.c:1429ulink_queue_statemove()
tap_set_state(tap_get_end_state());
ulink.c:1496ulink_queue_scan()
tap_set_state(TAP_IRSHIFT);
ulink.c:1511ulink_queue_scan()
tap_set_state(TAP_DRSHIFT);
ulink.c:1608ulink_queue_scan()
tap_set_state(cmd->cmd.scan->end_state);
ulink.c:1628ulink_queue_tlr_reset()
tap_set_state(TAP_RESET);
ulink.c:1681ulink_queue_reset()
tap_set_state(TAP_RESET);
ulink.c:1739ulink_queue_pathmove()
tap_set_state(path[state_count]);
ulink.c:2023ulink_khz()
LOG_DEBUG_IO("ULINK TCK setup: delay_tck = %i (%li Hz),",
ulink.c:2026ulink_khz()
LOG_DEBUG_IO(" delay_tms = %i (%li Hz),",
ulink.c:2029ulink_khz()
LOG_DEBUG_IO(" delay_scan_in = %i (%li Hz),",
ulink.c:2032ulink_khz()
LOG_DEBUG_IO(" delay_scan_out = %i (%li Hz),",
ulink.c:2035ulink_khz()
LOG_DEBUG_IO(" delay_scan_io = %i (%li Hz),",
usb_blaster.c:166ublast_buf_read()
LOG_DEBUG_IO("(size=%d, buf=[%s]) -> %" PRIu32, size, str,
usb_blaster.c:177ublast_buf_write()
LOG_DEBUG_IO("(size=%d, buf=[%s]) -> %" PRIu32, size, str,
usb_blaster.c:258ublast_queue_byte()
LOG_DEBUG_IO("(byte=0x%02x)", abyte);
usb_blaster.c:329ublast_clock_tms()
LOG_DEBUG_IO("(tms=%d)", !!tms);
usb_blaster.c:346ublast_idle_clock()
LOG_DEBUG_IO(".");
usb_blaster.c:367ublast_clock_tdi()
LOG_DEBUG_IO("(tdi=%d)", !!tdi);
usb_blaster.c:392ublast_clock_tdi_flip_tms()
LOG_DEBUG_IO("(tdi=%d)", !!tdi);
usb_blaster.c:422ublast_queue_bytes()
LOG_DEBUG_IO("(nb_bytes=%d, bytes=[0x%02x, ...])", nb_bytes,
usb_blaster.c:449ublast_tms_seq()
LOG_DEBUG_IO("(bits=%02x..., nb_bits=%d)", bits[0], nb_bits);
usb_blaster.c:461ublast_tms()
LOG_DEBUG_IO("(num_bits=%d)", cmd->num_bits);
usb_blaster.c:477ublast_path_move()
LOG_DEBUG_IO("(num_states=%u, last_state=%d)",
usb_blaster.c:484ublast_path_move()
tap_set_state(cmd->path[i]);
usb_blaster.c:502ublast_state_move()
LOG_DEBUG_IO("(from %s to %s)", tap_state_name(tap_get_state()),
usb_blaster.c:509ublast_state_move()
tap_set_state(state);
usb_blaster.c:531ublast_read_byteshifted_tdos()
LOG_DEBUG_IO("%s(buf=%p, num_bits=%d)", __func__, buf, nb_bytes * 8);
usb_blaster.c:563ublast_read_bitbang_tdos()
LOG_DEBUG_IO("%s(buf=%p, num_bits=%d)", __func__, buf, nb_bits);
usb_blaster.c:678ublast_runtest()
LOG_DEBUG_IO("%s(cycles=%u, end_state=%d)", __func__, num_cycles, state);
usb_blaster.c:687ublast_stableclocks()
LOG_DEBUG_IO("%s(cycles=%u)", __func__, num_cycles);
usb_blaster.c:717ublast_scan()
LOG_DEBUG_IO("%s(scan=%s, type=%s, bits=%d, buf=[%s], end_state=%d)", __func__,
usb_blaster.c:738ublast_usleep()
LOG_DEBUG_IO("%s(us=%d)", __func__, us);
usb_blaster.c:763ublast_initial_wipeout()
tap_set_state(TAP_RESET);
usb_blaster.c:874ublast_init()
tap_set_state(TAP_RESET);
usbprog.c:96usbprog_execute_queue()
LOG_DEBUG_IO("reset trst: %i srst %i",
usbprog.c:100usbprog_execute_queue()
tap_set_state(TAP_RESET);
usbprog.c:104usbprog_execute_queue()
LOG_DEBUG_IO("runtest %u cycles, end in %i",
usbprog.c:111usbprog_execute_queue()
LOG_DEBUG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
usbprog.c:116usbprog_execute_queue()
LOG_DEBUG_IO("pathmove: %u states, end in %i",
usbprog.c:122usbprog_execute_queue()
LOG_DEBUG_IO("scan end in %i", cmd->cmd.scan->end_state);
usbprog.c:132usbprog_execute_queue()
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
usbprog.c:187usbprog_state_move()
tap_set_state(tap_get_end_state());
usbprog.c:217usbprog_path_move()
tap_set_state(cmd->path[state_count]);
usbprog.c:247usbprog_runtest()
LOG_DEBUG_IO("runtest: cur_state %s end_state %s", tap_state_name(
usbprog.c:294usbprog_scan()
tap_set_state(TAP_IRPAUSE);
usbprog.c:296usbprog_scan()
tap_set_state(TAP_DRPAUSE);
usbprog.c:321usbprog_reset()
LOG_DEBUG("trst: %i, srst: %i", trst, srst);
virtex2.c:141virtex2_read_stat()
LOG_DEBUG("status: 0x%8.8" PRIx32, *status);
vsllink.c:94vsllink_execute_queue()
LOG_DEBUG_IO("-------------------------------------"
vsllink.c:101vsllink_execute_queue()
LOG_DEBUG_IO("runtest %u cycles, end in %s",
vsllink.c:110vsllink_execute_queue()
LOG_DEBUG_IO("statemove end in %s",
vsllink.c:118vsllink_execute_queue()
LOG_DEBUG_IO("pathmove: %u states, end in %s",
vsllink.c:126vsllink_execute_queue()
LOG_DEBUG_IO("JTAG Scan...");
vsllink.c:134vsllink_execute_queue()
LOG_DEBUG_IO(
vsllink.c:141vsllink_execute_queue()
LOG_DEBUG_IO(
vsllink.c:147vsllink_execute_queue()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO))
vsllink.c:158vsllink_execute_queue()
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
vsllink.c:164vsllink_execute_queue()
LOG_DEBUG_IO("add %u clocks",
vsllink.c:194vsllink_execute_queue()
LOG_DEBUG_IO("add %d jtag tms",
vsllink.c:286vsllink_interface_init()
LOG_DEBUG("vsllink found on %04X:%04X",
vsllink.c:371vsllink_state_move()
tap_set_state(tap_get_end_state());
vsllink.c:388vsllink_path_move()
tap_set_state(path[i]);
vsllink.c:448vsllink_scan()
tap_set_state(ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE);
vsllink.c:456vsllink_reset()
LOG_DEBUG("trst: %i, srst: %i", trst, srst);
vsllink.c:638vsllink_jtag_execute()
LOG_DEBUG_IO(
vsllink.c:641vsllink_jtag_execute()
if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO))
vsllink.c:705vsllink_swd_frequency()
LOG_DEBUG("SWD delay: %d, retry count: %d", delay, retry_count);
vsllink.c:717vsllink_swd_switch_seq()
LOG_DEBUG("SWD line reset");
vsllink.c:722vsllink_swd_switch_seq()
LOG_DEBUG("JTAG-to-SWD");
vsllink.c:727vsllink_swd_switch_seq()
LOG_DEBUG("SWD-to-JTAG");
vsllink.c:862vsllink_debug_buffer()
LOG_DEBUG_IO("%s", line);
w600.c:131w600_start_do()
LOG_DEBUG("WRITE CMD: 0x%08" PRIx32 "", cmd);
w600.c:137w600_start_do()
LOG_DEBUG("WRITE START: 0x%08" PRIx32 "", addr);
w600.c:142w600_start_do()
LOG_DEBUG("DELAY %dms", timeout);
w600.c:148w600_start_do()
LOG_DEBUG("READ START...");
w600.c:151w600_start_do()
LOG_DEBUG("READ START: 0x%08" PRIx32 "", status);
w600.c:153w600_start_do()
LOG_DEBUG("READ START FAILED");
x86_32_common.c:65x86_32_get_gdb_reg_list()
LOG_DEBUG("num_regs=%d, reg_class=%d", (*reg_list_size), reg_class);
x86_32_common.c:74x86_32_get_gdb_reg_list()
LOG_DEBUG("value %s = %08" PRIx32, x86_32->cache->reg_list[i].name,
x86_32_common.c:164read_phys_mem()
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:269write_phys_mem()
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:305write_phys_mem()
LOG_DEBUG("invalid read size");
x86_32_common.c:573x86_32_common_read_memory()
LOG_DEBUG("addr=" TARGET_ADDR_FMT ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:630x86_32_common_write_memory()
LOG_DEBUG("addr=" TARGET_ADDR_FMT ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:688x86_32_common_read_io()
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", buf=%p", addr, size, buf);
x86_32_common.c:766x86_32_common_write_io()
LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", buf=%p", addr, size, buf);
x86_32_common.c:861x86_32_common_add_breakpoint()
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:872x86_32_common_remove_breakpoint()
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:885set_debug_regs()
LOG_DEBUG("addr=0x%08" PRIx32 ", bp_num=%" PRIu8 ", bp_type=%" PRIu8 ", pb_length=%" PRIu8,
x86_32_common.c:945unset_debug_regs()
LOG_DEBUG("bp_num=%" PRIu8, bp_num);
x86_32_common.c:1020set_swbp()
LOG_DEBUG("id %" PRIx32, bp->unique_id);
x86_32_common.c:1030set_swbp()
LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8 "", *bp->orig_instr);
x86_32_common.c:1076unset_swbp()
LOG_DEBUG("id %" PRIx32, bp->unique_id);
x86_32_common.c:1125set_breakpoint()
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1155unset_breakpoint()
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1183set_watchpoint()
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, wp->rw, wp->address);
x86_32_common.c:1239unset_watchpoint()
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, wp->rw, wp->address);
x86_32_common.c:1247unset_watchpoint()
LOG_DEBUG("Invalid FP Comparator number in watchpoint");
x86_32_common.c:1310read_hw_reg_to_cache()
LOG_DEBUG("reg %s value 0x%08" PRIx32,
x86_32_common.c:1326write_hw_reg_from_cache()
LOG_DEBUG("reg %s value 0x%08" PRIx32, x86_32->cache->reg_list[num].name,
x86_32_common.c:1432target_fill_io()
LOG_DEBUG("address=0x%08" PRIx32 ", data_size=%u, b=0x%08" PRIx32,
xcf.c:470read_write_data()
LOG_DEBUG("written %d bytes from %d", dbg_written, dbg_count);
xds110.c:633xds_execute()
LOG_DEBUG("XDS110: command 0x%02x return %" PRIu32 " bytes, expected %" PRIu32,
xds110.c:640xds_execute()
LOG_DEBUG("XDS110: command 0x%02x returned error %d",
xds110.c:1101xds110_swd_switch_seq()
LOG_DEBUG("JTAG-to-SWD");
xds110.c:1118xds110_swd_switch_seq()
LOG_DEBUG("SWD-to-JTAG");
xds110.c:1333xds110_swd_queue_cmd()
LOG_DEBUG("XDS110: refusing to enable sticky overrun detection");
xilinx_bit.c:116xilinx_read_bit_file()
LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
xmc1xxx.c:93xmc1xxx_erase()
LOG_DEBUG("Infineon XMC1000 erase sectors %u to %u", first, last);
xmc1xxx.c:203xmc1xxx_erase_check()
LOG_DEBUG("Erase-checking 0x%08" PRIx32, start);
xmc1xxx.c:254xmc1xxx_write()
LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
xmc1xxx.c:307xmc1xxx_write()
LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
xmc1xxx.c:330xmc1xxx_write()
LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
xmc1xxx.c:394xmc1xxx_protect_check()
LOG_DEBUG("NVMCONF = %08" PRIx32, nvmconf);
xmc1xxx.c:421xmc1xxx_get_info_command()
LOG_DEBUG("ID[%d] = %08" PRIX32, i, chipid[i]);
xmc1xxx.c:428xmc1xxx_get_info_command()
LOG_DEBUG("ID[7] = %08" PRIX32, chipid[7]);
xmc1xxx.c:467xmc1xxx_probe()
LOG_DEBUG("IDCHIP = %08" PRIx32, idchip);
xmc4xxx.c:272xmc4xxx_load_bank_layout()
LOG_DEBUG("%u sectors", bank->num_sectors);
xmc4xxx.c:306xmc4xxx_load_bank_layout()
LOG_DEBUG("\t%d: %uk", i, capacity[i]);
xmc4xxx.c:348xmc4xxx_probe()
LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
xmc4xxx.c:365xmc4xxx_probe()
LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
xmc4xxx.c:369xmc4xxx_probe()
LOG_DEBUG("XMC4xxx: XMC4400 detected.");
xmc4xxx.c:373xmc4xxx_probe()
LOG_DEBUG("XMC4xxx: XMC4500 detected.");
xmc4xxx.c:377xmc4xxx_probe()
LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
xmc4xxx.c:556xmc4xxx_erase()
LOG_DEBUG("Erasing sector %u @ 0x%08"PRIx32, i, tmp_addr);
xmc4xxx.c:655xmc4xxx_write_page()
LOG_DEBUG("WLO: %08"PRIx32, w_lo);
xmc4xxx.c:656xmc4xxx_write_page()
LOG_DEBUG("WHI: %08"PRIx32, w_hi);
xmc4xxx.c:1082xmc4xxx_flash_protect()
LOG_DEBUG("Setting flash protection with procon:");
xmc4xxx.c:1083xmc4xxx_flash_protect()
LOG_DEBUG("PROCON: %"PRIx32, procon);
xscale.c:402xscale_read_tx()
if (debug_level >= 3) {
xscale.c:403xscale_read_tx()
LOG_DEBUG("waiting 100ms");
xscale.c:452xscale_write_rx()
LOG_DEBUG("polling RX");
xscale.c:473xscale_write_rx()
if (debug_level >= 3) {
xscale.c:474xscale_write_rx()
LOG_DEBUG("waiting 100ms");
xscale.c:642xscale_load_ic()
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
xscale.c:862xscale_debug_entry()
LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
xscale.c:868xscale_debug_entry()
LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
xscale.c:875xscale_debug_entry()
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
xscale.c:879xscale_debug_entry()
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
xscale.c:886xscale_debug_entry()
LOG_DEBUG("target entered debug state in %s mode",
xscale.c:1012xscale_halt()
LOG_DEBUG("target->state: %s",
xscale.c:1016xscale_halt()
LOG_DEBUG("target was already halted");
xscale.c:1023xscale_halt()
LOG_DEBUG("target->state == TARGET_RESET");
xscale.c:1118xscale_resume()
LOG_DEBUG("-");
xscale.c:1155xscale_resume()
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
xscale.c:1169xscale_resume()
LOG_DEBUG("enable single-step");
xscale.c:1183xscale_resume()
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
xscale.c:1190xscale_resume()
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
xscale.c:1197xscale_resume()
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
xscale.c:1210xscale_resume()
LOG_DEBUG("disable single-step");
xscale.c:1213xscale_resume()
LOG_DEBUG("set breakpoint at " TARGET_ADDR_FMT "",
xscale.c:1248xscale_resume()
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
xscale.c:1254xscale_resume()
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
xscale.c:1260xscale_resume()
LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
xscale.c:1275xscale_resume()
LOG_DEBUG("target resumed");
xscale.c:1304xscale_step_inner()
LOG_DEBUG("enable single-step");
xscale.c:1334xscale_step_inner()
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
xscale.c:1343xscale_step_inner()
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
xscale.c:1352xscale_step_inner()
LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
xscale.c:1365xscale_step_inner()
LOG_DEBUG("disable single-step");
xscale.c:1401xscale_step()
LOG_DEBUG("current pc %" PRIx32, current_pc);
xscale.c:1426xscale_step()
LOG_DEBUG("target stepped");
xscale.c:1443xscale_assert_reset()
LOG_DEBUG("target->state: %s",
xscale.c:1485xscale_deassert_reset()
LOG_DEBUG("-");
xscale.c:1632xscale_full_context()
LOG_DEBUG("-");
xscale.c:1778xscale_read_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
xscale.c:1877xscale_write_memory()
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
xscale.c:2529xscale_read_trace()
LOG_DEBUG("no trace data collected");
xsvf.c:297handle_xsvf_command()
LOG_DEBUG("XSTATE 0x%02X %s", uc,
xsvf.c:349handle_xsvf_command()
LOG_DEBUG("XCOMPLETE");
xsvf.c:359handle_xsvf_command()
LOG_DEBUG("XTDOMASK");
xsvf.c:375handle_xsvf_command()
LOG_DEBUG("XRUNTEST %d 0x%08X", xruntest, xruntest);
xsvf.c:387handle_xsvf_command()
LOG_DEBUG("XREPEAT %d", xrepeat);
xsvf.c:402handle_xsvf_command()
LOG_DEBUG("XSDRSIZE %d", xsdrsize);
xsvf.c:439handle_xsvf_command()
LOG_DEBUG("%s %d", op_name, xsdrsize);
xsvf.c:575handle_xsvf_command()
LOG_DEBUG("XSTATE 0x%02X %s", uc, tap_state_name(mystate));
xsvf.c:627handle_xsvf_command()
LOG_DEBUG("XENDIR 0x%02X %s", uc, tap_state_name(xendir));
xsvf.c:648handle_xsvf_command()
LOG_DEBUG("XENDDR %02X %s", uc, tap_state_name(xenddr));
xsvf.c:666handle_xsvf_command()
LOG_DEBUG("XSIR %d", bitcount);
xsvf.c:673handle_xsvf_command()
LOG_DEBUG("XSIR2 %d", bitcount);
xsvf.c:762handle_xsvf_command()
LOG_DEBUG("XWAIT %s %s usecs:%d", tap_state_name(
xsvf.c:810handle_xsvf_command()
LOG_DEBUG("XWAITSTATE %s %s clocks:%i usecs:%i",
xsvf.c:854handle_xsvf_command()
LOG_DEBUG("LCOUNT %d", loop_count);
xsvf.c:879handle_xsvf_command()
LOG_DEBUG("LDELAY %s clocks:%d usecs:%d", tap_state_name(
xsvf.c:893handle_xsvf_command()
LOG_DEBUG("LSDR");
xsvf.c:983handle_xsvf_command()
LOG_DEBUG("xsvf failed, setting taps to reasonable state");
xtensa.c:474xtensa_core_reg_set()
LOG_DEBUG("Scratch reg %s [0x%08" PRIx32 "] set from gdb", reg->name,
xtensa.c:476xtensa_core_reg_set()
LOG_DEBUG("scratch_ars mapping: a3/%s, a4/%s",
xtensa.c:580xtensa_region_ar_exec()
LOG_TARGET_DEBUG(target, "PPTLB(" TARGET_ADDR_FMT ") -> 0x%08" PRIx32 " exec_acc %d",
xtensa.c:617xtensa_window_state_save()
LOG_TARGET_DEBUG(target, "Clearing %s (0x%08" PRIx32 " -> 0x%08" PRIx32 ")",
xtensa.c:636xtensa_window_state_restore()
LOG_TARGET_DEBUG(target, "Restored %s (0x%08" PRIx32 ")",
xtensa.c:654xtensa_scratch_regs_fixup()
LOG_DEBUG("AR conflict: a%d -> ar%d", a_name, j - XT_REG_IDX_AR0);
xtensa.c:657xtensa_scratch_regs_fixup()
LOG_DEBUG("AR conflict: ar%d -> a%d", j - XT_REG_IDX_AR0, a_name);
xtensa.c:679xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(target, "start");
xtensa.c:696xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(target, "Writing back reg %s (%d) val %08" PRIX32,
xtensa.c:724xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(target, "Delaying MS write: 0x%x", ms);
xtensa.c:738xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(target, "Writing back reg cpenable (224) val %08" PRIX32, regval);
xtensa.c:804xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(target, "Writing back reg %s value %08" PRIX32 ", num =%i",
xtensa.c:830xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(
xtensa.c:866xtensa_write_dirty_registers()
LOG_TARGET_DEBUG(target, "Delayed MS (0x%x) write complete: 0x%x", ms_regno, ms);
xtensa.c:891xtensa_examine()
LOG_TARGET_DEBUG(target, "");
xtensa.c:909xtensa_examine()
LOG_DEBUG("OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id);
xtensa.c:936xtensa_smpbreak_write()
LOG_TARGET_DEBUG(xtensa->target, "write smpbreak set=0x%" PRIx32 " clear=0x%" PRIx32, set, clear);
xtensa.c:952xtensa_smpbreak_set()
LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state=%i", set, target->state);
xtensa.c:994xtensa_imprecise_exception_occurred()
LOG_TARGET_DEBUG(target, "Imprecise exception: %s: 0x%x",
xtensa.c:1011xtensa_imprecise_exception_clear()
LOG_TARGET_DEBUG(target, "Imprecise exception: clearing %s (0x%x)",
xtensa.c:1024xtensa_core_status_check()
LOG_TARGET_DEBUG(target, "DSR (%08" PRIX32 ")", dsr);
xtensa.c:1165xtensa_assert_reset()
LOG_TARGET_DEBUG(target, " begin");
xtensa.c:1186xtensa_deassert_reset()
LOG_TARGET_DEBUG(target, "halt=%d", target->reset_halt);
xtensa.c:1206xtensa_soft_reset_halt()
LOG_TARGET_DEBUG(target, "begin");
xtensa.c:1220xtensa_fetch_all_regs()
bool debug_dsrs = !xtensa->regs_fetched || LOG_LEVEL_IS(LOG_LVL_DEBUG);
xtensa.c:1234xtensa_fetch_all_regs()
LOG_TARGET_DEBUG(target, "start");
xtensa.c:1252xtensa_fetch_all_regs()
LOG_TARGET_DEBUG(target, "Overriding MS (0x%x): 0x%x", ms_regno, XT_MS_DISPST_DBG);
xtensa.c:1318xtensa_fetch_all_regs()
LOG_TARGET_DEBUG(target, "CPENABLE: was 0x%" PRIx32 ", all enabled", cpenable);
xtensa.c:1426xtensa_fetch_all_regs()
LOG_DEBUG("%s = 0x%x", rlist[ridx].name, regval);
xtensa.c:1439xtensa_fetch_all_regs()
LOG_TARGET_DEBUG(target, "Caching MS: 0x%x", ms);
xtensa.c:1508xtensa_get_gdb_reg_list()
LOG_DEBUG("reg_class=%i, num_regs=%d", (int)reg_class, num_regs);
xtensa.c:1537xtensa_get_gdb_reg_list()
LOG_DEBUG("SPARSE GDB reg 0x%x getting EPS%d 0x%x",
xtensa.c:1570xtensa_halt()
LOG_TARGET_DEBUG(target, "start");
xtensa.c:1572xtensa_halt()
LOG_TARGET_DEBUG(target, "target was already halted");
xtensa.c:1581xtensa_halt()
LOG_TARGET_DEBUG(target, "Core status 0x%" PRIx32, xtensa_dm_core_status_get(&xtensa->dbg_mod));
xtensa.c:1602xtensa_prepare_resume()
LOG_TARGET_DEBUG(target,
xtensa.c:1619xtensa_prepare_resume()
LOG_TARGET_DEBUG(target, "DEBUGCAUSE 0x%x (watchpoint %lu) (break %lu)",
xtensa.c:1660xtensa_do_resume()
LOG_TARGET_DEBUG(target, "start");
xtensa.c:1679xtensa_resume()
LOG_TARGET_DEBUG(target, "start");
xtensa.c:1732xtensa_do_step()
LOG_TARGET_DEBUG(target, "current=%d, address=" TARGET_ADDR_FMT ", handle_breakpoints=%i",
xtensa.c:1751xtensa_do_step()
LOG_TARGET_DEBUG(target, "oldps=%" PRIx32 ", oldpc=%" PRIx32 " dbg_cause=%" PRIx32 " exc_cause=%" PRIx32,
xtensa.c:1758xtensa_do_step()
LOG_TARGET_DEBUG(target, "Increment PC to pass break instruction...");
xtensa.c:1802xtensa_do_step()
LOG_TARGET_DEBUG(
xtensa.c:1821xtensa_do_step()
LOG_TARGET_DEBUG(target,
xtensa.c:1864xtensa_do_step()
LOG_TARGET_DEBUG(target, "Finish stepping. dsr=0x%08" PRIx32,
xtensa.c:1879xtensa_do_step()
LOG_TARGET_DEBUG(target,
xtensa.c:1893xtensa_do_step()
LOG_DEBUG("Stepping out of window exception, PC=%" PRIX32, cur_pc);
xtensa.c:1903xtensa_do_step()
LOG_DEBUG("Stepped from %" PRIX32 " to %" PRIX32, oldpc, cur_pc);
xtensa.c:1909xtensa_do_step()
LOG_DEBUG("Done stepping, PC=%" PRIX32, cur_pc);
xtensa.c:1912xtensa_do_step()
LOG_TARGET_DEBUG(target, "...Done, re-installing watchpoints.");
xtensa.c:1920xtensa_do_step()
LOG_DEBUG("Restoring %s after stepping: 0x%08" PRIx32,
xtensa.c:2017xtensa_read_memory()
LOG_DEBUG("address " TARGET_ADDR_FMT " not readable", address);
xtensa.c:2064xtensa_read_memory()
LOG_TARGET_DEBUG(target, "Disabling LDDR32.P/SDDR32.P");
xtensa.c:2247xtensa_write_memory()
LOG_TARGET_DEBUG(target, "Cache OPs: IHI %d, DHWBI %d", issue_ihi, issue_dhwbi);
xtensa.c:2315xtensa_poll()
LOG_TARGET_DEBUG(target, "PWRSTAT: read 0x%08" PRIx32 ", clear 0x%08lx, reread 0x%08" PRIx32,
xtensa.c:2341xtensa_poll()
LOG_TARGET_DEBUG(target,
xtensa.c:2349xtensa_poll()
LOG_TARGET_DEBUG(target, "not powered 0x%" PRIX32 "%ld",
xtensa.c:2380xtensa_poll()
LOG_TARGET_DEBUG(target, "Target halted, pc=0x%08" PRIx32
xtensa.c:2385xtensa_poll()
LOG_TARGET_DEBUG(target, "Halt reason=0x%08" PRIX32 ", exc_cause=%" PRId32 ", dsr=0x%08" PRIx32,
xtensa.c:2399xtensa_poll()
LOG_TARGET_DEBUG(target, "Enabling PS.DIEXC: 0x%08x -> 0x%08x", ps, newps);
xtensa.c:2460xtensa_update_instruction()
LOG_TARGET_DEBUG(target, "IHI %d, DHWBI %d for address " TARGET_ADDR_FMT,
xtensa.c:2465xtensa_update_instruction()
LOG_TARGET_DEBUG(target,
xtensa.c:2474xtensa_update_instruction()
LOG_TARGET_DEBUG(target,
xtensa.c:2502xtensa_update_instruction()
LOG_DEBUG("DHWB dcache line for address "TARGET_ADDR_FMT, address);
xtensa.c:2504xtensa_update_instruction()
LOG_TARGET_DEBUG(target, "DHWB second dcache line for address "TARGET_ADDR_FMT, address + 4);
xtensa.c:2574xtensa_breakpoint_add()
LOG_TARGET_DEBUG(target, "placed SW breakpoint %u @ " TARGET_ADDR_FMT,
xtensa.c:2591xtensa_breakpoint_add()
LOG_TARGET_DEBUG(target, "placed HW breakpoint %u @ " TARGET_ADDR_FMT,
xtensa.c:2617xtensa_breakpoint_remove()
LOG_TARGET_DEBUG(target, "cleared SW breakpoint %u @ " TARGET_ADDR_FMT, slot, breakpoint->address);
xtensa.c:2632xtensa_breakpoint_remove()
LOG_TARGET_DEBUG(target, "cleared HW breakpoint %u @ " TARGET_ADDR_FMT, slot, breakpoint->address);
xtensa.c:2687xtensa_watchpoint_add()
LOG_TARGET_DEBUG(target, "placed HW watchpoint @ " TARGET_ADDR_FMT,
xtensa.c:2707xtensa_watchpoint_remove()
LOG_TARGET_DEBUG(target, "cleared HW watchpoint @ " TARGET_ADDR_FMT,
xtensa.c:2789xtensa_start_algorithm()
LOG_DEBUG("setting core_mode: 0x%x", algorithm_info->core_mode);
xtensa.c:2853xtensa_wait_algorithm()
LOG_DEBUG("Read mem params");
xtensa.c:2855xtensa_wait_algorithm()
LOG_DEBUG("Check mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
xtensa.c:2857xtensa_wait_algorithm()
LOG_DEBUG("Read mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
xtensa.c:2874xtensa_wait_algorithm()
LOG_DEBUG("Skip restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32,
xtensa.c:2883xtensa_wait_algorithm()
LOG_DEBUG("restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32,
xtensa.c:2888xtensa_wait_algorithm()
LOG_DEBUG("restoring register %s: 0x%8.8" PRIx64 " -> 0x%8.8" PRIx64,
xtensa.c:2893xtensa_wait_algorithm()
LOG_DEBUG("restoring register %s %u-bits", xtensa->core_cache->reg_list[i].name, reg->size);
xtensa.c:2981xtensa_build_reg_cache()
LOG_TARGET_DEBUG(target,
xtensa.c:2997xtensa_build_reg_cache()
LOG_TARGET_DEBUG(target, "xtensa->total_regs_num %d reg_list_size %d xtensa->dbregs_num %d",
xtensa.c:3041xtensa_build_reg_cache()
LOG_TARGET_DEBUG(target,
xtensa.c:3119xtensa_gdbqc_parse_exec_tie_ops()
LOG_TARGET_DEBUG(target, "%s", insn_buf);
xtensa.c:3157xtensa_gdbqc_qxtreg()
LOG_DEBUG("TIE reg 0x%08" PRIx32 " %s (%d bytes)", regnum, iswrite ? "write" : "read", reglen);
xtensa.c:3240xtensa_gdbqc_qxtreg()
LOG_TARGET_DEBUG(target, "TIE response: %s", *response_p);
xtensa.c:3304xtensa_gdb_query_custom()
LOG_TARGET_DEBUG(target, "memcheck: %dB @ 0x%08x", size, base);
xtensa.c:3352xtensa_gdb_query_custom()
LOG_TARGET_DEBUG(target, "Set spill 0x%08" PRIx32 " (%d)", xtensa->spill_loc, xtensa->spill_bytes);
xtensa.c:3489xtensa_target_deinit()
LOG_DEBUG("start");
xtensa.c:3570xtensa_cmd_exe_do()
LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]);
xtensa.c:3980xtensa_cmd_xtreg_do()
LOG_DEBUG("Setting PS (%s) index to %d", rptr->name, xtensa->eps_dbglevel_idx);
xtensa.c:4005xtensa_cmd_xtreg_do()
LOG_DEBUG("NX reg %s: index %d (%d)",
xtensa.c:4020xtensa_cmd_xtreg_do()
LOG_DEBUG("Added %s register %-16s: 0x%04x/0x%02x t%d (%d of %d)",
xtensa_chip.c:103xtensa_chip_target_create()
LOG_DEBUG("DAP: ap_num %" PRId64 " DAP %p\n", pc->ap_num, pc->dap);
xtensa_chip.c:106xtensa_chip_target_create()
LOG_DEBUG("JTAG: %s:%s pos %u", target->tap->chip, target->tap->tapname,
xtensa_debug_module.c:120xtensa_dm_examine()
LOG_DEBUG("DM examine: DAP AP select %d", dm->debug_apsel);
xtensa_debug_module.c:126xtensa_dm_examine()
LOG_DEBUG("DM examine: search for APB-type MEM-AP...");
xtensa_debug_module.c:139xtensa_dm_examine()
LOG_DEBUG("DM examine: Setting apsel to %d", dm->debug_apsel);
xtensa_fileio.c:64xtensa_fileio_detect_proc()
LOG_TARGET_DEBUG(target, "File-I/O: syscall breakpoint found at 0x%x", pc);
xtensa_fileio.c:88xtensa_get_gdb_fileio_info()
LOG_TARGET_DEBUG(target, "File-I/O: syscall 0x%x 0x%x 0x%x 0x%x 0x%x",
xtensa_fileio.c:160xtensa_get_gdb_fileio_info()
LOG_TARGET_DEBUG(target, "File-I/O: syscall unknown (%d), pc=0x%08X",
xtensa_fileio.c:177xtensa_gdb_fileio_end()
LOG_TARGET_DEBUG(target, "File-I/O: syscall return code: 0x%x, errno: 0x%x , ctrl_c: %s",
zephyr.c:434zephyr_create()
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, ARC_AUX_SEC_BUILD_REG, &value));
zephyr.c:436zephyr_create()
LOG_DEBUG("ARC EM board has security subsystem, changing offsets");
zephyr.c:560zephyr_fetch_thread()
LOG_DEBUG("Fetched thread%" PRIx32 ": {entry@0x%" PRIx32
zephyr.c:611zephyr_fetch_thread_list()
LOG_DEBUG("Got information for %zu threads", thread_array.elements);
zephyr.c:726zephyr_update_threads()
LOG_DEBUG("Zephyr OpenOCD support version %" PRId32,

Data Use

Functions writing debug_level
Functions reading debug_level
all items filtered out
debug_level
all items filtered out