target::coreid is only used within OpenOCD.
 
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target::coreid field

Syntax

int32_t coreid;

References

LocationReferrerText
target.h:120
int32_t coreid; /* which device on the TAP? */
aarch64.c:2662aarch64_examine_first()
&armv8->debug_base, target->coreid);
aarch64.c:2666aarch64_examine_first()
target->coreid, armv8->debug_base);
cortex_a.c:669get_cortex_a()
if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
cortex_a.c:699update_halt_gdb()
target->gdb_service->core[0] = target->coreid;
cortex_a.c:2932cortex_a_examine_first()
&armv7a->debug_base, target->coreid);
cortex_a.c:2939cortex_a_examine_first()
target->coreid, armv7a->debug_base);
cortex_a.c:3349handle_cortex_a_freeze_core_command()
if (pThisTarget->coreid == coreid)
esp_xtensa_smp.c:141get_halted_esp_xtensa_smp()
if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
esp_xtensa_smp.c:263esp_xtensa_smp_update_halt_gdb()
target->gdb_service->core[0] = target->coreid;
esp_xtensa_smp.c:890esp_xtensa_smp_cmd_tracedump()
if (cores_max_id < curr->coreid)
esp_xtensa_smp.c:891esp_xtensa_smp_cmd_tracedump()
cores_max_id = curr->coreid;
esp_xtensa_smp.c:902esp_xtensa_smp_cmd_tracedump()
target_to_xtensa(curr), CMD_ARGV[curr->coreid]);
linux.c:186linux_os_thread_reg_list()
if (head->target->coreid == next->core_id) {
linux.c:432get_current()
cpu = head->target->coreid;
linux.c:1219linux_gdb_h_packet()
while ((ct) && (ct->core_id != target->coreid))
linux.c:1344linux_thread_packet()
while ((ct) && (ct->core_id) != target->coreid)
linux.c:1395linux_os_smp_init()
ct->core_id = head->target->coreid;
linux.c:1422linux_os_create()
ct->core_id = target->coreid;
mips_m4k.c:127get_mips_m4k()
if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
mips_m4k.c:157update_halt_gdb()
target->gdb_service->core[0] = target->coreid;
riscv-013.c:251get_dm()
LOG_DEBUG("[%d] Allocating new DM", target->coreid);
riscv-013.c:1585examine()
info->index = target->coreid;
riscv-013.c:1705examine()
r->current_hartid = target->coreid;
riscv-013.c:1765examine()
LOG_INFO("Core %d made part of halt group %d.", target->coreid,
riscv-013.c:1769examine()
target->coreid, target->smp);
riscv-013.c:2357assert_reset()
uint32_t control = set_hartsel(control_base, target->coreid);
riscv-013.c:2409deassert_reset()
if (index != target->coreid)
riscv-013.c:4080riscv013_get_register()
LOG_DEBUG("[%d] read PC from DPC: 0x%" PRIx64, target->coreid, *value);
riscv-013.c:4100riscv013_set_register()
target->coreid, value, gdb_regno_name(rid));
riscv-013.c:4105riscv013_set_register()
LOG_DEBUG("[%d] writing PC to DPC: 0x%" PRIx64, target->coreid, value);
riscv-013.c:4109riscv013_set_register()
LOG_DEBUG("[%d] actual DPC written: 0x%016" PRIx64, target->coreid, actual_value);
riscv-013.c:4175select_prepped_harts()
LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped);
riscv-013.c:4333riscv013_halt_reason()
LOG_DEBUG("{%d} halted because of trigger", target->coreid);
riscv.c:731add_trigger()
LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
riscv.c:867riscv_add_breakpoint()
riscv.c:930remove_trigger()
LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
riscv.c:1004riscv_remove_watchpoint()
riscv.c:1163riscv_select_current_hart()
riscv.c:1235riscv_halt()
LOG_DEBUG("[%d] halting all harts", target->coreid);
riscv.c:1275riscv_assert_reset()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:1283riscv_deassert_reset()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:1402resume_prep()
LOG_DEBUG("[%d]", target->coreid);
riscv.c:1427resume_prep()
LOG_DEBUG("[%d] mark as prepped", target->coreid);
riscv.c:3130riscv_info_init()
r->current_hartid = target->coreid;
riscv.c:3231riscv_invalidate_register_cache()
LOG_DEBUG("[%d]", target->coreid);
target.c:5239target_configure()
target->coreid = (int32_t)w;
target.c:5244target_configure()
target.c:5896target_create()
target->coreid = 0;