OpenOCD
target::coreid
is only used within OpenOCD.
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target::coreid
target::coreid field
Syntax
from
target.h:120
int32_t
coreid
;
References
Location
Referrer
Text
target.h:120
int32_t
coreid
;
/* which device on the TAP? */
aarch64.c:2662
aarch64_examine_first()
&
armv8
->
debug_base
,
target
->
coreid
)
;
aarch64.c:2666
aarch64_examine_first()
target
->
coreid
,
armv8
->
debug_base
)
;
cortex_a.c:669
get_cortex_a()
if
(
(
curr
->
coreid
==
coreid
)
&&
(
curr
->
state
==
TARGET_HALTED
)
)
cortex_a.c:699
update_halt_gdb()
target
->
gdb_service
->
core
[
0
]
=
target
->
coreid
;
cortex_a.c:2932
cortex_a_examine_first()
&
armv7a
->
debug_base
,
target
->
coreid
)
;
cortex_a.c:2939
cortex_a_examine_first()
target
->
coreid
,
armv7a
->
debug_base
)
;
cortex_a.c:3349
handle_cortex_a_freeze_core_command()
if
(
pThisTarget
->
coreid
==
coreid
)
esp_xtensa_smp.c:141
get_halted_esp_xtensa_smp()
if
(
(
curr
->
coreid
==
coreid
)
&&
(
curr
->
state
==
TARGET_HALTED
)
)
esp_xtensa_smp.c:263
esp_xtensa_smp_update_halt_gdb()
target
->
gdb_service
->
core
[
0
]
=
target
->
coreid
;
esp_xtensa_smp.c:890
esp_xtensa_smp_cmd_tracedump()
if
(
cores_max_id
<
curr
->
coreid
)
esp_xtensa_smp.c:891
esp_xtensa_smp_cmd_tracedump()
cores_max_id
=
curr
->
coreid
;
esp_xtensa_smp.c:902
esp_xtensa_smp_cmd_tracedump()
target_to_xtensa
(
curr
)
,
CMD_ARGV
[
curr
->
coreid
]
)
;
linux.c:186
linux_os_thread_reg_list()
if
(
head
->
target
->
coreid
==
next
->
core_id
)
{
linux.c:432
get_current()
cpu
=
head
->
target
->
coreid
;
linux.c:1219
linux_gdb_h_packet()
while
(
(
ct
)
&&
(
ct
->
core_id
!=
target
->
coreid
)
)
linux.c:1344
linux_thread_packet()
while
(
(
ct
)
&&
(
ct
->
core_id
)
!=
target
->
coreid
)
linux.c:1395
linux_os_smp_init()
ct
->
core_id
=
head
->
target
->
coreid
;
linux.c:1422
linux_os_create()
ct
->
core_id
=
target
->
coreid
;
mips_m4k.c:127
get_mips_m4k()
if
(
(
curr
->
coreid
==
coreid
)
&&
(
curr
->
state
==
TARGET_HALTED
)
)
mips_m4k.c:157
update_halt_gdb()
target
->
gdb_service
->
core
[
0
]
=
target
->
coreid
;
riscv-013.c:251
get_dm()
LOG_DEBUG
(
"[%d] Allocating new DM"
,
target
->
coreid
)
;
riscv-013.c:1585
examine()
info
->
index
=
target
->
coreid
;
riscv-013.c:1705
examine()
r
->
current_hartid
=
target
->
coreid
;
riscv-013.c:1765
examine()
LOG_INFO
(
"Core %d made part of halt group %d."
,
target
->
coreid
,
riscv-013.c:1769
examine()
target
->
coreid
,
target
->
smp
)
;
riscv-013.c:2357
assert_reset()
uint32_t
control
=
set_hartsel
(
control_base
,
target
->
coreid
)
;
riscv-013.c:2409
deassert_reset()
if
(
index
!=
target
->
coreid
)
riscv-013.c:4080
riscv013_get_register()
LOG_DEBUG
(
"[%d] read PC from DPC: 0x%"
PRIx64
,
target
->
coreid
,
*
value
)
;
riscv-013.c:4100
riscv013_set_register()
target
->
coreid
,
value
,
gdb_regno_name
(
rid
)
)
;
riscv-013.c:4105
riscv013_set_register()
LOG_DEBUG
(
"[%d] writing PC to DPC: 0x%"
PRIx64
,
target
->
coreid
,
value
)
;
riscv-013.c:4109
riscv013_set_register()
LOG_DEBUG
(
"[%d] actual DPC written: 0x%016"
PRIx64
,
target
->
coreid
,
actual_value
)
;
riscv-013.c:4175
select_prepped_harts()
LOG_DEBUG
(
"index=%d, coreid=%d, prepped=%d"
,
index
,
t
->
coreid
,
r
->
prepped
)
;
riscv-013.c:4333
riscv013_halt_reason()
LOG_DEBUG
(
"{%d} halted because of trigger"
,
target
->
coreid
)
;
riscv.c:731
add_trigger()
LOG_DEBUG
(
"[%d] Using trigger %d (type %d) for bp %d"
,
target
->
coreid
,
riscv.c:867
riscv_add_breakpoint()
LOG_DEBUG
(
"[%d] @0x%"
TARGET_PRIxADDR
,
target
->
coreid
,
breakpoint
->
address
)
;
riscv.c:930
remove_trigger()
LOG_DEBUG
(
"[%d] Stop using resource %d for bp %d"
,
target
->
coreid
,
i
,
riscv.c:1004
riscv_remove_watchpoint()
LOG_DEBUG
(
"[%d] @0x%"
TARGET_PRIxADDR
,
target
->
coreid
,
watchpoint
->
address
)
;
riscv.c:1163
riscv_select_current_hart()
return
riscv_set_current_hartid
(
target
,
target
->
coreid
)
;
riscv.c:1235
riscv_halt()
LOG_DEBUG
(
"[%d] halting all harts"
,
target
->
coreid
)
;
riscv.c:1275
riscv_assert_reset()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:1283
riscv_deassert_reset()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:1402
resume_prep()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
riscv.c:1427
resume_prep()
LOG_DEBUG
(
"[%d] mark as prepped"
,
target
->
coreid
)
;
riscv.c:3130
riscv_info_init()
r
->
current_hartid
=
target
->
coreid
;
riscv.c:3231
riscv_invalidate_register_cache()
LOG_DEBUG
(
"[%d]"
,
target
->
coreid
)
;
target.c:5239
target_configure()
target
->
coreid
=
(
int32_t
)
w
;
target.c:5244
target_configure()
Jim_SetResult
(
goi
->
interp
,
Jim_NewIntObj
(
goi
->
interp
,
target
->
coreid
)
)
;
target.c:5896
target_create()
target
->
coreid
=
0
;
Data Use
Functions writing
target::coreid
Functions reading
target::coreid
target_configure()
target_create()
all items filtered out
target::coreid
linux_os_thread_reg_list()
get_current()
linux_gdb_h_packet()
linux_thread_packet()
linux_os_smp_init()
linux_os_create()
get_cortex_a()
update_halt_gdb()
cortex_a_examine_first()
handle_cortex_a_freeze_core_command()
get_mips_m4k()
update_halt_gdb()
target_configure()
aarch64_examine_first()
add_trigger()
riscv_add_breakpoint()
remove_trigger()
riscv_remove_watchpoint()
riscv_select_current_hart()
riscv_halt()
riscv_assert_reset()
riscv_deassert_reset()
resume_prep()
riscv_info_init()
riscv_invalidate_register_cache()
get_dm()
examine()
assert_reset()
deassert_reset()
riscv013_get_register()
riscv013_set_register()
select_prepped_harts()
riscv013_halt_reason()
get_halted_esp_xtensa_smp()
esp_xtensa_smp_update_halt_gdb()
esp_xtensa_smp_cmd_tracedump()
all items filtered out
Type of
target::coreid
target::coreid
int32_t
all items filtered out