LOG_DEBUG - syntax, references, description

References

Location	Text
log.h:109	#define LOG_DEBUG(expr ...) \
FLASHPlugin.c:157	LOG_DEBUG("FLASH plugin: placing the stack at 0x%08x-0x%08x", lastSectionEnd, lastSectionEnd + stackSize);
FreeRTOS.c:158	LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %" PRIu32,
FreeRTOS.c:180	LOG_DEBUG("FreeRTOS: Read pxCurrentTCB at 0x%" PRIx64 ", value 0x%" PRIx64,
FreeRTOS.c:193	LOG_DEBUG("FreeRTOS: Read xSchedulerRunning at 0x%" PRIx64 ", value 0x%" PRIx32,
FreeRTOS.c:242	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu32,
FreeRTOS.c:290	LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRIu32,
FreeRTOS.c:307	LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx32,
FreeRTOS.c:323	LOG_DEBUG("FreeRTOS: Read Thread ID at 0x%" PRIx32 ", value 0x%" PRIx64,
FreeRTOS.c:343	LOG_DEBUG("FreeRTOS: Read Thread Name at 0x%" PRIx64 ", value '%s'",
FreeRTOS.c:378	LOG_DEBUG("FreeRTOS: Read next thread location at 0x%" PRIx32 ", value 0x%" PRIx32,
FreeRTOS.c:416	LOG_DEBUG("FreeRTOS: Read stack pointer at 0x%" PRIx64 ", value 0x%" PRIx64,
ThreadX.c:244	LOG_DEBUG(" solicited stack");
ThreadX.c:247	LOG_DEBUG(" interrupt stack: %" PRIu32, flag);
aarch64.c:184	LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
aarch64.c:212	LOG_DEBUG("%s", target_name(target));
aarch64.c:217	LOG_DEBUG("Examine %s failed", "oslock");
aarch64.c:324	LOG_DEBUG("target %s timeout, prsr=0x%08"PRIx32, target_name(target), prsr);
aarch64.c:337	LOG_DEBUG("target %s exc %i", target_name(target), exc_target);
aarch64.c:360	LOG_DEBUG("target %s prepared", target_name(curr));
aarch64.c:381	LOG_DEBUG("%s", target_name(target));
aarch64.c:480	LOG_DEBUG("Halting remaining targets in SMP group");
aarch64.c:537	LOG_DEBUG("Target %s halted", target_name(target));
aarch64.c:586	LOG_DEBUG("%s", target_name(target));
aarch64.c:619	LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
aarch64.c:645	LOG_DEBUG("%s", target_name(target));
aarch64.c:690	LOG_DEBUG("%s", target_name(target));
aarch64.c:731	LOG_DEBUG("%s", target_name(target));
aarch64.c:787	LOG_DEBUG("%s", target_name(target));
aarch64.c:796	LOG_DEBUG("error restarting target %s", target_name(first));
aarch64.c:949	LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
aarch64.c:953	LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
aarch64.c:979	LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), dscr);
aarch64.c:1080	LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
aarch64.c:1150	LOG_DEBUG("Restarted all non-stepping targets in SMP group");
aarch64.c:1161	LOG_DEBUG("target step-resumed at 0x%" PRIx64, address);
aarch64.c:1223	LOG_DEBUG("%s", target_name(target));
aarch64.c:1295	LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
aarch64.c:1357	LOG_DEBUG("Failed to set DSCR.HDE");
aarch64.c:1407	LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
aarch64.c:1437	LOG_DEBUG("brp(CTX) found num: %d", brp_1);
aarch64.c:1447	LOG_DEBUG("brp(IVA) found num: %d", brp_2);
aarch64.c:1518	LOG_DEBUG("Invalid BRP number in breakpoint");
aarch64.c:1521	LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
aarch64.c:1542	LOG_DEBUG("Invalid BRP number in breakpoint");
aarch64.c:1545	LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_j,
aarch64.c:1573	LOG_DEBUG("Invalid BRP number in breakpoint");
aarch64.c:1576	LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_i,
aarch64.c:1771	LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, wp_i,
aarch64.c:1777	LOG_DEBUG("Failed to set DSCR.HDE");
aarch64.c:1803	LOG_DEBUG("Invalid WP number in watchpoint");
aarch64.c:1806	LOG_DEBUG("rwp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, wp_i,
aarch64.c:1904	LOG_DEBUG("EDECR = 0x%08" PRIx32 ", enable=%d", edecr, enable);
aarch64.c:1931	LOG_DEBUG("Reset Catch debug event %s",
aarch64.c:1952	LOG_DEBUG(" ");
aarch64.c:2012	LOG_DEBUG(" ");
aarch64.c:2418	LOG_DEBUG("Reading CPU memory address 0x%016" PRIx64 " size %" PRIu32 " count %" PRIu32,
aarch64.c:2665	LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
aarch64.c:2673	LOG_DEBUG("Examine %s failed", "oslock");
aarch64.c:2680	LOG_DEBUG("Examine %s failed", "CPUID");
aarch64.c:2689	LOG_DEBUG("Examine %s failed", "Memory Model Type");
aarch64.c:2697	LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
aarch64.c:2712	LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
aarch64.c:2713	LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
aarch64.c:2714	LOG_DEBUG("debug = 0x%08" PRIx64, debug);
aarch64.c:2755	LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
adapter.c:214	LOG_DEBUG("convert khz to adapter specific speed value");
adapter.c:218	LOG_DEBUG("have adapter set up");
adapter.c:235	LOG_DEBUG("trying fallback speed...");
adapter.c:250	LOG_DEBUG("handle adapter khz");
adapter.c:259	LOG_DEBUG("handle adapter rclk");
adapter.c:948	LOG_DEBUG("Processing %s", CMD_ARGV[i]);
adapter.c:961	LOG_DEBUG("-chip arg is %s", CMD_ARGV[i + 1]);
adi_v5_dapdirect.c:33	LOG_DEBUG("dapdirect_jtag_empty_command(\"%s\")", CMD_NAME);
adi_v5_dapdirect.c:180	LOG_DEBUG("dapdirect_jtag_select()");
adi_v5_dapdirect.c:187	LOG_DEBUG("dapdirect_swd_select()");
adi_v5_dapdirect.c:196	LOG_DEBUG("dapdirect_init()");
adi_v5_jtag.c:617	LOG_DEBUG("DAP transaction stalled during replay (WAIT) - resending");
adi_v5_jtag.c:671	LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
adi_v5_jtag.c:684	LOG_DEBUG("JTAG-DP STICKY OVERRUN");
adi_v5_swd.c:287	LOG_DEBUG("Failed to select multidrop %s, retrying...",
adi_v5_swd.c:741	LOG_DEBUG("no SWD driver?");
adi_v5_swd.c:747	LOG_DEBUG("can't init SWD driver");
aduc702x.c:78	LOG_DEBUG("performing mass erase.");
aduc702x.c:89	LOG_DEBUG("mass erase successful.");
aduc702x.c:107	LOG_DEBUG("erased sector at address 0x%08lX", adr);
aduc702x.c:297	LOG_DEBUG("wrote %d bytes at address 0x%08lX", (int)count, (unsigned long)(offset + x));
aducm302x.c:137	LOG_DEBUG("bank=%p", bank);
aducm302x.c:240	LOG_DEBUG("bank=%p first=%d last = %d", bank, first, last);
aducm302x.c:304	LOG_DEBUG("WRPROT 0x%"PRIx32, wrprot);
aducm302x.c:355	LOG_DEBUG("bank=%p buffer=%p offset=%08"PRIx32" dwcount=%"PRIx32,
aducm302x.c:365	LOG_DEBUG("no working area for block memory writes");
aducm302x.c:384	LOG_DEBUG("retry target_alloc_working_area(%s, size=%"PRIu32")",
aducm302x.c:443	LOG_DEBUG("bank=%p buffer=%p offset=%08"PRIx32" count=%"PRIx32,
aducm302x.c:476	LOG_DEBUG("writing flash word-at-a-time");
aducm360.c:207	LOG_DEBUG("'aducm360_write_block_sync' requested, dst:0x%08" PRIx32 ", count:0x%08" PRIx32 "bytes.",
aducm360.c:329	LOG_DEBUG("'aducm360_write_block_async' requested, dst:0x%08" PRIx32 ", count:0x%08" PRIx32 "bytes.",
aducm360.c:447	LOG_DEBUG("performing slow write (offset=0x%08" PRIx32 ", count=0x%08" PRIx32 ")...",
ambiqmicro.c:185	LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
ambiqmicro.c:233	LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro.c:271	LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
ambiqmicro.c:312	LOG_DEBUG("state = %d", target->state);
ambiqmicro.c:588	LOG_DEBUG("address = 0x%08" PRIx32, address);
arc.c:64	LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
arc.c:107	LOG_DEBUG("Resetting internal variables of caches states");
arc.c:208	LOG_DEBUG(
arc.c:230	LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
arc.c:258	LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
arc.c:284	LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
arc.c:378	LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
arc.c:393	LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
arc.c:472	LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
arc.c:524	LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
arc.c:542	LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
arc.c:554	LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
arc.c:600	LOG_DEBUG("reg_name=%s", reg_name);
arc.c:618	LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
arc.c:658	LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc.c:690	LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc.c:710	LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc.c:719	LOG_DEBUG("Configuring ARC ICCM and DCCM");
arc.c:773	LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
arc.c:775	LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
arc.c:786	LOG_DEBUG("target->state: %s", target_state_name(target));
arc.c:789	LOG_DEBUG("target was already halted");
arc.c:828	LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
arc.c:830	LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
arc.c:849	LOG_DEBUG("Saving aux and core registers values");
arc.c:919	LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
arc.c:934	LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
arc.c:1060	LOG_DEBUG("ARC core in halt or reset state.");
arc.c:1067	LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
arc.c:1074	LOG_DEBUG("ARC core is in debug running mode");
arc.c:1090	LOG_DEBUG("target->state: %s", target_state_name(target));
arc.c:1104	LOG_DEBUG("Starting CPU execution after reset");
arc.c:1141	LOG_DEBUG("target->state: %s", target_state_name(target));
arc.c:1158	LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32,
arc.c:1177	LOG_DEBUG("Restoring registers values");
arc.c:1204	LOG_DEBUG("Will write regnum=%u", i);
arc.c:1215	LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
arc.c:1263	LOG_DEBUG("interrupts enabled");
arc.c:1268	LOG_DEBUG("interrupts disabled");
arc.c:1282	LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
arc.c:1307	LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
arc.c:1317	LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
arc.c:1323	LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
arc.c:1332	LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
arc.c:1353	LOG_DEBUG("Core started to run");
arc.c:1361	LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
arc.c:1365	LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
arc.c:1389	LOG_DEBUG("deinitialization of target");
arc.c:1438	LOG_DEBUG("Entering");
arc.c:1459	LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
arc.c:1495	LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
arc.c:1555	LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
arc.c:1617	LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
arc.c:1622	LOG_DEBUG("ERROR: setting unknown breakpoint type");
arc.c:1641	LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
arc.c:1687	LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
arc.c:1700	LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
arc.c:1704	LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
arc.c:1778	LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
arc.c:1920	LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
arc.c:1941	LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
arc.c:1954	LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
arc.c:2023	LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
arc.c:2048	LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
arc.c:2057	LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
arc.c:2065	LOG_DEBUG("core debug step mode disabled");
arc.c:2107	LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
arc.c:2139	LOG_DEBUG("target stepped ");
arc.c:2162	LOG_DEBUG("Invalidating I$.");
arc.c:2182	LOG_DEBUG("Invalidating D$.");
arc.c:2211	LOG_DEBUG("Invalidating L2$.");
arc.c:2224	LOG_DEBUG("Waiting for invalidation end.");
arc.c:2262	LOG_DEBUG("Flushing D$.");
arc.c:2298	LOG_DEBUG("Flushing L2$.");
arc.c:2305	LOG_DEBUG("Waiting for flushing end.");
arc.h:250	LOG_DEBUG("error while calling \"%s\"", \
arc_cmd.c:133	LOG_DEBUG("-");
arc_cmd.c:180	LOG_DEBUG("added flags type {name=%s}", type->data_type.id);
arc_cmd.c:446	LOG_DEBUG("-");
arc_cmd.c:493	LOG_DEBUG("added struct type {name=%s}", type->data_type.id);
arc_cmd.c:764	LOG_DEBUG("-");
arc_jtag.c:245	LOG_DEBUG("Writing to %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32
arc_jtag.c:286	LOG_DEBUG("Reading %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32,
arc_jtag.c:316	LOG_DEBUG("Read from register: buf[0]=0x%" PRIx32, buffer[0]);
arc_jtag.c:442	LOG_DEBUG("Writing to memory: addr=0x%08" PRIx32 ";count=%" PRIu32 ";buffer[0]=0x%08" PRIx32,
arc_jtag.c:495	LOG_DEBUG("Reading memory: addr=0x%" PRIx32 ";count=%" PRIu32 ";slow=%c",
arc_mem.c:38	LOG_DEBUG("Write 4-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
arc_mem.c:69	LOG_DEBUG("Write 2-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
arc_mem.c:127	LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
arc_mem.c:161	LOG_DEBUG("address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
arc_mem.c:223	LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
arc_mem.c:246	LOG_DEBUG("Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
arm-jtag-ew.c:368	LOG_DEBUG("trst: %i, srst: %i", trst, srst);
arm11.c:46	LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
arm11.c:47	LOG_DEBUG("Bringing target into debug mode");
arm11.c:181	LOG_DEBUG("Reset c1 Control Register");
arm11.c:316	LOG_DEBUG("enter TARGET_HALTED");
arm11.c:328	LOG_DEBUG("enter TARGET_RUNNING");
arm11.c:357	LOG_DEBUG("target->state: %s",
arm11.c:364	LOG_DEBUG("target was already halted");
arm11.c:447	LOG_DEBUG("target->state: %s",
arm11.c:458	LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
arm11.c:472	LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
arm11.c:498	LOG_DEBUG("Add BP %d at %08" TARGET_PRIxADDR, brp_num,
arm11.c:519	LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
arm11.c:550	LOG_DEBUG("target->state: %s",
arm11.c:562	LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
arm11.c:574	LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address);
arm11.c:580	LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address);
arm11.c:584	LOG_DEBUG("Not stepping jump to self");
arm11.c:665	LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
arm11.c:805	LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
arm11.c:903	LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
arm11.c:1060	LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
arm11.c:1065	LOG_DEBUG("only breakpoints of four bytes length supported");
arm11.c:1204	LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
arm11.h:22	LOG_DEBUG("error while calling \"%s\"", \
arm11_dbgtap.c:24	LOG_DEBUG(expr); } while (0)
arm720t.c:80	LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
arm720t.c:199	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
arm7_9_common.c:62	LOG_DEBUG("-");
arm7_9_common.c:95	LOG_DEBUG("BPID: %" PRIu32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %u",
arm7_9_common.c:146	LOG_DEBUG("SW BP using hw wp: %d",
arm7_9_common.c:181	LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
arm7_9_common.c:293	LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR,
arm7_9_common.c:303	LOG_DEBUG("BPID: %" PRIu32 " Releasing hw wp: %d",
arm7_9_common.c:813	LOG_DEBUG("DBGACK already set during server startup.");
arm7_9_common.c:875	LOG_DEBUG("target->state: %s", target_state_name(target));
arm7_9_common.c:970	LOG_DEBUG("target->state: %s", target_state_name(target));
arm7_9_common.c:1117	LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
arm7_9_common.c:1178	LOG_DEBUG("target->state: %s",
arm7_9_common.c:1182	LOG_DEBUG("target was already halted");
arm7_9_common.c:1269	LOG_DEBUG("target entered debug from Thumb state");
arm7_9_common.c:1274	LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
arm7_9_common.c:1282	LOG_DEBUG("target entered debug from Jazelle state");
arm7_9_common.c:1287	LOG_DEBUG("target entered debug from ARM state");
arm7_9_common.c:1314	LOG_DEBUG("target entered debug state in %s mode",
arm7_9_common.c:1318	LOG_DEBUG("thumb state, applying fixups");
arm7_9_common.c:1335	LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
arm7_9_common.c:1343	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
arm7_9_common.c:1391	LOG_DEBUG("-");
arm7_9_common.c:1507	LOG_DEBUG("-");
arm7_9_common.c:1526	LOG_DEBUG("examining %s mode",
arm7_9_common.c:1537	LOG_DEBUG("examining dirty reg: %s", reg->name);
arm7_9_common.c:1547	LOG_DEBUG("require mode change");
arm7_9_common.c:1581	LOG_DEBUG("writing register %i mode %s "
arm7_9_common.c:1597	LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "",
arm7_9_common.c:1612	LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
arm7_9_common.c:1617	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
arm7_9_common.c:1627	LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
arm7_9_common.c:1710	LOG_DEBUG("-");
arm7_9_common.c:1733	LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRIu32,
arm7_9_common.c:1752	LOG_DEBUG("enable single-step");
arm7_9_common.c:1775	LOG_DEBUG("disable single-step");
arm7_9_common.c:1789	LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
arm7_9_common.c:1792	LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
arm7_9_common.c:1843	LOG_DEBUG("target resumed");
arm7_9_common.c:1978	LOG_DEBUG("target stepped");
arm7_9_common.c:2118	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
arm7tdmi.c:367	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm7tdmi.c:397	LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm7tdmi.c:541	LOG_DEBUG("-");
arm920t.c:412	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
arm920t.c:450	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
arm920t.c:626	LOG_DEBUG("D-Cache buffered, "
arm920t.c:650	LOG_DEBUG("D-Cache in 'write back' mode, "
arm920t.c:674	LOG_DEBUG("D-Cache enabled, "
arm920t.c:708	LOG_DEBUG("I-Cache enabled, "
arm920t.c:880	LOG_DEBUG("error opening cache content file");
arm920t.c:1162	LOG_DEBUG("error opening mmu content file");
arm926ejs.c:224	LOG_DEBUG("no NEW debug entry (?missed one?)");
arm926ejs.c:229	LOG_DEBUG("breakpoint from EICE unit 0");
arm926ejs.c:233	LOG_DEBUG("breakpoint from EICE unit 1");
arm926ejs.c:237	LOG_DEBUG("soft breakpoint (BKPT instruction)");
arm926ejs.c:241	LOG_DEBUG("vector catch breakpoint");
arm926ejs.c:245	LOG_DEBUG("external breakpoint");
arm926ejs.c:249	LOG_DEBUG("watchpoint from EICE unit 0");
arm926ejs.c:253	LOG_DEBUG("watchpoint from EICE unit 1");
arm926ejs.c:257	LOG_DEBUG("external watchpoint");
arm926ejs.c:261	LOG_DEBUG("internal debug request");
arm926ejs.c:265	LOG_DEBUG("external debug request");
arm926ejs.c:269	LOG_DEBUG("debug re-entry from system speed access");
arm926ejs.c:429	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
arm926ejs.c:458	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
arm946e.c:263	LOG_DEBUG("ERROR writing index");
arm946e.c:271	LOG_DEBUG("ERROR reading dtag");
arm946e.c:282	LOG_DEBUG("ERROR cleaning cache line");
arm946e.c:289	LOG_DEBUG("ERROR flushing cache line");
arm946e.c:305	LOG_DEBUG("FLUSHING I$");
arm946e.c:312	LOG_DEBUG("ERROR flushing I$");
arm946e.c:352	LOG_DEBUG("ERROR disabling cache");
arm946e.c:381	LOG_DEBUG("ERROR enabling cache");
arm946e.c:411	LOG_DEBUG("ERROR writing index");
arm946e.c:418	LOG_DEBUG("ERROR reading dtag");
arm946e.c:431	LOG_DEBUG("ERROR cleaning cache line");
arm946e.c:438	LOG_DEBUG("ERROR flushing cache line");
arm946e.c:468	LOG_DEBUG("ERROR writing index");
arm946e.c:475	LOG_DEBUG("ERROR reading itag");
arm946e.c:488	LOG_DEBUG("ERROR flushing cache line");
arm946e.c:506	LOG_DEBUG("-");
arm946e.c:554	LOG_DEBUG("-");
arm9tdmi.c:441	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm9tdmi.c:476	LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm9tdmi.c:614	LOG_DEBUG("-");
arm_adi_v5.c:400	LOG_DEBUG("AP#0x%" PRIx64 " probed size %u: %s", ap->ap_num, size,
arm_adi_v5.c:409	LOG_DEBUG("probed packing: %s",
arm_adi_v5.c:783	LOG_DEBUG("%s", adiv5_dap_name(dap));
arm_adi_v5.c:816	LOG_DEBUG("DAP: wait CDBGPWRUPACK");
arm_adi_v5.c:824	LOG_DEBUG("DAP: wait CSYSPWRUPACK");
arm_adi_v5.c:859	LOG_DEBUG("%s", adiv5_dap_name(dap));
arm_adi_v5.c:934	LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
arm_adi_v5.c:954	LOG_DEBUG("Enter SWD mode");
arm_adi_v5.c:972	LOG_DEBUG("Enter JTAG mode");
arm_adi_v5.c:1111	LOG_DEBUG("On ADIv6 we cannot scan all the possible AP");
arm_adi_v5.c:1136	LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
arm_adi_v5.c:1146	LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
arm_adi_v5.c:1193	LOG_DEBUG("refcount AP#0x%" PRIx64 " get %u", ap_num, ap->refcount);
arm_adi_v5.c:1203	LOG_DEBUG("refcount AP#0x%" PRIx64 " get_config %u", ap_num, ap->refcount);
arm_adi_v5.c:1218	LOG_DEBUG("refcount AP#0x%" PRIx64 " put %u", ap->ap_num, ap->refcount);
arm_adi_v5.c:1402	LOG_DEBUG("Failed read CoreSight registers");
arm_adi_v5.c:1879	LOG_DEBUG("Failed read ROM table entry");
arm_adi_v5.c:1910	LOG_DEBUG("Wrong AP # 0x%" PRIx64, component_base);
arm_adi_v5.c:1923	LOG_DEBUG("Ignore error parsing CoreSight component");
arm_adi_v5.c:2305	LOG_DEBUG("CS lookup ended in AP # 0x%" PRIx64 ". Ignore it", lookup.ap_num);
arm_adi_v5.c:2308	LOG_DEBUG("CS lookup found at 0x%" PRIx64, lookup.component_base);
arm_adi_v5.c:2313	LOG_DEBUG("CS lookup error %d", retval);
arm_adi_v5.c:2316	LOG_DEBUG("CS lookup not found");
arm_adi_v5.h:682	LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
arm_adi_v5.h:696	LOG_DEBUG("DAP: poll %x timeout", reg);
arm_dap.c:96	LOG_DEBUG("Initializing all DAPs ...");
arm_dap.c:120	LOG_DEBUG("DAP %s configured by default to use ADIv5 protocol", jtag_tap_name(dap->tap));
arm_dap.c:123	LOG_DEBUG("DAP %s configured to use %s protocol by user cfg file", jtag_tap_name(dap->tap),
arm_dpm.c:53	LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
arm_dpm.c:77	LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
arm_dpm.c:101	LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
arm_dpm.c:125	LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
arm_dpm.c:201	LOG_DEBUG("READ: %s, %8.8x, %8.8x", r->name,
arm_dpm.c:269	LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
arm_dpm.c:305	LOG_DEBUG("WRITE: %s, %8.8x, %8.8x", r->name,
arm_dpm.c:354	LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
arm_dpm.c:904	LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
arm_dpm.c:924	LOG_DEBUG("using HW bkpt, not SW...");
arm_dpm.c:968	LOG_DEBUG("watchpoint values and masking not supported");
arm_io.c:50	LOG_DEBUG("%s: no %d byte buffer", __func__, (int) size);
arm_tpiu_swo.c:169	LOG_DEBUG("TPIU/SWO: %s event: %s (%d) action : %s",
arm_tpiu_swo.c:610	LOG_DEBUG("%s: enable deferred", obj->name);
arm_tpiu_swo.c:639	LOG_DEBUG("SWO pin frequency not set, will be autodetected by the adapter");
arm_tpiu_swo.c:1027	LOG_DEBUG("%s: running enable during init", obj->name);
armv4_5.c:485	LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv4_5.c:620	LOG_DEBUG("changing ARM core mode to '%s'",
armv4_5.c:1406	LOG_DEBUG("Running algorithm");
armv4_5.c:1485	LOG_DEBUG("setting core_mode: 0x%2.2x",
armv4_5.c:1554	LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
armv4_5_mmu.c:34	LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
armv4_5_mmu.c:71	LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
armv7a.c:104	LOG_DEBUG("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
armv7a.c:137	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
armv7a.c:172	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
armv7a.c:300	LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
armv7a.c:390	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
armv7a.c:402	LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
armv7a.c:430	LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv7a.c:436	LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv7a.c:450	LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv7a.c:456	LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv7a_cache.c:31	LOG_DEBUG("data cache is not enabled");
armv7a_cache.c:49	LOG_DEBUG("instruction cache is not enabled");
armv7a_cache.c:61	LOG_DEBUG("cl %" PRId32, cl);
armv7a_cache_l2x.c:33	LOG_DEBUG("l2x is not configured!");
armv7a_mmu.c:258	LOG_DEBUG("L1 desc[%8.8x]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
armv7m.c:174	LOG_DEBUG(" ");
armv7m.c:369	LOG_DEBUG("read %s value 0x%016" PRIx64, r->name, q);
armv7m.c:371	LOG_DEBUG("read %s value 0x%08" PRIx32, r->name, reg_value);
armv7m.c:439	LOG_DEBUG("write %s value 0x%016" PRIx64, r->name, q);
armv7m.c:441	LOG_DEBUG("write %s value 0x%08" PRIx32, r->name, t);
armv7m.c:606	LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
armv7m.c:656	LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
armv7m.c:704	LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
armv7m.c:715	LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
armv7m.c:1006	LOG_DEBUG("Starting erase check of %d blocks, parameters@"
armv7m.c:1088	LOG_DEBUG("Skipping over BKPT instruction");
armv8.c:162	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
armv8.c:176	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
armv8.c:319	LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
armv8.c:328	LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
armv8.c:337	LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
armv8.c:346	LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
armv8.c:355	LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
armv8.c:364	LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
armv8.c:373	LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
armv8.c:382	LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
armv8.c:391	LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
armv8.c:480	LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
armv8.c:489	LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
armv8.c:498	LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
armv8.c:507	LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
armv8.c:516	LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
armv8.c:525	LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
armv8.c:534	LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
armv8.c:543	LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
armv8.c:552	LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
armv8.c:964	LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv8.c:1248	LOG_DEBUG("found: %s", n->name);
armv8.c:1967	LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
armv8.c:1994	LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
armv8_cache.c:48	LOG_DEBUG("cl %" PRId32, cl);
armv8_cache.c:327	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
armv8_cache.c:337	LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
armv8_cache.c:364	LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv8_cache.c:370	LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv8_cache.c:384	LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
armv8_cache.c:390	LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
armv8_dpm.c:247	LOG_DEBUG("EL %i -> %" PRIu32, dpm->last_el, (dscr >> 8) & 3);
armv8_dpm.c:472	LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
armv8_dpm.c:495	LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
armv8_dpm.c:520	LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
armv8_dpm.c:551	LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
armv8_dpm.c:554	LOG_DEBUG("setting mode 0x%x", mode);
armv8_dpm.c:589	LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el);
armv8_dpm.c:605	LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
armv8_dpm.c:659	LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64);
armv8_dpm.c:661	LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64);
armv8_dpm.c:674	LOG_DEBUG("READ: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
armv8_dpm.c:675	LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
armv8_dpm.c:680	LOG_DEBUG("Failed to read %s register", r->name);
armv8_dpm.c:702	LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64);
armv8_dpm.c:704	LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64);
armv8_dpm.c:716	LOG_DEBUG("WRITE: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
armv8_dpm.c:717	LOG_DEBUG("WRITE: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
armv8_dpm.c:722	LOG_DEBUG("Failed to write %s register", r->name);
armv8_dpm.c:1157	LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
armv8_dpm.c:1177	LOG_DEBUG("using HW bkpt, not SW...");
armv8_dpm.c:1221	LOG_DEBUG("watchpoint values and masking not supported");
armv8_dpm.c:1327	LOG_DEBUG("Exception taken to EL %i, DLR=0x%016"PRIx64" DSPSR=0x%08"PRIx32,
at91sam3.c:2004	LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
at91sam3.c:2027	LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
at91sam3.c:2111	LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
at91sam3.c:2115	LOG_DEBUG("Error Write failed");
at91sam3.c:2181	LOG_DEBUG("Begin");
at91sam3.c:2196	LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
at91sam3.c:2212	LOG_DEBUG("Here");
at91sam3.c:2228	LOG_DEBUG("Here");
at91sam3.c:2269	LOG_DEBUG("Here");
at91sam3.c:2283	LOG_DEBUG("Failed: %d", r);
at91sam3.c:2287	LOG_DEBUG("End: %d", r);
at91sam3.c:2333	LOG_DEBUG("Here");
at91sam3.c:2337	LOG_DEBUG("End: %d", r);
at91sam3.c:2923	LOG_DEBUG("Start: %s", reg->name);
at91sam3.c:2932	LOG_DEBUG("End: %s", reg->name);
at91sam3.c:2957	LOG_DEBUG("Begin");
at91sam3.c:2973	LOG_DEBUG("Failed: %d", r);
at91sam3.c:2979	LOG_DEBUG("Done");
at91sam3.c:3076	LOG_DEBUG("Begin");
at91sam3.c:3124	LOG_DEBUG("End");
at91sam3.c:3134	LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
at91sam3.c:3150	LOG_DEBUG("Here");
at91sam3.c:3189	LOG_DEBUG("Bank = %d, nbanks = %d",
at91sam3.c:3216	LOG_DEBUG("Here");
at91sam3.c:3224	LOG_DEBUG("Here,r=%d", r);
at91sam3.c:3234	LOG_DEBUG("Here");
at91sam3.c:3247	LOG_DEBUG("Here");
at91sam3.c:3261	LOG_DEBUG("End: r=%d", r);
at91sam3.c:3299	LOG_DEBUG("Error Read failed: read flash mode register");
at91sam3.c:3307	LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
at91sam3.c:3310	LOG_DEBUG("Error Write failed: set flash mode register");
at91sam3.c:3312	LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
at91sam3.c:3399	LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
at91sam3.c:3400	LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
at91sam3.c:3411	LOG_DEBUG("Special case, all in one page");
at91sam3.c:3431	LOG_DEBUG("Not-Aligned start");
at91sam3.c:3460	LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
at91sam3.c:3475	LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
at91sam3.c:3486	LOG_DEBUG("Done!");
at91sam3.c:3543	LOG_DEBUG("Sam3Info, Failed %d", r);
at91sam4.c:1454	LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
at91sam4.c:1477	LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
at91sam4.c:1561	LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
at91sam4.c:1565	LOG_DEBUG("Error Write failed");
at91sam4.c:1631	LOG_DEBUG("Begin");
at91sam4.c:1646	LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
at91sam4.c:1662	LOG_DEBUG("Here");
at91sam4.c:1678	LOG_DEBUG("Here");
at91sam4.c:1724	LOG_DEBUG("Here");
at91sam4.c:1765	LOG_DEBUG("Here");
at91sam4.c:1779	LOG_DEBUG("Failed: %d", r);
at91sam4.c:1783	LOG_DEBUG("End: %d", r);
at91sam4.c:1829	LOG_DEBUG("Here");
at91sam4.c:1837	LOG_DEBUG("End: %d", r);
at91sam4.c:2416	LOG_DEBUG("Start: %s", reg->name);
at91sam4.c:2425	LOG_DEBUG("End: %s", reg->name);
at91sam4.c:2450	LOG_DEBUG("Begin");
at91sam4.c:2466	LOG_DEBUG("Failed: %d", r);
at91sam4.c:2472	LOG_DEBUG("Done");
at91sam4.c:2562	LOG_DEBUG("Begin");
at91sam4.c:2580	LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
at91sam4.c:2612	LOG_DEBUG("End");
at91sam4.c:2640	LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
at91sam4.c:2656	LOG_DEBUG("Here");
at91sam4.c:2668	LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
at91sam4.c:2698	LOG_DEBUG("Bank = %d, nbanks = %d",
at91sam4.c:2730	LOG_DEBUG("Here");
at91sam4.c:2738	LOG_DEBUG("Here,r=%d", r);
at91sam4.c:2748	LOG_DEBUG("Here");
at91sam4.c:2779	LOG_DEBUG("Here");
at91sam4.c:2793	LOG_DEBUG("End: r=%d", r);
at91sam4.c:2836	LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
at91sam4.c:2856	LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
at91sam4.c:2947	LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
at91sam4.c:2948	LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
at91sam4.c:2959	LOG_DEBUG("Special case, all in one page");
at91sam4.c:2979	LOG_DEBUG("Not-Aligned start");
at91sam4.c:3008	LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
at91sam4.c:3023	LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
at91sam4.c:3034	LOG_DEBUG("Done!");
at91sam4.c:3091	LOG_DEBUG("Sam4Info, Failed %d", r);
at91sam4l.c:440	LOG_DEBUG("Erasing the whole chip");
at91sam4l.c:448	LOG_DEBUG("Erasing sectors %u through %u...\n", first, last);
at91sam4l.c:469	LOG_DEBUG("Page %u was not erased.", pn);
at91sam4l.c:486	LOG_DEBUG("sam4l_write_page address=%08" PRIx32, address);
at91sam4l.c:524	LOG_DEBUG("sam4l_write_page_partial address=%08" PRIx32 " nb=%08" PRIx32, address, nb);
at91sam4l.c:554	LOG_DEBUG("sam4l_write offset=%08" PRIx32 " count=%08" PRIx32, offset, count);
at91sam7.c:280	LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
at91sam7.c:294	LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
at91sam7.c:298	LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
at91sam7.c:322	LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
at91sam7.c:630	LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
at91sam7.c:930	LOG_DEBUG("first_page: %i, last_page: %i, count %i",
at91sam7.c:957	LOG_DEBUG("Write flash bank:%u page number:%" PRIu32, bank->bank_number, pagen);
at91sam7.c:1086	LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32,
at91sam9.c:488	LOG_DEBUG("AT91SAM9 NAND Device Command");
ath79.c:266	LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08" PRIx32 ", %p, %d)",
ath79.c:269	LOG_DEBUG("max code %d => max len %d. to_xfer %d",
ath79.c:275	LOG_DEBUG("Assembled %d instructions, %d stores",
ath79.c:304	LOG_DEBUG("bitbang %02x => %02x",
ath79.c:352	LOG_DEBUG("%s", __func__);
ath79.c:496	LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
ath79.c:610	LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
ath79.c:638	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
ath79.c:679	LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
ath79.c:707	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
ath79.c:782	LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
atsamv.c:95	LOG_DEBUG("starting flash command: 0x%08x", (unsigned int)(v));
atsamv.c:98	LOG_DEBUG("write failed");
atsamv.c:204	LOG_DEBUG("get gpnvm failed: %d", r);
atsamv.c:208	LOG_DEBUG("clear gpnvm result: %d", r);
atsamv.c:439	LOG_DEBUG("write page %u at address 0x%08x", pagenum, (unsigned int)addr);
atsamv.c:484	LOG_DEBUG("offset: 0x%08x, count: 0x%08x",
atsamv.c:486	LOG_DEBUG("page start: %d, page end: %d", (int)(page_cur), (int)(page_end));
atsamv.c:499	LOG_DEBUG("special case, all in one page");
atsamv.c:516	LOG_DEBUG("non-aligned start");
atsamv.c:540	LOG_DEBUG("full page loop: cur=%d, end=%d, count = 0x%08x",
atsamv.c:554	LOG_DEBUG("final partial page, count = 0x%08x", (unsigned int)(count));
avr32_ap7k.c:120	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
avr32_ap7k.c:260	LOG_DEBUG("target->state: %s",
avr32_ap7k.c:264	LOG_DEBUG("target was already halted");
avr32_ap7k.c:340	LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
avr32_ap7k.c:375	LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
avr32_ap7k.c:379	LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
avr32_ap7k.c:428	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
avr32_ap7k.c:468	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
avrf.c:129	LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
avrf.c:190	LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
avrf.c:218	LOG_DEBUG("%s", __func__);
avrf.c:256	LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
avrf.c:257	LOG_DEBUG("count is %" PRIu32 "", count);
avrf.c:436	LOG_DEBUG("%s", __func__);
avrt.c:83	LOG_DEBUG("%s", __func__);
avrt.c:89	LOG_DEBUG("%s", __func__);
avrt.c:98	LOG_DEBUG("%s", __func__);
avrt.c:104	LOG_DEBUG("%s", __func__);
avrt.c:111	LOG_DEBUG("%s", __func__);
avrt.c:117	LOG_DEBUG("%s", __func__);
avrt.c:125	LOG_DEBUG("%s", __func__);
avrt.c:133	LOG_DEBUG("%s", __func__);
batch.c:91	LOG_DEBUG("Ignoring empty batch.");
bluenrg-x.c:194	LOG_DEBUG("address = %08" PRIx32 ", index = %u", address, i);
bluenrg-x.c:291	LOG_DEBUG("no working area for target algorithm stack");
bluenrg-x.c:328	LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
bluenrg-x.c:329	LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
bluenrg-x.c:330	LOG_DEBUG("write_algorithm_stack->address = " TARGET_ADDR_FMT, write_algorithm_stack->address);
bluenrg-x.c:331	LOG_DEBUG("address = %08" PRIx32, address);
bluenrg-x.c:332	LOG_DEBUG("count = %08" PRIx32, count);
breakpoints.c:646	LOG_DEBUG("Delete all watchpoints for target: %s",
cfi.c:337	LOG_DEBUG("status: 0x%x", status);
cfi.c:391	LOG_DEBUG("status: 0x%x", status);
cfi.c:396	LOG_DEBUG("status: 0x%x", status);
cfi.c:449	LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
cfi.c:462	LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
cfi.c:475	LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
cfi.c:497	LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
cfi.c:550	LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
cfi.c:587	LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
cfi.c:590	LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
cfi.c:594	LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->burst_mode, pri_ext->page_mode);
cfi.c:597	LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
cfi.c:601	LOG_DEBUG("WP# protection 0x%x", pri_ext->top_bottom);
cfi.c:660	LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
cfi.c:680	LOG_DEBUG(
cfi.c:1288	LOG_DEBUG("Using target buffer at " TARGET_ADDR_FMT " and of size 0x%04" PRIx32,
cfi.c:1308	LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32,
cfi.c:2195	LOG_DEBUG("Buffer Writes Not Supported");
cfi.c:2222	LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
cfi.c:2467	LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
cfi.c:2518	LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
cfi.c:2652	LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
cfi.c:2711	LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
cfi.c:2725	LOG_DEBUG(
cfi.c:2767	LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
cfi.c:2773	LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
cfi.c:2778	LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
cfi.c:2795	LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
chibios.c:248	LOG_DEBUG("Enabled FPU detected.");
chromium-ec.c:93	LOG_DEBUG("Chromium-EC: Symbol \"%s\" found",
chromium-ec.c:207	LOG_DEBUG("Current task: %lx tasks_found: %d",
cmsis_dap.c:329	LOG_DEBUG("Flushed %u packets", i);
cmsis_dap.c:795	LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
cmsis_dap.c:845	LOG_DEBUG("refusing to enable sticky overrun detection");
cmsis_dap.c:909	LOG_DEBUG("error reading adapter response");
cmsis_dap.c:939	LOG_DEBUG("CMSIS-DAP Protocol Error @ %d (wrong parity)", transfer_count);
cmsis_dap.c:945	LOG_DEBUG("SWD ack not OK @ %d %s", transfer_count,
cmsis_dap.c:1252	LOG_DEBUG("JTAG-to-SWD");
cmsis_dap.c:1257	LOG_DEBUG("JTAG-to-DORMANT");
cmsis_dap.c:1262	LOG_DEBUG("SWD-to-JTAG");
cmsis_dap.c:1267	LOG_DEBUG("SWD-to-DORMANT");
cmsis_dap.c:1272	LOG_DEBUG("DORMANT-to-SWD");
cmsis_dap.c:1277	LOG_DEBUG("DORMANT-to-JTAG");
cmsis_dap.c:1369	LOG_DEBUG("CMSIS-DAP: Packet Size = %" PRIu16, pkt_sz);
cmsis_dap.c:1393	LOG_DEBUG("CMSIS-DAP: Packet Count = %u", pkt_cnt);
cmsis_dap.c:1396	LOG_DEBUG("Allocating FIFO for %u pending packets", cmsis_dap_handle->packet_count);
cmsis_dap.c:1752	LOG_DEBUG("discarding trailing empty field");
cmsis_dap.c:1756	LOG_DEBUG("empty scan, doing nothing");
cmsis_dap_usb_bulk.c:124	LOG_DEBUG("could not open device 0x%04x:0x%04x: %s",
cmsis_dap_usb_bulk.c:145	LOG_DEBUG(msg, dev_desc.idVendor, dev_desc.idProduct,
cmsis_dap_usb_bulk.c:169	LOG_DEBUG("found product string of 0x%04x:0x%04x '%s'",
cmsis_dap_usb_bulk.c:189	LOG_DEBUG("enumerating interfaces of 0x%04x:0x%04x",
cmsis_dap_usb_bulk.c:230	LOG_DEBUG("could not read interface string %d for device 0x%04x:0x%04x: %s",
cmsis_dap_usb_bulk.c:236	LOG_DEBUG("found interface %d string '%s'",
cmsis_dap_usb_bulk.c:249	LOG_DEBUG("skipping interface %d, has only %d endpoints",
cmsis_dap_usb_bulk.c:256	LOG_DEBUG("skipping interface %d, endpoint[0] is not bulk out",
cmsis_dap_usb_bulk.c:263	LOG_DEBUG("skipping interface %d, endpoint[1] is not bulk in",
cmsis_dap_usb_bulk.c:295	LOG_DEBUG("skipping interface %d, class %" PRId8
cmsis_dap_usb_bulk.c:494	LOG_DEBUG("command write USB timeout @ %u", dap->pending_fifo_get_idx);
cmsis_dap_usb_bulk.c:508	LOG_DEBUG("USB timeout @ %u", dap->pending_fifo_get_idx);
cmsis_dap_usb_bulk.c:543	LOG_DEBUG("USB write timeout @ %u, late detect", dap->pending_fifo_get_idx);
cmsis_dap_usb_hid.c:98	LOG_DEBUG("Cannot read product string of device 0x%x:0x%x",
command.c:153	LOG_DEBUG("%s", dbg);
command.c:259	LOG_DEBUG("command '%s' is already registered", full_name);
command.c:271	LOG_DEBUG("registering '%s'...", full_name);
command.c:370	LOG_DEBUG("delete command \"%s\"", name);
command.c:528	LOG_DEBUG("Command '%s' failed with error code %d",
commands.c:211	LOG_DEBUG("fields[%u].out_value[%u]: 0x%s", i,
commands.c:253	LOG_DEBUG("fields[%u].in_value[%u]: 0x%s",
configuration.c:33	LOG_DEBUG("adding %s", dir);
configuration.c:88	LOG_DEBUG("found %s", full_path);
core.c:314	LOG_DEBUG("controller initialization failed");
core.c:372	LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
core.c:474	LOG_DEBUG("controller initialization failed");
core.c:107	LOG_DEBUG("call flash_driver_read()");
core.c:156	LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
core.c:596	LOG_DEBUG("iterating over more than one flash bank.");
core.c:856	LOG_DEBUG("Truncate flash run size to the current flash chip.");
core.c:939	LOG_DEBUG("image_read_section: section = %d, t_section_num = %d, "
core.c:328	LOG_DEBUG("jtag event: %s", jtag_event_strings[event]);
core.c:556	LOG_DEBUG("cur_state=%s goal_state=%s",
core.c:636	LOG_DEBUG("SRST line asserted");
core.c:640	LOG_DEBUG("SRST line released");
core.c:714	LOG_DEBUG("SRST line asserted");
core.c:718	LOG_DEBUG("SRST line released");
core.c:731	LOG_DEBUG("JTAG reset with TLR instead of TRST");
core.c:737	LOG_DEBUG("TRST line asserted");
core.c:742	LOG_DEBUG("TRST line released");
core.c:826	LOG_DEBUG("SRST line asserted");
core.c:830	LOG_DEBUG("SRST line released");
core.c:843	LOG_DEBUG("JTAG reset with TLR instead of TRST");
core.c:850	LOG_DEBUG("TRST line asserted");
core.c:855	LOG_DEBUG("TRST line released");
core.c:1235	LOG_DEBUG("DR scan interrogation for IDCODE/BYPASS");
core.c:1365	LOG_DEBUG("IR capture validation scan");
core.c:1422	LOG_DEBUG("%s: IR capture 0x%0*" PRIx64, jtag_tap_name(tap),
core.c:1475	LOG_DEBUG("Created Tap: %s @ abs position %u, "
core.c:1510	LOG_DEBUG("Init JTAG chain");
core.c:1592	LOG_DEBUG("Initializing with hard SRST reset");
core.c:1607	LOG_DEBUG("Initializing with hard TRST+SRST reset");
cortex_a.c:193	LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32,
cortex_a.c:292	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
cortex_a.c:335	LOG_DEBUG("write DCC 0x%08" PRIx32, data);
cortex_a.c:598	LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
cortex_a.c:628	LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
cortex_a.c:764	LOG_DEBUG("Target halted");
cortex_a.c:881	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
cortex_a.c:1012	LOG_DEBUG("target resumed at " TARGET_ADDR_FMT, address);
cortex_a.c:1016	LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT, address);
cortex_a.c:1030	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
cortex_a.c:1114	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
cortex_a.c:1141	LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
cortex_a.c:1258	LOG_DEBUG("target stepped");
cortex_a.c:1267	LOG_DEBUG(" ");
cortex_a.c:1322	LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1414	LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1444	LOG_DEBUG("brp(CTX) found num: %d", brp_1);
cortex_a.c:1454	LOG_DEBUG("brp(IVA) found num: %d", brp_2);
cortex_a.c:1519	LOG_DEBUG("Invalid BRP number in breakpoint");
cortex_a.c:1522	LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1538	LOG_DEBUG("Invalid BRP number in breakpoint");
cortex_a.c:1541	LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
cortex_a.c:1563	LOG_DEBUG("Invalid BRP number in breakpoint");
cortex_a.c:1566	LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
cortex_a.c:1784	LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
cortex_a.c:1813	LOG_DEBUG("Invalid WRP number in watchpoint");
cortex_a.c:1816	LOG_DEBUG("wrp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i,
cortex_a.c:1889	LOG_DEBUG(" ");
cortex_a.c:1930	LOG_DEBUG(" ");
cortex_a.c:2254	LOG_DEBUG("Writing CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
cortex_a.c:2571	LOG_DEBUG("Reading CPU memory address 0x%" PRIx32 " size %" PRIu32 " count %" PRIu32,
cortex_a.c:2720	LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2737	LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2756	LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2773	LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2928	LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
cortex_a.c:2938	LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
cortex_a.c:2950	LOG_DEBUG("Examine %s failed", "DIDR");
cortex_a.c:2957	LOG_DEBUG("Examine %s failed", "CPUID");
cortex_a.c:2961	LOG_DEBUG("didr = 0x%08" PRIx32, didr);
cortex_a.c:2962	LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
cortex_a.c:3054	LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
cortex_a.c:3068	LOG_DEBUG("Configured %i hw watchpoints", cortex_a->wrp_num);
dsp563xx.c:404	LOG_DEBUG("%s", __func__);
dsp563xx.c:414	LOG_DEBUG("%s", __func__);
dsp563xx.c:571	LOG_DEBUG("%s conditional branch not supported yet (0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 ")",
dsp563xx.c:900	LOG_DEBUG("%s", __func__);
dsp563xx.c:940	LOG_DEBUG("%s", __func__);
dsp563xx.c:1070	LOG_DEBUG("target->state: %s (%" PRIx32 ")", target_state_name(target), once_status);
dsp563xx.c:1098	LOG_DEBUG("%s", __func__);
dsp563xx.c:1101	LOG_DEBUG("target was already halted");
dsp563xx.c:1138	LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
dsp563xx.c:1186	LOG_DEBUG("target was not halted");
dsp563xx.c:1202	LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
dsp563xx.c:1263	LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff);
dsp563xx.c:1267	LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff);
dsp563xx.c:1271	LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff);
dsp563xx.c:1341	LOG_DEBUG("%s", __func__);
dsp563xx.c:1369	LOG_DEBUG("%s", __func__);
dsp563xx.c:1519	LOG_DEBUG(
dsp563xx.c:1614	LOG_DEBUG("size is not aligned to 4 byte");
dsp563xx.c:1700	LOG_DEBUG(
dsp563xx.c:1788	LOG_DEBUG("size is not aligned to 4 byte");
dsp563xx_once.c:135	LOG_DEBUG("debug request: %02X", ir_in);
dsp563xx_once.c:156	LOG_DEBUG("enable once: %02X", ir_in);
dsp563xx_once.c:159	LOG_DEBUG("error");
dsp5680xx.c:97	LOG_DEBUG("Data read (%d bits): 0x%04X", len, *d_out);
dsp5680xx.c:99	LOG_DEBUG("Data read was discarded.");
dsp5680xx.c:177	LOG_DEBUG("Data read (%d bits): 0x%04X", num_bits, *data_read);
dsp5680xx.c:529	LOG_DEBUG("Reg. data: 0x%02X.", *data_read);
dsp5680xx.c:676	LOG_DEBUG("EOnCE successfully entered debug mode.");
dsp5680xx.c:816	LOG_DEBUG("EOnCE successfully entered debug mode.");
dsp5680xx.c:872	LOG_DEBUG("target initiated!");
dsp5680xx.c:1031	LOG_DEBUG("EOnCE status: 0x%02X.", eonce_status);
dsp5680xx.c:1109	LOG_DEBUG("%s:Data read from 0x%06" PRIX32 ": 0x%02X%02X", __func__, address,
dsp5680xx.c:1731	LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",
dsp5680xx.c:1735	LOG_DEBUG
dsp5680xx.c:1756	LOG_DEBUG("HFM CLK divisor set to 0x%02x.", i[0] & 0x7f);
dsp5680xx_flash.c:157	LOG_DEBUG("%s not implemented", __func__);
eCos.c:544	LOG_DEBUG("eCos: %s 0x%016" PRIX64 " %s",
efm32.c:433	LOG_DEBUG("status: 0x%" PRIx32 "", status);
efm32.c:465	LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
efm32.c:480	LOG_DEBUG("status 0x%" PRIx32, status);
efm32.c:923	LOG_DEBUG("status 0x%" PRIx32, status);
em357.c:118	LOG_DEBUG("status: 0x%" PRIx32 "", status);
embeddedice.c:505	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
eneispif.c:51	LOG_DEBUG("%s", __func__);
eneispif.c:85	LOG_DEBUG("Read address " TARGET_ADDR_FMT " = 0x%" PRIx32,
eneispif.c:95	LOG_DEBUG("Write address " TARGET_ADDR_FMT " = 0x%" PRIx32,
eneispif.c:166	LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
eneispif.c:219	LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32, bank->size, offset,
eneispif.c:305	LOG_DEBUG("ISPCFG = (0x%08" PRIx32 ")", conf);
eneispif.c:321	LOG_DEBUG("ISPDAT = (0x%08" PRIx32 ")", value);
esirisc.c:163	LOG_DEBUG("-");
esirisc.c:215	LOG_DEBUG("-");
esirisc.c:232	LOG_DEBUG("-");
esirisc.c:268	LOG_DEBUG("-");
esirisc.c:284	LOG_DEBUG("-");
esirisc.c:301	LOG_DEBUG("-");
esirisc.c:319	LOG_DEBUG("-");
esirisc.c:340	LOG_DEBUG("-");
esirisc.c:362	LOG_DEBUG("-");
esirisc.c:411	LOG_DEBUG("-");
esirisc.c:463	LOG_DEBUG("-");
esirisc.c:480	LOG_DEBUG("-");
esirisc.c:531	LOG_DEBUG("-");
esirisc.c:551	LOG_DEBUG("-");
esirisc.c:579	LOG_DEBUG("-");
esirisc.c:599	LOG_DEBUG("-");
esirisc.c:616	LOG_DEBUG("-");
esirisc.c:715	LOG_DEBUG("-");
esirisc.c:735	LOG_DEBUG("-");
esirisc.c:763	LOG_DEBUG("-");
esirisc.c:782	LOG_DEBUG("-");
esirisc.c:805	LOG_DEBUG("-");
esirisc.c:831	LOG_DEBUG("-");
esirisc.c:858	LOG_DEBUG("-");
esirisc.c:924	LOG_DEBUG("-");
esirisc.c:933	LOG_DEBUG("-");
esirisc.c:945	LOG_DEBUG("-");
esirisc.c:974	LOG_DEBUG("-");
esirisc.c:1003	LOG_DEBUG("-");
esirisc.c:1037	LOG_DEBUG("-");
esirisc.c:1125	LOG_DEBUG("-");
esirisc.c:1156	LOG_DEBUG("-");
esirisc.c:1189	LOG_DEBUG("-");
esirisc.c:1255	LOG_DEBUG("-");
esirisc.c:1275	LOG_DEBUG("-");
esirisc.c:1305	LOG_DEBUG("-");
esirisc.c:1328	LOG_DEBUG("-");
esirisc.c:1350	LOG_DEBUG("-");
esirisc.c:1373	LOG_DEBUG("-");
esirisc.c:1393	LOG_DEBUG("-");
esirisc.c:1408	LOG_DEBUG("-");
esirisc.c:1432	LOG_DEBUG("-");
esirisc.c:1522	LOG_DEBUG("-");
esirisc.c:1632	LOG_DEBUG("-");
esirisc_flash.c:421	LOG_DEBUG("TIMING0: 0x%" PRIx32, value);
esirisc_flash.c:426	LOG_DEBUG("TIMING1: 0x%" PRIx32, value);
esirisc_flash.c:433	LOG_DEBUG("TIMING2: 0x%" PRIx32, value);
esirisc_jtag.c:260	LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx8, address, *data);
esirisc_jtag.c:288	LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx16, address, *data);
esirisc_jtag.c:316	LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, *data);
esirisc_jtag.c:326	LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx8, address, data);
esirisc_jtag.c:346	LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx16, address, data);
esirisc_jtag.c:367	LOG_DEBUG("address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data);
esirisc_jtag.c:404	LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, *data);
esirisc_jtag.c:414	LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, data);
esirisc_jtag.c:452	LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, *data);
esirisc_jtag.c:462	LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, data);
esp.c:77	LOG_DEBUG("Check dbg stub %d - %x", i, dbg_stubs->entries[i]);
esp.c:79	LOG_DEBUG("New dbg stub %d at %x", dbg_stubs->entries_count, dbg_stubs->entries[i]);
esp32.c:102	LOG_DEBUG("start");
esp32.c:105	LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
esp32.c:109	LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
esp32.c:158	LOG_DEBUG("Loading stub code into RTC RAM");
esp32.c:175	LOG_DEBUG("Resuming the target");
esp32.c:184	LOG_DEBUG("resume done, waiting for the target to come alive");
esp32.c:202	LOG_DEBUG("halting the target");
esp32.c:206	LOG_DEBUG("restoring RTC_SLOW_MEM");
esp32_apptrace.c:222	LOG_DEBUG("apptrace: Failed to create socket (%d, %d, %d) (%s)",
esp32_apptrace.c:353	LOG_DEBUG("esp32_apptrace_ready_block_put");
esp32_apptrace.c:667	LOG_DEBUG("Halt all targets!");
esp32_apptrace.c:688	LOG_DEBUG("Read current block statuses");
esp32_apptrace.c:792	LOG_DEBUG("Resume targets");
esp32_apptrace.c:881	LOG_DEBUG("Got block %" PRId32 " bytes [%x %x...%x %x]", data_len, data[12], data[13],
esp32_apptrace.c:922	LOG_DEBUG("Got block %" PRId32 " bytes", block->data_len);
esp32_apptrace.c:925	LOG_DEBUG("Process usr block %" PRId32 "/%" PRId32, processed, block->data_len);
esp32_sysview.c:321	LOG_DEBUG("sysview: evt %d len %d plen %d dlen %d",
esp32_sysview.c:421	LOG_DEBUG("sysview: Redirect %d bytes of event %d to dest %d", wr_len, event_id, i);
esp32_sysview.c:449	LOG_DEBUG("sysview: Read from target %d bytes [%x %x %x %x]",
esp32_sysview.c:469	LOG_DEBUG("sysview: Process %d sync bytes", SYSVIEW_SYNC_LEN);
esp32_sysview.c:513	LOG_DEBUG("sysview: Process packet: core %d, %d id, %d bytes [%x %x %x %x]",
esp32s2.c:183	LOG_DEBUG("start");
esp32s3.c:99	LOG_DEBUG("start");
esp32s3.c:102	LOG_DEBUG("Target not halted before SoC reset, trying to halt it first");
esp32s3.c:106	LOG_DEBUG("Couldn't halt target before SoC reset, trying to do reset-halt");
esp32s3.c:155	LOG_DEBUG("Loading stub code into RTC RAM");
esp32s3.c:175	LOG_DEBUG("Resuming the target");
esp32s3.c:184	LOG_DEBUG("resume done, waiting for the target to come alive");
esp32s3.c:203	LOG_DEBUG("halting the target");
esp32s3.c:207	LOG_DEBUG("restoring RTC_SLOW_MEM");
esp_algorithm.c:95	LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT,
esp_algorithm.c:117	LOG_DEBUG("Wait algorithm completion");
esp_algorithm.c:136	LOG_DEBUG("Got algorithm RC 0x%" PRIx32, run->ret_code);
esp_algorithm.c:165	LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT,
esp_algorithm.c:180	LOG_DEBUG("Wait algorithm completion");
esp_algorithm.c:195	LOG_DEBUG("Got algorithm RC 0x%" PRIx32, run->ret_code);
esp_algorithm.c:321	LOG_DEBUG("stub: base 0x%x, start 0x%" PRIx32 ", %d sections",
esp_algorithm.c:352	LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64,
esp_algorithm.c:408	LOG_DEBUG("Write reversed tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, al_tramp_size);
esp_algorithm.c:411	LOG_DEBUG("Write tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, tramp_sz);
esp_algorithm.c:422	LOG_DEBUG("Tramp mapped to addr " TARGET_ADDR_FMT, run->stub.tramp_mapped_addr);
esp_algorithm.c:446	LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64, section->base_address, section->size,
esp_algorithm.c:451	LOG_DEBUG("DATA sec size %" PRIu32 " -> %" PRIu32, section->size, data_sec_sz);
esp_algorithm.c:453	LOG_DEBUG("BSS sec size %" PRIu32 " -> %" PRIu32, run->image.bss_size, bss_sec_sz);
esp_algorithm.c:494	LOG_DEBUG("Stub loaded in %g ms", duration_elapsed(&algo_time) * 1000);
esp_algorithm.c:579	LOG_DEBUG("Stub loaded in %g ms", duration_elapsed(&algo_time) * 1000);
esp_xtensa.c:89	LOG_DEBUG("start");
esp_xtensa_algorithm.c:98	LOG_DEBUG("reg params count %d (%d/%d).",
esp_xtensa_algorithm.c:116	LOG_DEBUG("Set arg[0] = %d (%s)", arg, run->reg_args.params[run->reg_args.first_user_param + 0].reg_name);
esp_xtensa_algorithm.c:125	LOG_DEBUG("Set arg[%d] = %d (%s)", i, arg, run->reg_args.params[run->reg_args.first_user_param + i].reg_name);
esp_xtensa_apptrace.c:83	LOG_DEBUG("ctrl=0x%" PRIx32 " memadrstart=0x%" PRIx32 " memadrend=0x%" PRIx32 " traxadr=0x%" PRIx32,
esp_xtensa_apptrace.c:169	LOG_DEBUG("Read data on target (%s)", target_name(target));
esp_xtensa_apptrace.c:177	LOG_DEBUG("Ack block %" PRIu32 " target (%s)!", block_id, target_name(target));
esp_xtensa_apptrace.c:487	LOG_DEBUG("Ack block %" PRId32 " on target (%s)!", block_id, target_name(target));
esp_xtensa_smp.c:194	LOG_DEBUG("Failed to examine!");
esp_xtensa_smp.c:259	LOG_DEBUG("GDB target '%s'", target_name(target->gdb_service->target));
esp_xtensa_smp.c:273	LOG_DEBUG("Check target '%s'", target_name(curr));
esp_xtensa_smp.c:287	LOG_DEBUG("Poll target '%s'", target_name(curr));
esp_xtensa_smp.c:318	LOG_DEBUG("exit");
etb.c:209	LOG_DEBUG("%i", (int)(etb_reg->addr));
etb.c:290	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
etm.c:325	LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
etm.c:501	LOG_DEBUG("%s (%u)", r->name, reg_addr);
etm.c:588	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
etm.c:1402	LOG_DEBUG("out of memory");
etm.c:1498	LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
fa526.c:126	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
fa526.c:163	LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
feroceon.c:240	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
feroceon.c:282	LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
feroceon.c:331	LOG_DEBUG("-");
fespi.c:137	LOG_DEBUG("%s", __func__);
fespi.c:153	LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
fespi.c:363	LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
fespi.c:489	LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32,
fespi.c:586	LOG_DEBUG("Failed to write %d bytes to " TARGET_ADDR_FMT ": %d",
fespi.c:591	LOG_DEBUG("write(ctrl_base=0x%" TARGET_PRIxADDR ", page_size=0x%x, "
fespi.c:750	LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
fespi.c:754	LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
fm3.c:188	LOG_DEBUG("fm3_busy_wait(%" PRIx32 ") needs about %d ms", offset, ms);
fm4.c:121	LOG_DEBUG("Spansion FM4 erase sectors %u to %u", first, last);
fm4.c:216	LOG_DEBUG("Spansion FM4 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
fm4.c:276	LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
fm4.c:287	LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
fm4.c:372	LOG_DEBUG("%u sectors", bank->num_sectors);
fm4.c:439	LOG_DEBUG("%u sectors", bank->num_sectors);
ftdi.c:294	LOG_DEBUG("RCLK not supported");
ftdi.c:652	LOG_DEBUG("ftdi interface using 7 step jtag state transitions");
ftdi.c:654	LOG_DEBUG("ftdi interface using shortest path jtag state transitions");
ftdi.c:1142	LOG_DEBUG("Increased SWD command queue to %zu elements", swd_cmd_queue_alloced);
ftdi.c:1200	LOG_DEBUG("SWD line reset");
ftdi.c:1205	LOG_DEBUG("JTAG-to-SWD");
ftdi.c:1210	LOG_DEBUG("JTAG-to-DORMANT");
ftdi.c:1215	LOG_DEBUG("SWD-to-JTAG");
ftdi.c:1220	LOG_DEBUG("SWD-to-DORMANT");
ftdi.c:1225	LOG_DEBUG("DORMANT-to-SWD");
ftdi.c:1230	LOG_DEBUG("DORMANT-to-JTAG");
gdb_server.c:238	LOG_DEBUG("GDB connection closed by the remote client");
gdb_server.c:342	LOG_DEBUG("GDB socket marked as closed, cannot write to it.");
gdb_server.c:687	LOG_DEBUG("Received first acknowledgment after entering noack mode. Ignoring it.");
gdb_server.c:908	LOG_DEBUG("Unknown syscall: %s", target->fileio_info->identifier);
gdb_server.c:1283	LOG_DEBUG("Couldn't get register %s.", reg_list[i]->name);
gdb_server.c:1351	LOG_DEBUG("Couldn't set register %s.", reg_list[i]->name);
gdb_server.c:1403	LOG_DEBUG("Couldn't get register %s.", reg_list[reg_num]->name);
gdb_server.c:1473	LOG_DEBUG("Couldn't set register %s.", reg_list[reg_num]->name);
gdb_server.c:1493	LOG_DEBUG("Reporting %i to GDB as generic error", retval);
gdb_server.c:1531	LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
gdb_server.c:1603	LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
gdb_server.c:1679	LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
gdb_server.c:1711	LOG_DEBUG("-");
gdb_server.c:1737	LOG_DEBUG("continue");
gdb_server.c:1741	LOG_DEBUG("step");
gdb_server.c:1760	LOG_DEBUG("[%s]", target_name(target));
gdb_server.c:3140	LOG_DEBUG("request to step current core only");
gdb_server.c:3164	LOG_DEBUG("fake step thread %"PRIx64, thread_id);
gdb_server.c:3179	LOG_DEBUG("stepi ignored. GDB will now fetch the register state "
gdb_server.c:3458	LOG_DEBUG("wrote %u bytes from vFlash image to flash", (unsigned)written);
gdb_server.c:3498	LOG_DEBUG("-");
gdb_server.c:3511	LOG_DEBUG("File-I/O response, retcode: 0x%x, errno: 0x%x, ctrl-c: %s",
gdb_server.c:3676	LOG_DEBUG("stepi ignored. GDB will now fetch the register state "
gdb_server.c:3772	LOG_DEBUG("ignoring 0x%2.2x packet", packet[0]);
hla_interface.c:43	LOG_DEBUG("hl_interface_open");
hla_interface.c:68	LOG_DEBUG("hl_interface_init_target");
hla_interface.c:110	LOG_DEBUG("hl_interface_init");
hla_interface.c:118	LOG_DEBUG("hl_interface_quit");
hla_interface.c:216	LOG_DEBUG("hl_interface_handle_device_desc_command");
hla_interface.c:229	LOG_DEBUG("hl_interface_handle_layout_command");
hla_layout.c:28	LOG_DEBUG("hl_layout_open");
hla_layout.c:35	LOG_DEBUG("failed");
hla_layout.c:83	LOG_DEBUG("hl_layout_init");
hla_target.c:77	LOG_DEBUG("data 0x%x ctrl 0x%x", value, ctrl);
hla_target.c:163	LOG_DEBUG("%s", __func__);
hla_target.c:183	LOG_DEBUG("%s", __func__);
hla_target.c:193	LOG_DEBUG("%s", __func__);
hla_target.c:278	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
hla_target.c:323	LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
hla_target.c:336	LOG_DEBUG("%s", __func__);
hla_target.c:402	LOG_DEBUG("%s", __func__);
hla_target.c:417	LOG_DEBUG("%s", __func__);
hla_target.c:420	LOG_DEBUG("target was already halted");
hla_target.c:448	LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
hla_target.c:496	LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
hla_target.c:538	LOG_DEBUG("%s", __func__);
hla_target.c:601	LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
hla_target.c:616	LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
hla_transport.c:26	LOG_DEBUG("hl_transport_jtag_command");
hla_transport.c:163	LOG_DEBUG("hl_transport_init");
hla_transport.c:180	LOG_DEBUG("current transport %s", transport->name);
hla_transport.c:200	LOG_DEBUG("hl_jtag_transport_select");
hla_transport.c:211	LOG_DEBUG("hl_swd_transport_select");
hwthread.c:209	LOG_DEBUG("%s current_thread=%i", __func__, (int)rtos->current_thread);
image.c:58	LOG_DEBUG("Less than 9 bytes in the image file found.");
image.c:59	LOG_DEBUG("BIN image detected.");
image.c:69	LOG_DEBUG("ELF image detected.");
image.c:80	LOG_DEBUG("IHEX image detected.");
image.c:87	LOG_DEBUG("S19 image detected.");
image.c:90	LOG_DEBUG("BIN image detected.");
image.c:638	LOG_DEBUG("ELF32 image detected.");
image.c:643	LOG_DEBUG("ELF64 image detected.");
image.c:667	LOG_DEBUG("load segment %d at 0x%" TARGET_PRIxADDR " (sz = 0x%" PRIx32 ")", section, offset, size);
image.c:673	LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
image.c:710	LOG_DEBUG("load segment %d at 0x%" TARGET_PRIxADDR " (sz = 0x%" PRIx32 ")", section, offset, size);
image.c:716	LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
image.c:1090	LOG_DEBUG(
image.c:1271	LOG_DEBUG("Calculating checksum");
image.c:1303	LOG_DEBUG("Calculating checksum done; checksum=0x%" PRIx32, crc);
jep106.c:22	LOG_DEBUG("BUG: Caller passed out-of-range JEP106 ID!");
jlink.c:159	LOG_DEBUG("discarding trailing empty field");
jlink.c:163	LOG_DEBUG("empty scan, doing nothing");
jlink.c:479	LOG_DEBUG("Adjusted SWD transaction buffer size to %u bytes",
jlink.c:649	LOG_DEBUG("Using libjaylink %s (compiled with %s)",
jlink.c:953	LOG_DEBUG("TRST: %i, SRST: %i", trst, srst);
jlink.c:1406	LOG_DEBUG("Using %" PRIu32 " bytes device memory for trace capturing",
jlink.c:2120	LOG_DEBUG("JTAG-to-SWD");
jlink.c:2125	LOG_DEBUG("JTAG-to-DORMANT");
jlink.c:2130	LOG_DEBUG("SWD-to-JTAG");
jlink.c:2135	LOG_DEBUG("SWD-to-DORMANT");
jlink.c:2140	LOG_DEBUG("DORMANT-to-SWD");
jlink.c:2145	LOG_DEBUG("DORMANT-to-JTAG");
jlink.c:2167	LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
jlink.c:2189	LOG_DEBUG("SWD ack not OK: %d %s", ack,
jtagspi.c:88	LOG_DEBUG("loading jtagspi ir(0x%" PRIx32 ")", info->ir);
jtagspi.c:111	LOG_DEBUG("cmd=0x%02x write_len=%d data_len=%d", cmd, write_len, data_len);
jtagspi.c:218	LOG_DEBUG("%s", __func__);
jtagspi.c:366	LOG_DEBUG("%s", __func__);
jtagspi.c:417	LOG_DEBUG("%s", __func__);
jtagspi.c:523	LOG_DEBUG("status=0x%02" PRIx32, *status);
jtagspi.c:542	LOG_DEBUG("waited %" PRId64 " ms", dt);
jtagspi.c:630	LOG_DEBUG("erase from sector %u to sector %u", first, last);
jtagspi.c:652	LOG_DEBUG("Trying bulk erase.");
jtagspi.c:715	LOG_DEBUG("read page at 0x%08" PRIx32, offset);
jtagspi.c:768	LOG_DEBUG("wrote page at 0x%08" PRIx32, offset);
kinetis.c:430	LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
kinetis.c:434	LOG_DEBUG("MDM: failed to get AP");
kinetis.c:440	LOG_DEBUG("MDM: failed to queue a write request");
kinetis.c:448	LOG_DEBUG("MDM: dap_run failed");
kinetis.c:460	LOG_DEBUG("MDM: failed to get AP");
kinetis.c:466	LOG_DEBUG("MDM: failed to queue a read request");
kinetis.c:474	LOG_DEBUG("MDM: dap_run failed");
kinetis.c:478	LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
kinetis.c:497	LOG_DEBUG("MDM: polling timed out");
kinetis.c:531	LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
kinetis.c:548	LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
kinetis.c:841	LOG_DEBUG("MDM: dap_run failed when validating secured state");
kinetis.c:1557	LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
kinetis.c:1741	LOG_DEBUG("Generated FCF written");
kinetis.c:1827	LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
kinetis.c:1834	LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
kinetis.c:1899	LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
kinetis.c:1945	LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
kinetis.c:2723	LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
kinetis.c:2938	LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
kinetis.c:2973	LOG_DEBUG("FlexNVM bank %u limited to 0x%08" PRIx32 " due to active EEPROM backup",
kinetis.c:2978	LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
kinetis.c:3120	LOG_DEBUG("Ignoring error on PFlash sector blank-check");
kinetis_ke.c:139	LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
kinetis_ke.c:143	LOG_DEBUG("MDM: failed to get AP");
kinetis_ke.c:149	LOG_DEBUG("MDM: failed to queue a write request");
kinetis_ke.c:157	LOG_DEBUG("MDM: dap_run failed");
kinetis_ke.c:168	LOG_DEBUG("MDM: failed to get AP");
kinetis_ke.c:174	LOG_DEBUG("MDM: failed to queue a read request");
kinetis_ke.c:182	LOG_DEBUG("MDM: dap_run failed");
kinetis_ke.c:186	LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
kinetis_ke.c:204	LOG_DEBUG("MDM: polling timed out");
kinetis_ke.c:1197	LOG_DEBUG("Ignoring error on PFlash sector blank-check");
kitprog.c:336	LOG_DEBUG("HID write returned %i", ret);
kitprog.c:424	LOG_DEBUG("Zero bytes transferred");
kitprog.c:429	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:452	LOG_DEBUG("Zero bytes transferred");
kitprog.c:457	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:476	LOG_DEBUG("Zero bytes transferred");
kitprog.c:481	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:501	LOG_DEBUG("Zero bytes transferred");
kitprog.c:506	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:525	LOG_DEBUG("Zero bytes transferred");
kitprog.c:530	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:549	LOG_DEBUG("Zero bytes transferred");
kitprog.c:554	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:573	LOG_DEBUG("Zero bytes transferred");
kitprog.c:578	LOG_DEBUG("Programmer did not respond OK");
kitprog.c:608	LOG_DEBUG("Acquisition function failed for device 0x%02x.", devices[j]);
kitprog.c:651	LOG_DEBUG("JTAG to SWD");
kitprog.c:656	LOG_DEBUG("JTAG to SWD not supported");
kitprog.c:661	LOG_DEBUG("SWD line reset");
kitprog.c:686	LOG_DEBUG("Skipping due to previous errors: %d", queued_retval);
kitprog.c:712	LOG_DEBUG("refusing to enable sticky overrun detection");
kitprog.c:783	LOG_DEBUG("SWD ack not OK: %d %s", i,
lakemont.c:280	LOG_DEBUG("dr in 0x%02" PRIx8, *in);
lakemont.c:335	LOG_DEBUG("reg=%s, value=0x%08" PRIx32, reg->name,
lakemont.c:345	LOG_DEBUG("reg=%s, newval=0x%08" PRIx32, reg->name, value);
lakemont.c:439	LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
lakemont.c:441	LOG_DEBUG("core already in probemode");
lakemont.c:453	LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
lakemont.c:466	LOG_DEBUG("TS before PM exit = 0x%08" PRIx32, tapstatus);
lakemont.c:487	LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSB].name, PM_DSB);
lakemont.c:490	LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSL].name, PM_DSL);
lakemont.c:493	LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR);
lakemont.c:496	LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSB].name, PM_DSB);
lakemont.c:499	LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSL].name, PM_DSL);
lakemont.c:502	LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7);
lakemont.c:510	LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags,
lakemont.c:517	LOG_DEBUG("EFLAGS now = 0x%08" PRIx32 ", VM86 = %d, IF = %d",
lakemont.c:528	LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
lakemont.c:534	LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
lakemont.c:539	LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0);
lakemont.c:544	LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:552	LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:612	LOG_DEBUG("read_all_core_hw_regs read %u registers ok", i);
lakemont.c:631	LOG_DEBUG("write_all_core_hw_regs wrote %u registers ok", i);
lakemont.c:662	LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
lakemont.c:680	LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
lakemont.c:779	LOG_DEBUG("reg %s op=0x%016" PRIx64, regs[num].name, regs[num].op);
lakemont.c:790	LOG_DEBUG("%s op=0x%016" PRIx64, instructions[num].name,
lakemont.c:875	LOG_DEBUG("redirect to PM, tapstatus=0x%08" PRIx32, get_tapstatus(t));
lakemont.c:1055	LOG_DEBUG("modifying PMCR = 0x%08" PRIx32 " and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
lakemont.c:1059	LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
lakemont.c:1117	LOG_DEBUG("issuing port 0xcf9 reset");
lakemont.c:1171	LOG_DEBUG(" ");
lakemont.c:1174	LOG_DEBUG("target must be halted first");
lakemont.c:1212	LOG_DEBUG(" ");
libusb_helper.c:113	LOG_DEBUG("Device serial number '%s' doesn't match requested serial '%s'",
libusb_helper.c:141	LOG_DEBUG("Device alternate serial number '%s' doesn't match requested serial '%s'",
libusb_helper.c:342	LOG_DEBUG("usb ep %s %02x",
libusb_helper.c:351	LOG_DEBUG("Claiming interface %d", (int)interdesc->bInterfaceNumber);
log.c:408	LOG_DEBUG("keep_alive() was not invoked in the "
log.h:150	LOG_DEBUG("[%s] " fmt_str, target_name(target), ##__VA_ARGS__)
lpc2000.c:839	LOG_DEBUG("IAP command = %i (0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32
lpc2000.c:1079	LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);
lpc2000.c:1086	LOG_DEBUG("Vector 0x%2.2x: 0x%8.8" PRIx32, i * 4, buf_get_u32(buffer + (i * 4), 0, 32));
lpc2000.c:1091	LOG_DEBUG("checksum: 0x%8.8" PRIx32, checksum);
lpc2000.c:1180	LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
lpc288x.c:104	LOG_DEBUG("Timedout!");
lpc2900.c:194	LOG_DEBUG("Timeout!");
lpc2900.c:1223	LOG_DEBUG("Skip secured sector %u",
lpc3180.c:120	LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
lpc3180.c:167	LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
lpc3180.c:1160	LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
lpc3180.c:1170	LOG_DEBUG("lpc3180_controller_ready count=%d",
lpc3180.c:1181	LOG_DEBUG("lpc3180_controller_ready count=%d",
lpc3180.c:1203	LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
lpc3180.c:1213	LOG_DEBUG("lpc3180_nand_ready count end=%d",
lpc3180.c:1224	LOG_DEBUG("lpc3180_nand_ready count end=%d",
lpc3180.c:1246	LOG_DEBUG("lpc3180_tc_ready count start=%d",
lpc3180.c:1256	LOG_DEBUG("lpc3180_tc_ready count=%d",
lpc32xx.c:170	LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
lpc32xx.c:213	LOG_DEBUG("no LPC32xx NAND flash controller selected, "
lpc32xx.c:955	LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
lpc32xx.c:975	LOG_DEBUG("lpc32xx_dma_ready count=%d",
lpc32xx.c:1009	LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
lpc32xx.c:1028	LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, "
lpc32xx.c:1439	LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32,
lpc32xx.c:1615	LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
lpc32xx.c:1629	LOG_DEBUG("lpc32xx_controller_ready count=%d",
lpc32xx.c:1644	LOG_DEBUG("lpc32xx_controller_ready count=%d",
lpc32xx.c:1668	LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
lpc32xx.c:1683	LOG_DEBUG("lpc32xx_nand_ready count end=%d",
lpc32xx.c:1698	LOG_DEBUG("lpc32xx_nand_ready count end=%d",
lpc32xx.c:1714	LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
lpc32xx.c:1726	LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
lpcspifi.c:133	LOG_DEBUG("Uninitializing LPC43xx SSP");
lpcspifi.c:164	LOG_DEBUG("Allocating working area for SPIFI init algorithm");
lpcspifi.c:178	LOG_DEBUG("Writing algorithm to working area at " TARGET_ADDR_FMT,
lpcspifi.c:207	LOG_DEBUG("Running SPIFI init algorithm");
lpcspifi.c:416	LOG_DEBUG("erase from sector %u to sector %u", first, last);
lpcspifi.c:444	LOG_DEBUG("Chip supports the bulk erase command."
lpcspifi.c:582	LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
lpcspifi.c:773	LOG_DEBUG("Getting ID");
ls1_sap.c:32	LOG_DEBUG("%s", __func__);
ls1_sap.c:38	LOG_DEBUG("%s", __func__);
ls1_sap.c:54	LOG_DEBUG("%s", __func__);
ls1_sap.c:61	LOG_DEBUG("%s", __func__);
ls1_sap.c:68	LOG_DEBUG("%s", __func__);
ls1_sap.c:76	LOG_DEBUG("%s", __func__);
ls1_sap.c:84	LOG_DEBUG("%s", __func__);
ls1_sap.c:175	LOG_DEBUG("Reading memory at physical address 0x%" TARGET_PRIxADDR
ls1_sap.c:197	LOG_DEBUG("Writing memory at physical address 0x%" TARGET_PRIxADDR
max32xxx.c:369	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
max32xxx.c:374	LOG_DEBUG("no working area for block memory writes");
max32xxx.c:391	LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
max32xxx.c:444	LOG_DEBUG("bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
max32xxx.c:477	LOG_DEBUG("writing flash word-at-a-time");
max32xxx.c:531	LOG_DEBUG("Writing @ 0x%08" PRIx32, address);
max32xxx.c:658	LOG_DEBUG("arm_pid = 0x%x", arm_pid);
max32xxx.c:663	LOG_DEBUG("max326xx_id = 0x%" PRIx32, max326xx_id);
max32xxx.c:668	LOG_DEBUG("info->max326xx = %d", info->max326xx);
mem_ap.c:61	LOG_DEBUG("%s", __func__);
mem_ap.c:71	LOG_DEBUG("%s", __func__);
mem_ap.c:83	LOG_DEBUG("%s", __func__);
mem_ap.c:99	LOG_DEBUG("%s", __func__);
mem_ap.c:109	LOG_DEBUG("%s", __func__);
mem_ap.c:118	LOG_DEBUG("%s", __func__);
mem_ap.c:130	LOG_DEBUG("%s", __func__);
mem_ap.c:166	LOG_DEBUG("%s", __func__);
mem_ap.c:241	LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
mem_ap.c:256	LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
mips32.c:358	LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
mips32.c:398	LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
mips32.c:588	LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
mips32.c:607	LOG_DEBUG("Running algorithm");
mips32.c:697	LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
mips32.c:831	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
mips32.c:1024	LOG_DEBUG("CPU: %s (PRId %08x)", entry->cpu_name, mips32->prid);
mips32.c:1146	LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
mips32_pracc.c:86	LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
mips32_pracc.c:178	LOG_DEBUG("restarting code");
mips32_pracc.c:189	LOG_DEBUG("unexpected write at address %" PRIx32, ejtag_info->pa_addr);
mips32_pracc.c:199	LOG_DEBUG("writing at unexpected address %" PRIx32, ejtag_info->pa_addr);
mips32_pracc.c:218	LOG_DEBUG("reading at unexpected address %" PRIx32 ", expected %x",
mips32_pracc.c:224	LOG_DEBUG("restarting, without clean jump");
mips32_pracc.c:255	LOG_DEBUG("unexpected second pass through pracc text");
mips32_pracc.c:260	LOG_DEBUG("unexpected read address in final check: %"
mips32_pracc.c:268	LOG_DEBUG("failed to jump back to pracc text");
mips32_pracc.c:273	LOG_DEBUG("execution abandoned, store pending: %d", store_pending);
mips32_pracc.c:291	LOG_DEBUG("warning: store access pass pracc text");
mips32_pracc.c:682	LOG_DEBUG("clsiz must be power of 2");
mips32_pracc.c:848	LOG_DEBUG("Unsupported MIPS Release ( > 5)");
mips32_pracc.c:1210	LOG_DEBUG("Unsupported MIPS Release ( > 5)");
mips32_pracc.c:1276	LOG_DEBUG("%s using 0x%.8" TARGET_PRIxADDR " for write handler", __func__, source->address);
mips64.c:286	LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
mips64.c:583	LOG_DEBUG("DCR 0x%" PRIx64 " numinst %i numdata %i", dcr,
mips64_pracc.c:55	LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n");
mips64_pracc.c:89	LOG_DEBUG("Reading %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:101	LOG_DEBUG("Reading %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:111	LOG_DEBUG("Running commands %" PRIx64 " at %" PRIx64, data,
mips64_pracc.c:123	LOG_DEBUG("Reading %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:178	LOG_DEBUG("Writing %" PRIx64 " at %" PRIx64, data, address);
mips64_pracc.c:225	LOG_DEBUG("%08" PRIx32, code[i]);
mips64_pracc.c:240	LOG_DEBUG("ERROR wait_for_pracc_rw");
mips64_pracc.c:251	LOG_DEBUG("-> %08" PRIx32, address32);
mips64_pracc.c:295	LOG_DEBUG("@MIPS64_PRACC_TEXT, address_prev=%" PRIx64, address_prev);
mips64_pracc.c:351	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:409	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:469	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:529	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:609	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:671	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:731	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:792	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:1032	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:1258	LOG_DEBUG("enter mips64_pracc_exec");
mips64_pracc.c:1351	LOG_DEBUG("%s using " TARGET_ADDR_FMT " for write handler", __func__,
mips64_pracc.c:1353	LOG_DEBUG("daddiu: %08" PRIx32, handler_code[11]);
mips64_pracc.c:1373	LOG_DEBUG("start: " TARGET_ADDR_FMT, val);
mips64_pracc.c:1383	LOG_DEBUG("stop: " TARGET_ADDR_FMT, val);
mips64_pracc.c:1391	LOG_DEBUG("num_clocks=%d", num_clocks);
mips_ejtag.c:248	LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
mips_ejtag.c:314	LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
mips_ejtag.c:323	LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
mips_ejtag.c:330	LOG_DEBUG("EJTAG v2.6: features:%s%s",
mips_ejtag.c:337	LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
mips_ejtag.c:373	LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
mips_ejtag.c:376	LOG_DEBUG("EJTAG: Version 2.5 Detected");
mips_ejtag.c:379	LOG_DEBUG("EJTAG: Version 2.6 Detected");
mips_ejtag.c:382	LOG_DEBUG("EJTAG: Version 3.1 Detected");
mips_ejtag.c:385	LOG_DEBUG("EJTAG: Version 4.1 Detected");
mips_ejtag.c:388	LOG_DEBUG("EJTAG: Version 5.1 Detected");
mips_ejtag.c:391	LOG_DEBUG("EJTAG: Unknown Version Detected");
mips_ejtag.c:397	LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
mips_ejtag.c:515	LOG_DEBUG("enter mips64_pracc_exec");
mips_m4k.c:114	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
mips_m4k.c:203	LOG_DEBUG("Reset Detected");
mips_m4k.c:211	LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
mips_m4k.c:260	LOG_DEBUG("target->state: %s", target_state_name(target));
mips_m4k.c:263	LOG_DEBUG("target was already halted");
mips_m4k.c:304	LOG_DEBUG("target->state: %s",
mips_m4k.c:340	LOG_DEBUG("Using MTAP reset to reset processor...");
mips_m4k.c:352	LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_m4k.c:374	LOG_DEBUG("target->state: %s", target_state_name(target));
mips_m4k.c:466	LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
mips_m4k.c:487	LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
mips_m4k.c:491	LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
mips_m4k.c:572	LOG_DEBUG("target stepped ");
mips_m4k.c:639	LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
mips_m4k.c:643	LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
mips_m4k.c:743	LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
mips_m4k.c:747	LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
mips_m4k.c:760	LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
mips_m4k.c:929	LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
mips_m4k.c:949	LOG_DEBUG("Invalid FP Comparator number in watchpoint");
mips_m4k.c:1013	LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1078	LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1183	LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
mips_m4k.c:1205	LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1271	LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:64	LOG_DEBUG("entered debug state at PC 0x%" PRIx64 ", target->state: %s",
mips_mips64.c:90	LOG_DEBUG("Reset Detected");
mips_mips64.c:121	LOG_DEBUG("target->state: %s",
mips_mips64.c:125	LOG_DEBUG("target was already halted");
mips_mips64.c:160	LOG_DEBUG("target->state: %s",
mips_mips64.c:199	LOG_DEBUG("target->state: %s",
mips_mips64.c:244	LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %" PRIu32 ")",
mips_mips64.c:271	LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx64, bp->unique_id,
mips_mips64.c:351	LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
mips_mips64.c:476	LOG_DEBUG("wp_num %i bp_value 0x%" PRIx64 "", wp_num, c->bp_value);
mips_mips64.c:507	LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
mips_mips64.c:512	LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d", bp->unique_id, bp_num);
mips_mips64.c:572	LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
mips_mips64.c:645	LOG_DEBUG("unset breakpoint at 0x%16.16" PRIx64 "",
mips_mips64.c:685	LOG_DEBUG("target resumed at 0x%" PRIx64 "", resume_pc);
mips_mips64.c:693	LOG_DEBUG("target debug resumed at 0x%" PRIx64 "", resume_pc);
mips_mips64.c:770	LOG_DEBUG("target stepped ");
mips_mips64.c:834	LOG_DEBUG("Invalid FP Comparator number in watchpoint");
mips_mips64.c:914	LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:952	LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:1069	LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mpsse.c:427	LOG_DEBUG("-");
mpsse.c:708	LOG_DEBUG("%s", enable ? "on" : "off");
mpsse.c:714	LOG_DEBUG("%d", divisor);
mpsse.c:734	LOG_DEBUG("%s", enable ? "on" : "off");
mpsse.c:745	LOG_DEBUG("%s", enable ? "on" : "off");
mpsse.c:753	LOG_DEBUG("target %d Hz", frequency);
mpsse.c:777	LOG_DEBUG("actually %d Hz", frequency);
mrvlqspi.c:150	LOG_DEBUG("status: 0x%08" PRIx32, regval);
mrvlqspi.c:205	LOG_DEBUG("status: 0x%08" PRIx32, regval);
mrvlqspi.c:234	LOG_DEBUG("status: 0x%08" PRIx32, regval);
mrvlqspi.c:275	LOG_DEBUG("status: 0x%08" PRIX32, val);
mrvlqspi.c:299	LOG_DEBUG("status: 0x%08" PRIx32, val);
mrvlqspi.c:407	LOG_DEBUG("Getting ID");
mrvlqspi.c:444	LOG_DEBUG("ID is 0x%02" PRIx8 " 0x%02" PRIx8 " 0x%02" PRIx8,
mrvlqspi.c:526	LOG_DEBUG("erase from sector %u to sector %u", first, last);
mrvlqspi.c:555	LOG_DEBUG("Chip supports the bulk erase command."
mrvlqspi.c:590	LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
mx3.c:409	LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
mx3.c:672	LOG_DEBUG("main area read with 1 (correctable) error");
mx3.c:675	LOG_DEBUG("main area read with more than 1 (incorrectable) error");
mx3.c:680	LOG_DEBUG("spare area read with 1 (correctable) error");
mx3.c:683	LOG_DEBUG("main area read with more than 1 (incorrectable) error");
mxc.c:132	LOG_DEBUG("BI-swap enabled");
mxc.c:241	LOG_DEBUG("MXC_NF : bus is 16-bit width");
mxc.c:243	LOG_DEBUG("MXC_NF : bus is 8-bit width");
mxc.c:255	LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
mxc.c:497	LOG_DEBUG("part of spare block will be overridden "
mxc.c:709	LOG_DEBUG("MXC_NF : work in Big Endian mode");
mxc.c:712	LOG_DEBUG("MXC_NF : work in Little Endian mode");
mxc.c:714	LOG_DEBUG("MXC_NF : work with ECC mode");
mxc.c:717	LOG_DEBUG("MXC_NF : work without ECC mode");
nrf5.c:401	LOG_DEBUG("Timed out waiting for NVMC_READY");
nrf5.c:721	LOG_DEBUG("Couldn't read FICR INFO.PART register");
nrf5.c:755	LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
nrf5.c:774	LOG_DEBUG("Invalid FICR INFO PART value 0x%08"
nrf5.c:813	LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
nrf5.c:818	LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
nrf5.c:826	LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
nrf5.c:830	LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
nrf5.c:916	LOG_DEBUG("Couldn't read some of FICR INFO registers");
nrf5.c:933	LOG_DEBUG("Couldn't read FICR CONFIGID register, using FICR INFO");
nrf5.c:1070	LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
nrf5.c:1143	LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
numicro.c:548	LOG_DEBUG("NuMicro arm architecture: armv7m\n");
numicro.c:552	LOG_DEBUG("NuMicro arm architecture: armv6m\n");
numicro.c:570	LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected);
numicro.c:589	LOG_DEBUG("protection removed");
numicro.c:591	LOG_DEBUG("still protected!!");
numicro.c:669	LOG_DEBUG("timed out waiting for flash");
numicro.c:831	LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]);
numicro.c:879	LOG_DEBUG("erasing sector %u at address " TARGET_ADDR_FMT, i, bank->base + bank->sectors[i].offset);
numicro.c:900	LOG_DEBUG("timed out waiting for flash");
numicro.c:911	LOG_DEBUG("failure: 0x%" PRIx32 "", status);
numicro.c:920	LOG_DEBUG("Erase done.");
numicro.c:996	LOG_DEBUG("timed out waiting for flash");
numicro.c:1010	LOG_DEBUG("failure: 0x%" PRIx32 "", status);
numicro.c:1018	LOG_DEBUG("Write OK");
numicro.c:1022	LOG_DEBUG("Write done.");
numicro.c:1103	LOG_DEBUG("Nuvoton NuMicro: Probed ...");
numicro.c:1126	LOG_DEBUG("add flash_bank numicro %s", bank->name);
nuttx.c:216	LOG_DEBUG("Hash table size (g_npidhash) = %" PRId32, npidhash);
nuttx.c:224	LOG_DEBUG("Hash table address (g_pidhash) = %" PRIx32, pidhashaddr);
opendous.c:491	LOG_DEBUG("trst: %i, srst: %i", trst, srst);
openocd.c:133	LOG_DEBUG("Debug Adapter init complete");
openocd.c:150	LOG_DEBUG("Examining targets...");
openocd.c:152	LOG_DEBUG("target examination failed");
openocd.c:238	LOG_DEBUG("log_init: complete");
openocd.c:268	LOG_DEBUG("command registration: complete");
options.c:122	LOG_DEBUG("BINDIR = %s", BINDIR);
options.c:234	LOG_DEBUG("bindir=%s", BINDIR);
options.c:235	LOG_DEBUG("pkgdatadir=%s", PKGDATADIR);
options.c:236	LOG_DEBUG("exepath=%s", exepath);
options.c:237	LOG_DEBUG("bin2data=%s", bin2data);
options.c:355	LOG_DEBUG("ARGV[%d] = \"%s\"", i, argv[i]);
or1k.c:246	LOG_DEBUG("-");
or1k.c:311	LOG_DEBUG("-");
or1k.c:322	LOG_DEBUG("-");
or1k.c:336	LOG_DEBUG("-");
or1k.c:370	LOG_DEBUG("-");
or1k.c:407	LOG_DEBUG("-");
or1k.c:415	LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num, reg_value);
or1k.c:427	LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num, reg_value);
or1k.c:437	LOG_DEBUG("-");
or1k.c:444	LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num, reg_value);
or1k.c:456	LOG_DEBUG("-");
or1k.c:472	LOG_DEBUG("-");
or1k.c:509	LOG_DEBUG("-");
or1k.c:546	LOG_DEBUG("-");
or1k.c:570	LOG_DEBUG("target->state: %s",
or1k.c:574	LOG_DEBUG("Target was already halted");
or1k.c:714	LOG_DEBUG("-");
or1k.c:730	LOG_DEBUG("-");
or1k.c:746	LOG_DEBUG("-");
or1k.c:769	LOG_DEBUG("-");
or1k.c:788	LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
or1k.c:853	LOG_DEBUG("Unset breakpoint at 0x%08" TARGET_PRIxADDR, breakpoint->address);
or1k.c:878	LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
or1k.c:882	LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
or1k.c:915	LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, id: %" PRIu32,
or1k.c:973	LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, id: %" PRIu32,
or1k.c:1026	LOG_DEBUG("Read memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
or1k.c:1053	LOG_DEBUG("Write memory at 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
or1k.c:1140	LOG_DEBUG("Target is halted");
or1k.c:1357	LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
or1k_du_adv.c:183	LOG_DEBUG("Init done");
or1k_du_adv.c:202	LOG_DEBUG("Select module: %s", chain_name[chain]);
or1k_du_adv.c:285	LOG_DEBUG("Write control register %" PRId8 ": 0x%08" PRIx32, regidx, cmd_data[0]);
or1k_du_adv.c:421	LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32,
or1k_du_adv.c:518	LOG_DEBUG("CRC OK!");
or1k_du_adv.c:575	LOG_DEBUG("Doing burst write, word size %d, word count %d,"
or1k_du_adv.c:588	LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
or1k_du_adv.c:597	LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
or1k_du_adv.c:606	LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
or1k_du_adv.c:662	LOG_DEBUG("CRC OK!\n");
or1k_du_adv.c:839	LOG_DEBUG("Reading WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
or1k_du_adv.c:894	LOG_DEBUG("Writing WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
or1k_du_adv.c:965	LOG_DEBUG("JSP transfer");
or1k_tap_mohor.c:21	LOG_DEBUG("Initialising OpenCores JTAG TAP");
or1k_tap_vjtag.c:80	LOG_DEBUG("Initialising Altera Virtual JTAG TAP");
or1k_tap_vjtag.c:205	LOG_DEBUG("SLD HUB Configuration register");
or1k_tap_vjtag.c:206	LOG_DEBUG("------------------------------");
or1k_tap_vjtag.c:207	LOG_DEBUG("m_width = %d", m_width);
or1k_tap_vjtag.c:208	LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(hub_info));
or1k_tap_vjtag.c:209	LOG_DEBUG("nb_of_node = %d", nb_nodes);
or1k_tap_vjtag.c:210	LOG_DEBUG("version = %" PRIu32, VER(hub_info));
or1k_tap_vjtag.c:211	LOG_DEBUG("VIR length = %d", guess_addr_width(nb_nodes) + m_width);
or1k_tap_vjtag.c:247	LOG_DEBUG("Node info register");
or1k_tap_vjtag.c:248	LOG_DEBUG("--------------------");
or1k_tap_vjtag.c:249	LOG_DEBUG("instance_id = %" PRIu32, ID(node_info));
or1k_tap_vjtag.c:250	LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(node_info));
or1k_tap_vjtag.c:251	LOG_DEBUG("node_id = %" PRIu32 " (%s)", ID(node_info),
or1k_tap_vjtag.c:253	LOG_DEBUG("version = %" PRIu32, VER(node_info));
or1k_tap_xilinx_bscan.c:21	LOG_DEBUG("Initialising Xilinx Internal JTAG TAP");
osbdm.c:669	LOG_DEBUG("OSBDM init");
pic32mm.c:235	LOG_DEBUG("status: 0x%" PRIx32, status);
pic32mm.c:239	LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
pic32mm.c:398	LOG_DEBUG("Erasing entire program flash");
pic32mm.c:1040	LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
pic32mx.c:225	LOG_DEBUG("status: 0x%" PRIx32, status);
pic32mx.c:229	LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
pic32mx.c:327	LOG_DEBUG("Erasing entire program flash");
pic32mx.c:610	LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
pic32mx.c:903	LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
picoprobe.c:363	LOG_DEBUG("Add %d idle cycles", ap_delay_clk);
picoprobe.c:444	LOG_DEBUG("JTAG-to-SWD");
picoprobe.c:448	LOG_DEBUG("SWD-to-JTAG");
picoprobe.c:452	LOG_DEBUG("DORMANT-to-SWD");
picoprobe.c:456	LOG_DEBUG("SWD-to-DORMANT");
pld.c:337	LOG_DEBUG("Initializing PLDs...");
program.c:35	LOG_DEBUG("debug_buffer[%02x] = DASM(0x%08x)", i, program->debug_buffer[i]);
program.c:51	LOG_DEBUG("Saving register %d as used by program", (int)i);
program.c:70	LOG_DEBUG("Unable to execute program %p", p);
psoc4.c:252	LOG_DEBUG("no working area for sysreq code");
psoc4.c:268	LOG_DEBUG("SYSREQ %02" PRIx8 " %04" PRIx16 " %08" PRIx32 " size %" PRIu32,
psoc4.c:295	LOG_DEBUG("SYSREQ %02" PRIx8 " %04" PRIx16 " %08" PRIx32,
psoc4.c:661	LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32 "",
psoc4.c:772	LOG_DEBUG("SPCIF geometry: %" PRIu32 " KiB flash, row %" PRIu32 " bytes.",
psoc4.c:816	LOG_DEBUG("flash bank set %" PRIu32 " rows", num_rows);
psoc5lp.c:256	LOG_DEBUG("PANTHER_DEVICE_ID = 0x%08" PRIX32, device_id);
psoc5lp.c:870	LOG_DEBUG("Get_Temp: sign 0x%02" PRIx8 ", magnitude 0x%02" PRIx8,
psoc5lp.c:895	LOG_DEBUG("Padding %" PRIu32 " bytes", EEPROM_ROW_SIZE - byte_count);
psoc5lp.c:1033	LOG_DEBUG("Skipping duplicate erase of sectors %u to %u",
psoc5lp.c:1152	LOG_DEBUG("Get_Temp: sign 0x%02" PRIx8 ", magnitude 0x%02" PRIx8,
psoc5lp.c:1188	LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT,
psoc5lp.c:1211	LOG_DEBUG("Padding %d bytes", ROW_SIZE - len);
psoc5lp.c:1345	LOG_DEBUG("row[%u][%02u] = 0x%02" PRIx8, i, k, row_data[k]);
psoc5lp.c:1434	LOG_DEBUG("NVL[%d] = 0x%02" PRIx8, 3, nvl[3]);
psoc6.c:644	LOG_DEBUG("Erasing SECTOR @%08" PRIX32, addr);
psoc6.c:673	LOG_DEBUG("Erasing ROW @%08" PRIX32, addr);
psoc6.c:772	LOG_DEBUG("Programming ROW @%08" PRIX32, addr);
qn908x.c:246	LOG_DEBUG("Error reading reg at " TARGET_ADDR_FMT
qn908x.c:254	LOG_DEBUG("Error writing reg at " TARGET_ADDR_FMT " with 0x%08"
qn908x.c:259	LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08"
qn908x.c:262	LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32
qn908x.c:291	LOG_DEBUG("LOCK_STAT_%d = 0x%08" PRIx32, i, lock_stat);
qn908x.c:307	LOG_DEBUG("Clock clk_sel=0x%08" PRIu32, clk_sel);
qn908x.c:338	LOG_DEBUG("Core freq: %" PRIu32 " Hz \| AHB freq: %" PRIu32 " Hz",
qn908x.c:409	LOG_DEBUG("Flash protection = 0x%02" PRIx8,
qn908x.c:547	LOG_DEBUG("Erasing page %" PRIu32 " of block %" PRIu32,
qn908x.c:646	LOG_DEBUG("protect set=%d bits[%d] with mask=0x%02x", set, i, mask);
qn908x.c:691	LOG_DEBUG("computed image checksum: 0x%8.8" PRIx32, checksum);
qn908x.c:713	LOG_DEBUG("Code Read Protection = 0x%08" PRIx32, crp);
qn908x.c:920	LOG_DEBUG("auto_probe");
qn908x.c:1062	LOG_DEBUG("LOCK_STAT_8 before erasing: 0x%" PRIx32, lock_stat_8);
qn908x.c:1083	LOG_DEBUG("Erasing both blocks with command 0x%" PRIx32, erase_cmd);
renesas_rpchf.c:616	LOG_DEBUG("reading buffer of %" PRIu32 " byte at 0x%8.8" PRIx32,
riscv-011.c:307	LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
riscv-011.c:334	LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
riscv-011.c:343	LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
riscv-011.c:354	LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
riscv-011.c:772	LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
riscv-011.c:775	LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
riscv-011.c:864	LOG_DEBUG("enter");
riscv-011.c:986	LOG_DEBUG("exit");
riscv-011.c:1046	LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
riscv-011.c:1061	LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
riscv-011.c:1114	LOG_DEBUG("step=%d", step);
riscv-011.c:1213	LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
riscv-011.c:1221	LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
riscv-011.c:1265	LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
riscv-011.c:1392	LOG_DEBUG("riscv_halt()");
riscv-011.c:1410	LOG_DEBUG("riscv_deinit_target()");
riscv-011.c:1421	LOG_DEBUG("enter");
riscv-011.c:1473	LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
riscv-011.c:1474	LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
riscv-011.c:1475	LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
riscv-011.c:1476	LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
riscv-011.c:1500	LOG_DEBUG("dminfo: 0x%08x", dminfo);
riscv-011.c:1501	LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
riscv-011.c:1502	LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
riscv-011.c:1503	LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
riscv-011.c:1504	LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
riscv-011.c:1505	LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
riscv-011.c:1506	LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
riscv-011.c:1507	LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
riscv-011.c:1508	LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
riscv-011.c:1509	LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
riscv-011.c:1510	LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
riscv-011.c:1511	LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
riscv-011.c:1512	LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
riscv-011.c:1569	LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
riscv-011.c:1913	LOG_DEBUG("debug running");
riscv-011.c:1919	LOG_DEBUG("halting");
riscv-011.c:2092	LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
riscv-011.c:2172	LOG_DEBUG("t0 is 0x%" PRIx64, t0);
riscv-011.c:2374	LOG_DEBUG("init");
riscv-013.c:251	LOG_DEBUG("[%d] Allocating new DM", target->coreid);
riscv-013.c:445	LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
riscv-013.c:454	LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
riscv-013.c:715	LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
riscv-013.c:778	LOG_DEBUG("command=0x%x; access register, size=%d, postexec=%d, "
riscv-013.c:788	LOG_DEBUG("command=0x%x", command);
riscv-013.c:801	LOG_DEBUG("command 0x%x failed; abstractcs=0x%x", command, abstractcs);
riscv-013.c:1299	LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target),
riscv-013.c:1488	LOG_DEBUG("{%d} %s = 0x%" PRIx64, riscv_current_hartid(target),
riscv-013.c:1522	LOG_DEBUG("riscv_deinit_target()");
riscv-013.c:1567	LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
riscv-013.c:1568	LOG_DEBUG(" dmireset=%d", get_field(dtmcontrol, DTM_DTMCS_DMIRESET));
riscv-013.c:1569	LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTM_DTMCS_IDLE));
riscv-013.c:1570	LOG_DEBUG(" dmistat=%d", get_field(dtmcontrol, DTM_DTMCS_DMISTAT));
riscv-013.c:1571	LOG_DEBUG(" abits=%d", get_field(dtmcontrol, DTM_DTMCS_ABITS));
riscv-013.c:1572	LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTM_DTMCS_VERSION));
riscv-013.c:1617	LOG_DEBUG("dmstatus: 0x%08x", dmstatus);
riscv-013.c:1633	LOG_DEBUG("hartsellen=%d", info->hartsellen);
riscv-013.c:1702	LOG_DEBUG("Detected %d harts.", dm->hart_count);
riscv-013.c:1752	LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen,
riscv-013.c:2277	LOG_DEBUG("init");
riscv-013.c:2417	LOG_DEBUG("Waiting for hart %d to come out of reset.", index);
riscv-013.c:2472	LOG_DEBUG("Unable to execute pre-fence");
riscv-013.c:2502	LOG_DEBUG(fmt, value);
riscv-013.c:2596	LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
riscv-013.c:2618	LOG_DEBUG("\r\nread_memory: sab: access: 0x%08x", access);
riscv-013.c:2624	LOG_DEBUG("\r\nread_memory: sab: value: 0x%08x", value);
riscv-013.c:2633	LOG_DEBUG("reading block until final address 0x%" PRIx64, fin_addr);
riscv-013.c:2644	LOG_DEBUG("\r\naccess: 0x%08x", access);
riscv-013.c:2648	LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08"
riscv-013.c:2843	LOG_DEBUG("%s", msg);
riscv-013.c:2852	LOG_DEBUG("Skipping mem %s via progbuf - insufficient progbuf size.",
riscv-013.c:2858	LOG_DEBUG("Skipping mem %s via progbuf - target not halted.",
riscv-013.c:2864	LOG_DEBUG("Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
riscv-013.c:2870	LOG_DEBUG("Skipping mem %s via progbuf - unsupported size.",
riscv-013.c:2876	LOG_DEBUG("Skipping mem %s via progbuf - progbuf only supports %u-bit address.",
riscv-013.c:2892	LOG_DEBUG("Skipping mem %s via system bus - unsupported size.",
riscv-013.c:2899	LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.",
riscv-013.c:2905	LOG_DEBUG("Skipping mem read via system bus - "
riscv-013.c:2922	LOG_DEBUG("Skipping mem %s via abstract access - unsupported size: %d bits",
riscv-013.c:2928	LOG_DEBUG("Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
riscv-013.c:2956	LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
riscv-013.c:2990	LOG_DEBUG("aampostincrement is supported on this target.");
riscv-013.c:3001	LOG_DEBUG("aampostincrement is not supported on this target.");
riscv-013.c:3034	LOG_DEBUG("writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
riscv-013.c:3073	LOG_DEBUG("aampostincrement is supported on this target.");
riscv-013.c:3084	LOG_DEBUG("aampostincrement is not supported on this target.");
riscv-013.c:3151	LOG_DEBUG("i=%d, count=%d, read_addr=0x%" PRIx64, index, count, read_addr);
riscv-013.c:3193	LOG_DEBUG("successful (partial?) memory read");
riscv-013.c:3197	LOG_DEBUG("memory read resulted in busy response");
riscv-013.c:3250	LOG_DEBUG("error when reading memory, abstractcs=0x%08lx", (long)abstractcs);
riscv-013.c:3263	LOG_DEBUG("index=%d, reads=%d, next_index=%d, ignore_last=%d, j=%d",
riscv-013.c:3427	LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
riscv-013.c:3510	LOG_DEBUG("error reading single word of %d bytes from 0x%" TARGET_PRIxADDR,
riscv-013.c:3600	LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
riscv-013.c:3616	LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
riscv-013.c:3617	LOG_DEBUG("\r\nwrite_memory:SAB: ONE OFF: value 0x%08" PRIx64, value);
riscv-013.c:3627	LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access);
riscv-013.c:3638	LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
riscv-013.c:3664	LOG_DEBUG("transferring burst starting at address 0x%" TARGET_PRIxADDR,
riscv-013.c:3725	LOG_DEBUG("DMI busy encountered during system bus write.");
riscv-013.c:3742	LOG_DEBUG("Sbbusyerror encountered during system bus write.");
riscv-013.c:3755	LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
riscv-013.c:3771	LOG_DEBUG("System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")",
riscv-013.c:3776	LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR
riscv-013.c:3800	LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address);
riscv-013.c:3857	LOG_DEBUG("writing until final address 0x%016" PRIx64, fin_addr);
riscv-013.c:3859	LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64,
riscv-013.c:3940	LOG_DEBUG("successful (partial?) memory write");
riscv-013.c:3943	LOG_DEBUG("Memory write resulted in abstract command busy response.");
riscv-013.c:3945	LOG_DEBUG("Memory write resulted in DMI busy response.");
riscv-013.c:4070	LOG_DEBUG("[%s] reading register %s", target_name(target),
riscv-013.c:4080	LOG_DEBUG("[%d] read PC from DPC: 0x%" PRIx64, target->coreid, *value);
riscv-013.c:4099	LOG_DEBUG("[%d] writing 0x%" PRIx64 " to register %s",
riscv-013.c:4105	LOG_DEBUG("[%d] writing PC to DPC: 0x%" PRIx64, target->coreid, value);
riscv-013.c:4109	LOG_DEBUG("[%d] actual DPC written: 0x%016" PRIx64, target->coreid, actual_value);
riscv-013.c:4175	LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, r->prepped);
riscv-013.c:4214	LOG_DEBUG("halting hart %d", r->current_hartid);
riscv-013.c:4323	LOG_DEBUG("dcsr.cause: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
riscv-013.c:4333	LOG_DEBUG("{%d} halted because of trigger", target->coreid);
riscv-013.c:4359	LOG_DEBUG("cache hit for 0x%" PRIx32 " @%d", data, index);
riscv-013.c:4441	LOG_DEBUG("resuming hart %d (for step?=%d)", r->current_hartid, step);
riscv.c:372	LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
riscv.c:406	LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
riscv.c:432	LOG_DEBUG("riscv_create_target()");
riscv.c:445	LOG_DEBUG("riscv_init_target()");
riscv.c:491	LOG_DEBUG("riscv_deinit_target()");
riscv.c:572	LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
riscv.c:575	LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
riscv.c:622	LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
riscv.c:625	LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
riscv.c:674	LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
riscv.c:677	LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
riscv.c:724	LOG_DEBUG("trigger %d has unknown type %d", i, type);
riscv.c:731	LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
riscv.c:867	LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
riscv.c:930	LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
riscv.c:1004	LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
riscv.c:1027	LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
riscv.c:1036	LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
riscv.c:1048	LOG_DEBUG("Next byte is %x", buffer[i]);
riscv.c:1051	LOG_DEBUG("Full instruction is %x", instruction);
riscv.c:1065	LOG_DEBUG("%x is store instruction", instruction);
riscv.c:1068	LOG_DEBUG("%x is load instruction", instruction);
riscv.c:1075	LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
riscv.c:1077	LOG_DEBUG("%x is not a RV32I load or store", instruction);
riscv.c:1085	LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
riscv.c:1111	LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
riscv.c:1121	LOG_DEBUG("riscv_examine()");
riscv.c:1123	LOG_DEBUG("Target was already examined.");
riscv.c:1131	LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
riscv.c:1133	LOG_DEBUG(" version=0x%x", info->dtm_version);
riscv.c:1170	LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
riscv.c:1175	LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
riscv.c:1193	LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
riscv.c:1235	LOG_DEBUG("[%d] halting all harts", target->coreid);
riscv.c:1275	LOG_DEBUG("[%d]", target->coreid);
riscv.c:1283	LOG_DEBUG("[%d]", target->coreid);
riscv.c:1292	LOG_DEBUG("[%s] prep hart", target_name(target));
riscv.c:1299	LOG_DEBUG("[%s] hart requested resume, but was already resumed",
riscv.c:1303	LOG_DEBUG("[%s] mark as prepped", target_name(target));
riscv.c:1314	LOG_DEBUG("deal with triggers");
riscv.c:1344	LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set);
riscv.c:1382	LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
riscv.c:1402	LOG_DEBUG("[%d]", target->coreid);
riscv.c:1427	LOG_DEBUG("[%d] mark as prepped", target->coreid);
riscv.c:1474	LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
riscv.c:1546	LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
riscv.c:1553	LOG_DEBUG("Couldn't read SATP.");
riscv.c:1560	LOG_DEBUG("MMU is disabled.");
riscv.c:1563	LOG_DEBUG("MMU is enabled.");
riscv.c:1607	LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
riscv.c:1639	LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
riscv.c:1671	LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
riscv.c:1764	LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
riscv.c:1852	LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
riscv.c:1856	LOG_DEBUG("save %s", reg_params[i].reg_name);
riscv.c:1889	LOG_DEBUG("Disabling Interrupts");
riscv.c:1906	LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
riscv.c:1912	LOG_DEBUG("poll()");
riscv.c:1959	LOG_DEBUG("Restoring Interrupts");
riscv.c:1979	LOG_DEBUG("restore %s", reg_params[i].reg_name);
riscv.c:1999	LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
riscv.c:2072	LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
riscv.c:2091	LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
riscv.c:2097	LOG_DEBUG(" triggered a halt");
riscv.c:2101	LOG_DEBUG(" triggered running");
riscv.c:2132	LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
riscv.c:2143	LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
riscv.c:2186	LOG_DEBUG("polling all harts");
riscv.c:2237	LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
riscv.c:2244	LOG_DEBUG("halt all");
riscv.c:2247	LOG_DEBUG("resume all");
riscv.c:2274	LOG_DEBUG(" hart %d halted", halted_hart);
riscv.c:2306	LOG_DEBUG("stepping rtos hart");
riscv.c:3153	LOG_DEBUG("[%s] resuming hart", target_name(target));
riscv.c:3160	LOG_DEBUG("[%s] hart requested resume, but was already resumed",
riscv.c:3175	LOG_DEBUG("[%s] stepping", target_name(target));
riscv.c:3221	LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
riscv.c:3231	LOG_DEBUG("[%d]", target->coreid);
riscv.c:3311	LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
riscv.c:3329	LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
riscv.c:3343	LOG_DEBUG("[%s] %s does not exist.",
riscv.c:3350	LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
riscv.c:3367	LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
riscv.c:3462	LOG_DEBUG("[%s] Cannot access tselect register. "
riscv.c:3721	LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
riscv.c:3734	LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
riscv.c:3808	LOG_DEBUG("create register cache for %d registers",
riscv.c:4350	LOG_DEBUG("Exposing additional CSR %d (name=%s)",
riscv.c:4395	LOG_DEBUG("Exposing additional custom register %d (name=%s)",
riscv_semihosting.c:60	LOG_DEBUG(" -> NONE (!semihosting)");
riscv_semihosting.c:65	LOG_DEBUG(" -> NONE (!semihosting->is_active)");
riscv_semihosting.c:95	LOG_DEBUG("check %08x %08x %08x from 0x%" PRIx64 "-4", pre, ebreak, post, pc);
riscv_semihosting.c:99	LOG_DEBUG(" -> NONE (no magic)");
riscv_semihosting.c:114	LOG_DEBUG(" -> ERROR (couldn't read a0)");
riscv_semihosting.c:120	LOG_DEBUG(" -> ERROR (couldn't read a1)");
riscv_semihosting.c:139	LOG_DEBUG(" -> NONE (unknown operation number)");
riscv_semihosting.c:154	LOG_DEBUG(" -> HANDLED");
riscv_semihosting.c:158	LOG_DEBUG(" -> WAITING");
riscv_semihosting.c:171	LOG_DEBUG("[%s] enable=%d", target_name(target), enable);
riscv_semihosting.c:188	LOG_DEBUG("0x%" PRIx64, semihosting->result);
rlink.c:472	LOG_DEBUG("%d/%d", command_buffer_size, reply_buffer_size);
rlink.c:1471	LOG_DEBUG("Opened device, hdev = %p", hdev);
rlink.c:1485	LOG_DEBUG("interface claimed!");
rlink.c:1531	LOG_DEBUG(INTERFACE_NAME " firmware version: %d.%d.%d",
rp2040.c:124	LOG_DEBUG("Set %s = 0x%" PRIx32, args[i].reg_name, buf_get_u32(args[i].value, 0, 32));
rp2040.c:161	LOG_DEBUG("Flushing flash cache after write behind");
rp2040.c:168	LOG_DEBUG("Configuring SSI for execute-in-place");
rp2040.c:197	LOG_DEBUG("Connecting internal flash");
rp2040.c:204	LOG_DEBUG("Kicking flash out of XIP mode");
rp2040.c:216	LOG_DEBUG("Writing %d bytes starting at 0x%" PRIx32, count, offset);
rp2040.c:243	LOG_DEBUG("Allocated flash bounce buffer @" TARGET_ADDR_FMT, bounce->address);
rp2040.c:247	LOG_DEBUG("Writing %d bytes to offset 0x%" PRIx32, write_size, offset);
rp2040.c:290	LOG_DEBUG("RP2040 erase %d bytes starting at 0x%" PRIx32, length, start_addr);
rp2040.c:296	LOG_DEBUG("Remote call flash_range_erase");
rp2040.c:442	LOG_DEBUG("SPI flash autodetection disabled, using configured size");
rs14100.c:167	LOG_DEBUG("Running flash init algorithm");
rs14100.c:280	LOG_DEBUG("Running flash erase algorithm");
rsl10.c:345	LOG_DEBUG("erasing buffer flash address=0x%" PRIx32, address);
rsl10.c:405	LOG_DEBUG("Writing 0x%" PRIx32 " to flash address=0x%" PRIx32 " bytes=0x%" PRIx32, data, address, bytes);
rsl10.c:407	LOG_DEBUG("Writing buffer to flash address=0x%" PRIx32 " bytes=0x%" PRIx32, address, bytes);
rsl10.c:463	LOG_DEBUG(
rtkernel.c:131	LOG_DEBUG("task name at 0x%" PRIx32 ", value \"%s\"", name, tmp_str);
rtkernel.c:146	LOG_DEBUG("task state 0x%" PRIx16, state);
rtkernel.c:227	LOG_DEBUG("current task is 0x%" PRIx32, current_task);
rtkernel.c:237	LOG_DEBUG("chain start at 0x%" PRIx32, chain);
rtkernel.c:246	LOG_DEBUG("next entry at 0x%" PRIx32, next);
rtkernel.c:248	LOG_DEBUG("end of chain detected");
rtkernel.c:252	LOG_DEBUG("found task at 0x%" PRIx32, task);
rtkernel.c:291	LOG_DEBUG("stack pointer at 0x%" PRIx64 ", value 0x%" PRIx32,
rtkernel.c:321	LOG_DEBUG("cm3 stacking");
rtkernel.c:334	LOG_DEBUG("cm4f_fpu stacking");
rtkernel.c:338	LOG_DEBUG("cm4f stacking");
rtos.c:274	LOG_DEBUG("RTOS: Address of symbol '%s%s' is 0x%" PRIx64, cur_sym, cur_suffix, addr);
rtos.c:316	LOG_DEBUG("RTOS: Requesting symbol lookup of '%s%s' from the debugger", next_sym->symbol_name, next_suffix);
rtos.c:465	LOG_DEBUG("RTOS: GDB requested to set current thread to 0x%" PRIx64, threadid);
rtos.c:514	LOG_DEBUG("getting register %d for thread 0x%" PRIx64
rtos.c:566	LOG_DEBUG("RTOS: getting register list for thread 0x%" PRIx64
rtos.c:629	LOG_DEBUG("RTOS: Read stack frame at 0x%" PRIx32, address);
rtos_standard_stackings.c:165	LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
rtt.c:216	LOG_DEBUG("rtt: Registering sink for channel %u", channel_index);
rtt.c:237	LOG_DEBUG("rtt: Unregistering sink for channel %u", channel_index);
rtt.c:214	LOG_DEBUG("rtt: Wrote %zu bytes into down-channel %u", *length,
rtt_server.c:62	LOG_DEBUG("rtt: New connection for channel %u", service->channel);
rtt_server.c:82	LOG_DEBUG("rtt: Connection for channel %u closed", service->channel);
semihosting_common.c:107	LOG_DEBUG(" ");
semihosting_common.c:390	LOG_DEBUG("op=0x%x (%s), param=0x%" PRIx64, semihosting->op,
semihosting_common.c:452	LOG_DEBUG("ignoring semihosting attempt to close %s",
semihosting_common.c:468	LOG_DEBUG("close(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:693	LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:696	LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:753	LOG_DEBUG("SYS_GET_CMDLINE=[%s], %" PRId64, arg, semihosting->result);
semihosting_common.c:847	LOG_DEBUG("isatty(%d)=%" PRId64, fd, semihosting->result);
semihosting_common.c:966	LOG_DEBUG("dup(STDIN)=%d", fd);
semihosting_common.c:970	LOG_DEBUG("dup(STDOUT)=%d", fd);
semihosting_common.c:974	LOG_DEBUG("dup(STDERR)=%d", fd);
semihosting_common.c:988	LOG_DEBUG("open('%s')=%" PRId64, fn, semihosting->result);
semihosting_common.c:1051	LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%" PRId64,
semihosting_common.c:1091	LOG_DEBUG("getchar()=%" PRId64, semihosting->result);
semihosting_common.c:1138	LOG_DEBUG("remove('%s')=%" PRId64, fn, semihosting->result);
semihosting_common.c:1209	LOG_DEBUG("rename('%s', '%s')=%" PRId64 " %d", fn1, fn2, semihosting->result, errno);
semihosting_common.c:1255	LOG_DEBUG("lseek(%d, %d)=%" PRId64, fd, (int)pos, semihosting->result);
semihosting_common.c:1314	LOG_DEBUG("system('%s')=%" PRId64, cmd, semihosting->result);
semihosting_common.c:1392	LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%" PRId64,
server.c:608	LOG_DEBUG("Terminating on Signal %d", sig);
server.c:610	LOG_DEBUG("Ignored extra Signal %d", sig);
sfdp.c:76	LOG_DEBUG("header 0x%08" PRIx32 " 0x%08" PRIx32, header.signature, header.revision);
sfdp.c:89	LOG_DEBUG("parameter headers: %d", nph);
sfdp.c:106	LOG_DEBUG("pheader %d len=0x%02" PRIx8 " id=0x%04" PRIx16
sfdp.c:121	LOG_DEBUG("word %02d 0x%08X", j + 1, ptable[j]);
sfdp.c:133	LOG_DEBUG("basic flash parameter table");
sfdp.c:233	LOG_DEBUG("unimplemented parameter table id=0x%04" PRIx16, id);
sh_qspi.c:448	LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
sh_qspi.c:498	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
sh_qspi.c:531	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
sh_qspi.c:602	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
sh_qspi.c:776	LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
sh_qspi.c:878	LOG_DEBUG("%s", __func__);
sim3x.c:864	LOG_DEBUG("DAP_REG[0x%02x] <- %08" PRIX32, reg, value);
sim3x.c:868	LOG_DEBUG("DAP: failed to get AP");
sim3x.c:874	LOG_DEBUG("DAP: failed to queue a write request");
sim3x.c:882	LOG_DEBUG("DAP: dap_run failed");
sim3x.c:893	LOG_DEBUG("DAP: failed to get AP");
sim3x.c:899	LOG_DEBUG("DAP: failed to queue a read request");
sim3x.c:907	LOG_DEBUG("DAP: dap_run failed");
sim3x.c:911	LOG_DEBUG("DAP_REG[0x%02x]: %08" PRIX32, reg, *result);
sim3x.c:928	LOG_DEBUG("DAP: polling timed out");
stellaris.c:529	LOG_DEBUG("usecrl = %i", (int)(usecrl));
stellaris.c:576	LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
stellaris.c:579	LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
stellaris.c:582	LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
stellaris.c:662	LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
stellaris.c:1038	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
stellaris.c:1044	LOG_DEBUG("no working area for block memory writes");
stellaris.c:1059	LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
stellaris.c:1118	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
stellaris.c:1151	LOG_DEBUG("writing flash word-at-a-time");
stellaris.c:1168	LOG_DEBUG("0x%" PRIx32 "", address);
stellaris.c:1192	LOG_DEBUG("0x%" PRIx32 "", address);
stellaris.c:1208	LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
stlink_usb.c:669	LOG_DEBUG("ERROR, failed to alloc usb transfers");
stlink_usb.c:686	LOG_DEBUG("ERROR, failed to submit transfer %zu, error %d", i, retval);
stlink_usb.c:709	LOG_DEBUG("ERROR, transfer %zu failed, error %d", i, retval);
stlink_usb.c:904	LOG_DEBUG("get sense");
stlink_usb.c:927	LOG_DEBUG("socket send error: %s (errno %d)", strerror(errno), errno);
stlink_usb.c:929	LOG_DEBUG("sent size %d (expected %d)", sent_size, send_size);
stlink_usb.c:941	LOG_DEBUG("received size %d (expected %d)", recv_size - remaining_bytes, recv_size);
stlink_usb.c:950	LOG_DEBUG("socket recv error: %s (errno %d)", strerror(errno), errno);
stlink_usb.c:968	LOG_DEBUG("TCP busy");
stlink_usb.c:1066	LOG_DEBUG("unknown/unexpected STLINK status code 0x%x", h->databuf[0]);
stlink_usb.c:1079	LOG_DEBUG("SWD fault response (0x%x)", STLINK_DEBUG_ERR_FAULT);
stlink_usb.c:1082	LOG_DEBUG("wait status SWD_AP_WAIT (0x%x)", STLINK_SWD_AP_WAIT);
stlink_usb.c:1085	LOG_DEBUG("wait status SWD_DP_WAIT (0x%x)", STLINK_SWD_DP_WAIT);
stlink_usb.c:1088	LOG_DEBUG("STLINK_JTAG_GET_IDCODE_ERROR");
stlink_usb.c:1091	LOG_DEBUG("Write error");
stlink_usb.c:1094	LOG_DEBUG("Write verify error, ignoring");
stlink_usb.c:1102	LOG_DEBUG("STLINK_SWD_AP_FAULT");
stlink_usb.c:1105	LOG_DEBUG("STLINK_SWD_AP_ERROR");
stlink_usb.c:1108	LOG_DEBUG("STLINK_SWD_AP_PARITY_ERROR");
stlink_usb.c:1111	LOG_DEBUG("STLINK_SWD_DP_FAULT");
stlink_usb.c:1114	LOG_DEBUG("STLINK_SWD_DP_ERROR");
stlink_usb.c:1117	LOG_DEBUG("STLINK_SWD_DP_PARITY_ERROR");
stlink_usb.c:1120	LOG_DEBUG("STLINK_SWD_AP_WDATA_ERROR");
stlink_usb.c:1123	LOG_DEBUG("STLINK_SWD_AP_STICKY_ERROR");
stlink_usb.c:1126	LOG_DEBUG("STLINK_SWD_AP_STICKYORUN_ERROR");
stlink_usb.c:1129	LOG_DEBUG("STLINK_BAD_AP_ERROR");
stlink_usb.c:1132	LOG_DEBUG("unknown/unexpected STLINK status code 0x%x", h->databuf[0]);
stlink_usb.c:1183	LOG_DEBUG("stlink_cmd_allow_retry ERROR_WAIT, retry %d, delaying %u microseconds", retries, delay_us);
stlink_usb.c:1696	LOG_DEBUG("MODE: 0x%02X", mode);
stlink_usb.c:1764	LOG_DEBUG("MODE: 0x%02X", mode);
stlink_usb.c:1824	LOG_DEBUG("MODE: 0x%02X", mode);
stlink_usb.c:2057	LOG_DEBUG("IDCODE: 0x%08" PRIX32, *idcode);
stlink_usb.c:2230	LOG_DEBUG("Tracing: disable");
stlink_usb.c:2264	LOG_DEBUG("Tracing: recording at %" PRIu32 "Hz", h->trace.source_hz);
stlink_usb.c:2502	LOG_DEBUG("max buffer (%d) length exceeded", stlink_usb_block(h));
stlink_usb.c:2546	LOG_DEBUG("max buffer length (%d) exceeded", stlink_usb_block(h));
stlink_usb.c:2586	LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2592	LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2634	LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2640	LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2677	LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2683	LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2722	LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2728	LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2763	LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2769	LOG_DEBUG("Invalid data alignment");
stlink_usb.c:2805	LOG_DEBUG("max buffer (%d) length exceeded", STLINK_MAX_RW16_32);
stlink_usb.c:2811	LOG_DEBUG("Invalid data alignment");
stlink_usb.c:3130	LOG_DEBUG("Supported clock speeds are:");
stlink_usb.c:3133	LOG_DEBUG("%d kHz", map[i].speed);
stlink_usb.c:3418	LOG_DEBUG("claim interface failed");
stlink_usb.c:3427	LOG_DEBUG("libusb_get_pid failed");
stlink_usb.c:3540	LOG_DEBUG("socket : %x", h->tcp_backend_priv.fd);
stlink_usb.c:3614	LOG_DEBUG("%d ST-LINK detected", connected_stlinks);
stlink_usb.c:3676	LOG_DEBUG("Device serial number '%s' doesn't match requested serial '%s'",
stlink_usb.c:3698	LOG_DEBUG("transport: vid: 0x%04x pid: 0x%04x serial: %s", h->vid, h->pid, serial);
stlink_usb.c:3732	LOG_DEBUG("stlink_open");
stlink_usb.c:3737	LOG_DEBUG("malloc failed");
stlink_usb.c:3744	LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x serial: %s",
stlink_usb.c:3820	LOG_DEBUG("Using TAR autoincrement: %" PRIu32, h->max_mem_packet);
stlink_usb.c:4127	LOG_DEBUG("AP %d enabled", apsel);
stlink_usb.c:4297	LOG_DEBUG("Ignoring DPBANKSEL while write SELECT");
stlink_usb.c:4377	LOG_DEBUG("Queue: %u commands in %u items", len, items);
stlink_usb.c:5120	LOG_DEBUG("stlink_dap_init()");
stlink_usb.c:5155	LOG_DEBUG("stlink_dap_quit()");
stlink_usb.c:5163	LOG_DEBUG("stlink_dap_reset(%d)", req_srst);
stm32f1x.c:173	LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32f2x.c:284	LOG_DEBUG("status: 0x%" PRIx32, status);
stm32f2x.c:573	LOG_DEBUG("unable to read option bytes");
stm32f2x.c:677	LOG_DEBUG("unable to read option bytes");
stm32f2x.c:902	LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
stm32f2x.c:1150	LOG_DEBUG("unable to read option bytes");
stm32f2x.c:1167	LOG_DEBUG("unable to read option bytes");
stm32f2x.c:1192	LOG_DEBUG("allocated %u sectors", num_pages);
stm32f2x.c:1202	LOG_DEBUG("allocated %u prot blocks", num_prot_blocks);
stm32g0x.c:207	LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32g4x.c:387	LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32h7x.c:453	LOG_DEBUG("unable to read WPSN_CUR register");
stm32h7x.c:490	LOG_DEBUG("erase sector %u", i);
stm32h7x.c:534	LOG_DEBUG("unable to read WPSN_CUR register");
stm32h7x.c:548	LOG_DEBUG("stm32x_protect, option_bytes written WPSN 0x%" PRIx32, protection);
stm32h7x.c:604	LOG_DEBUG("target_alloc_working_area_try : buffer_size -> 0x%" PRIx32, buffer_size);
stm32h7x.c:768	LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
stm32h7x.c:792	LOG_DEBUG("flash_regs_base: 0x%" PRIx32, stm32x_info->flash_regs_base);
stm32h7x.c:973	LOG_DEBUG("unable to read FLASH_OPTSR_PRG register");
stm32l4x.c:878	LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32l4x.c:924	LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
stm32l4x.c:1355	LOG_DEBUG("current protected areas: %s", ranges_str);
stm32l4x.c:1358	LOG_DEBUG("current protected areas: none");
stm32l4x.c:1374	LOG_DEBUG("requested areas for protection: %s", ranges_str);
stm32l4x.c:1377	LOG_DEBUG("requested areas for protection: none");
stm32l4x.c:1647	LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
stm32l4x.c:2129	LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
stm32l5x.c:247	LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm32lx.c:444	LOG_DEBUG("no working area for block memory writes");
stm32lx.c:748	LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
stm32lx.c:1207	LOG_DEBUG("status: 0x%" PRIx32 "", status);
stm8.c:326	LOG_DEBUG("DM_BKR1E=%" PRIx32, data);
stm8.c:329	LOG_DEBUG("DM_BKR2E=%" PRIx32, data);
stm8.c:331	LOG_DEBUG("addr=%" PRIu32, addr);
stm8.c:340	LOG_DEBUG("DM_CR1=%" PRIx8, buf[0]);
stm8.c:418	LOG_DEBUG("hw breakpoints: numinst %i numdata %i", stm8->num_hw_bpoints,
stm8.c:433	LOG_DEBUG("csr1 = 0x%02X csr2 = 0x%02X", csr1, csr2);
stm8.c:473	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
stm8.c:742	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR
stm8.c:773	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR
stm8.c:795	LOG_DEBUG("stm8_speed: %d", speed);
stm8.c:801	LOG_DEBUG("writing B0 to SWIM_CSR (SAFE_MASK + SWIM_DM + HS:%d)", csr & HS ? 1 : 0);
stm8.c:836	LOG_DEBUG("stm8_read_dm_csrx failed retval=%d", retval);
stm8.c:848	LOG_DEBUG("DM_CSR2_STALL already set during server startup.");
stm8.c:852	LOG_DEBUG("stm8_debug_entry failed retval=%d", retval);
stm8.c:874	LOG_DEBUG("target->state: %s", target_state_name(target));
stm8.c:877	LOG_DEBUG("target was already halted");
stm8.c:921	LOG_DEBUG("Hardware srst not supported, falling back to swim reset");
stm8.c:993	LOG_DEBUG("%d " TARGET_ADDR_FMT " %d %d", current, address,
stm8.c:1032	LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT,
stm8.c:1054	LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
stm8.c:1058	LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
stm8.c:1134	LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num, reg_value);
stm8.c:1154	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
stm8.c:1298	LOG_DEBUG("%x " TARGET_ADDR_FMT " %x",
stm8.c:1345	LOG_DEBUG("target stepped ");
stm8.c:1399	LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
stm8.c:1403	LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
stm8.c:1476	LOG_DEBUG("Invalid comparator number in breakpoint (bpid: %" PRIu32 ")",
stm8.c:1480	LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
stm8.c:1489	LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
stm8.c:1587	LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "",
stm8.c:1639	LOG_DEBUG("Invalid hw comparator number in watchpoint");
stm8.c:1812	LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
stm8.c:1829	LOG_DEBUG("Running algorithm");
stm8.c:1923	LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
stm8.c:1959	LOG_DEBUG("blocksize=%8.8" PRIx32, stm8->blocksize);
stm8.c:1978	LOG_DEBUG("flashstart=%8.8" PRIx32, stm8->flashstart);
stm8.c:1997	LOG_DEBUG("flashend=%8.8" PRIx32, stm8->flashend);
stm8.c:2016	LOG_DEBUG("eepromstart=%8.8" PRIx32, stm8->eepromstart);
stm8.c:2035	LOG_DEBUG("eepromend=%8.8" PRIx32, stm8->eepromend);
stm8.c:2054	LOG_DEBUG("optionstart=%8.8" PRIx32, stm8->optionstart);
stm8.c:2073	LOG_DEBUG("optionend=%8.8" PRIx32, stm8->optionend);
stm8.c:2082	LOG_DEBUG("enable_step_irq=%8.8x", stm8->enable_step_irq);
stm8.c:2091	LOG_DEBUG("enable_stm8l=%8.8x", stm8->enable_stm8l);
stmqspi.c:210	LOG_DEBUG("%s", __func__);
stmqspi.c:253	LOG_DEBUG("busy: 0x%08X", spi_sr);
stmqspi.c:388	LOG_DEBUG("flash status regs: 0x%04" PRIx16, *status);
stmqspi.c:496	LOG_DEBUG("%s", __func__);
stmqspi.c:617	LOG_DEBUG("%s", __func__);
stmqspi.c:727	LOG_DEBUG("FSIZE = 0x%04x", fsize);
stmqspi.c:729	LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
stmqspi.c:731	LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
stmqspi.c:781	LOG_DEBUG("%s", __func__);
stmqspi.c:960	LOG_DEBUG("erase status regs: 0x%04" PRIx16, status);
stmqspi.c:986	LOG_DEBUG("erasing sector %4u", sector);
stmqspi.c:1002	LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
stmqspi.c:1193	LOG_DEBUG("checking sectors %u to %u", sector, sector + count - 1);
stmqspi.c:1220	LOG_DEBUG("Flash sector %u checked: 0x%04x", sector + index, result & 0xFFFFU);
stmqspi.c:1346	LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
stmqspi.c:1381	LOG_DEBUG("%s: offset=0x%08" PRIx32 " len=0x%08" PRIx32,
stmqspi.c:1576	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmqspi.c:1616	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmqspi.c:1677	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmqspi.c:1731	LOG_DEBUG("%s: len=%d, dual=%u, flash1=%d",
stmqspi.c:1782	LOG_DEBUG("start of SFDP header for flash%c after %u dummy bytes",
stmqspi.c:1799	LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count);
stmqspi.c:1851	LOG_DEBUG("%s: addr=0x%08" PRIx32 " words=0x%08x dummy=%u",
stmqspi.c:1923	LOG_DEBUG("raw SFDP data 0x%08" PRIx32, *buffer);
stmqspi.c:2110	LOG_DEBUG("QSPI_ABR register present");
stmqspi.c:2118	LOG_DEBUG("OCTOSPI_MAGIC present");
stmqspi.c:2162	LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
stmqspi.c:2167	LOG_DEBUG("QSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", QSPI_CR 0x%08"
stmqspi.c:2189	LOG_DEBUG("id1 0x%06" PRIx32 ", id2 0x%06" PRIx32, id1, id2);
stmqspi.c:2325	LOG_DEBUG("FSIZE = 0x%04x", fsize);
stmqspi.c:2327	LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
stmqspi.c:2329	LOG_DEBUG("FSIZE in DCR(1) is off by one regarding actual capacity. Fix for silicon bug?");
stmsmi.c:130	LOG_DEBUG("%s", __func__);
stmsmi.c:312	LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
stmsmi.c:367	LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
stmsmi.c:393	LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
stmsmi.c:553	LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
str7x.c:338	LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
str9xpec.c:109	LOG_DEBUG("status: 0x%2.2x", status);
str9xpec.c:137	LOG_DEBUG("ISC_MODE Enabled");
str9xpec.c:165	LOG_DEBUG("ISC_MODE Disabled");
str9xpec.c:181	LOG_DEBUG("ISC_CONFIGURATION");
str9xpec.c:316	LOG_DEBUG("blank check: first_bank: %u, last_bank: %u", first, last);
str9xpec.c:397	LOG_DEBUG("erase: first_bank: %u, last_bank: %u", first, last);
str9xpec.c:411	LOG_DEBUG("ISC_ERASE");
str9xpec.c:509	LOG_DEBUG("protect: first_bank: %u, last_bank: %u", first, last);
str9xpec.c:607	LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);
str9xpec.c:611	LOG_DEBUG("ISC_PROGRAM");
svf.c:1024	LOG_DEBUG("\tIR end_state = %s",
svf.c:1028	LOG_DEBUG("\tDR end_state = %s",
svf.c:1058	LOG_DEBUG("\tfrequency = %f", svf_para.frequency);
svf.c:1117	LOG_DEBUG("\tlength = %d", xxr_para_tmp->len);
svf.c:1403	LOG_DEBUG("\trun_state = %s", tap_state_name(i_tmp));
svf.c:1416	LOG_DEBUG("\trun_count@TCK = %d", run_count);
svf.c:1426	LOG_DEBUG("\tmin_time = %fs", min_time);
svf.c:1434	LOG_DEBUG("\tmax_time = %fs", max_time);
svf.c:1443	LOG_DEBUG("\tend_state = %s", tap_state_name(i_tmp));
svf.c:1534	LOG_DEBUG("\tmove to %s by path_move",
svf.c:1551	LOG_DEBUG("\tmove to %s by svf_add_statemove",
svf.c:1591	LOG_DEBUG("\ttrst_mode = %s", svf_trst_mode_name[svf_para.trst_mode]);
swim.c:81	LOG_DEBUG("Creating new SWIM \"tap\", Chip: %s, Tap: %s, Dotted: %s",
swim.c:116	LOG_DEBUG(__func__);
swim.c:125	LOG_DEBUG(__func__);
target.c:986	LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
target.c:1141	LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
target.c:1598	LOG_DEBUG("Initializing targets...");
target.c:1784	LOG_DEBUG("target event %i (%s) for core %s", event,
target.c:1803	LOG_DEBUG("target reset %i (%s)", reset_mode,
target.c:1910	LOG_DEBUG("%c%c " TARGET_ADDR_FMT "-" TARGET_ADDR_FMT " (%" PRIu32 " bytes)",
target.c:1989	LOG_DEBUG("MMU disabled, using physical "
target.c:2000	LOG_DEBUG("MMU enabled, using virtual "
target.c:2043	LOG_DEBUG("allocated new working area of %" PRIu32 " bytes at address " TARGET_ADDR_FMT,
target.c:2111	LOG_DEBUG("freed %" PRIu32 " bytes of working area at address " TARGET_ADDR_FMT,
target.c:2140	LOG_DEBUG("freeing all working areas");
target.c:2354	LOG_DEBUG("writing buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
target.c:2419	LOG_DEBUG("reading buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
target.c:2548	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2553	LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2572	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2577	LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2596	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%4.4" PRIx16,
target.c:2601	LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2618	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2623	LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2639	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2646	LOG_DEBUG("failed: %i", retval);
target.c:2660	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2667	LOG_DEBUG("failed: %i", retval);
target.c:2681	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16,
target.c:2688	LOG_DEBUG("failed: %i", retval);
target.c:2701	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2706	LOG_DEBUG("failed: %i", retval);
target.c:2720	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2727	LOG_DEBUG("failed: %i", retval);
target.c:2741	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2748	LOG_DEBUG("failed: %i", retval);
target.c:2762	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16,
target.c:2769	LOG_DEBUG("failed: %i", retval);
target.c:2782	LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2787	LOG_DEBUG("failed: %i", retval);
target.c:3033	LOG_DEBUG("-");
target.c:3240	LOG_DEBUG("waiting for target %s...",
target.c:3262	LOG_DEBUG("-");
target.c:3339	LOG_DEBUG("-");
target.c:4591	LOG_DEBUG("read_memory: read at " TARGET_ADDR_FMT " with width=%u and count=%zu failed",
target.c:4781	LOG_DEBUG("target: %s (%s) event: %d (%s) action: %s",
target.c:5985	LOG_DEBUG("target_create failed");
target.c:6085	LOG_DEBUG("%s ", targetname);
target.c:6123	LOG_DEBUG("Empty SMP target");
target.c:6126	LOG_DEBUG("%d", CMD_ARGC);
target_request.c:45	LOG_DEBUG("%s", msg);
target_request.c:70	LOG_DEBUG("size: %i, length: %i", (int)size, (int)length);
target_request.c:89	LOG_DEBUG("%s", line);
tcl.c:484	LOG_DEBUG("Initializing NAND devices...");
tcl.c:549	LOG_DEBUG("'%s' driver usage field missing", controller->name);
tcl.c:1307	LOG_DEBUG("'%s' driver usage field missing", driver_name);
tcl.c:1364	LOG_DEBUG("Initializing flash devices...");
tcl.c:404	LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
tcl.c:546	LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s",
tcl.c:685	LOG_DEBUG("Initializing jtag devices...");
telnet_server.c:822	LOG_DEBUG("unhandled nonprintable: %2.2x", *buf_p);
ti_icdi_usb.c:154	LOG_DEBUG("Error TX Data %d", result);
ti_icdi_usb.c:162	LOG_DEBUG("Error RX Data %d", result);
ti_icdi_usb.c:171	LOG_DEBUG("Resending packet %d", ++retry);
ti_icdi_usb.c:174	LOG_DEBUG("Unexpected Reply from ICDI: %c", h->read_buffer[0]);
ti_icdi_usb.c:179	LOG_DEBUG("maximum nack retries attempted");
ti_icdi_usb.c:201	LOG_DEBUG("Error RX timeout %d", result);
ti_icdi_usb.c:203	LOG_DEBUG("Error RX Data %d", result);
ti_icdi_usb.c:221	LOG_DEBUG("maximum data retries attempted");
ti_icdi_usb.c:372	LOG_DEBUG("max packet supported : %i bytes", h->max_packet);
ti_icdi_usb.c:671	LOG_DEBUG("icdi_usb_open");
ti_icdi_usb.c:681	LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x serial: %s", param->transport,
ti_icdi_usb.c:694	LOG_DEBUG("claim interface failed");
ti_icdi_usb.c:724	LOG_DEBUG("malloc failed");
tms470.c:503	LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
tms470.c:511	LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
tms470.c:517	LOG_DEBUG("set fmtcreg = 0x2fc0");
tms470.c:523	LOG_DEBUG("set fmmaxpp = 50");
tms470.c:529	LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
tms470.c:538	LOG_DEBUG("set fmptr3 = 0x9964");
tms470.c:542	LOG_DEBUG("set fmptr3 = 0x9b64");
tms470.c:545	LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
tms470.c:551	LOG_DEBUG("set fmptr4 = 0xa000");
tms470.c:565	LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) \| (delay << 8));
tms470.c:572	LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
tms470.c:579	LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
tms470.c:581	LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
tms470.c:583	LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
tms470.c:590	LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
tms470.c:597	LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
tms470.c:604	LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
tms470.c:610	LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
tms470.c:612	LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
tms470.c:614	LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
tms470.c:628	LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
tms470.c:683	LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl \| 0x10);
tms470.c:688	LOG_DEBUG("set fmregopt = 0x%08x", 0);
tms470.c:700	LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea \| (1 << sector));
tms470.c:704	LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb \| (1 << (sector - 16)));
tms470.c:712	LOG_DEBUG("write (uint16_t )0x%08" PRIx32 "=0x0040", flash_addr);
tms470.c:714	LOG_DEBUG("write (uint16_t )0x%08" PRIx32 "=0x0020", flash_addr);
tms470.c:716	LOG_DEBUG("write (uint16_t )0x%08" PRIx32 "=0xffff", flash_addr);
tms470.c:732	LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
tms470.c:736	LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
tms470.c:740	LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
tms470.c:742	LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
tms470.c:1096	LOG_DEBUG("bank %u sector %u is %s",
trace.c:20	LOG_DEBUG("tracepoint: %i", (int)number);
transport.c:146	LOG_DEBUG("register '%s'", new_transport->name);
transport.c:219	LOG_DEBUG("%s", __func__);
ublast2_access_libusb.c:76	LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04x)", section_index, addr,
ulink.c:442	LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04x)", section_index, addr,
usbprog.c:321	LOG_DEBUG("trst: %i, srst: %i", trst, srst);
virtex2.c:141	LOG_DEBUG("status: 0x%8.8" PRIx32, *status);
vsllink.c:286	LOG_DEBUG("vsllink found on %04X:%04X",
vsllink.c:456	LOG_DEBUG("trst: %i, srst: %i", trst, srst);
vsllink.c:705	LOG_DEBUG("SWD delay: %d, retry count: %d", delay, retry_count);
vsllink.c:717	LOG_DEBUG("SWD line reset");
vsllink.c:722	LOG_DEBUG("JTAG-to-SWD");
vsllink.c:727	LOG_DEBUG("SWD-to-JTAG");
w600.c:131	LOG_DEBUG("WRITE CMD: 0x%08" PRIx32 "", cmd);
w600.c:137	LOG_DEBUG("WRITE START: 0x%08" PRIx32 "", addr);
w600.c:142	LOG_DEBUG("DELAY %dms", timeout);
w600.c:148	LOG_DEBUG("READ START...");
w600.c:151	LOG_DEBUG("READ START: 0x%08" PRIx32 "", status);
w600.c:153	LOG_DEBUG("READ START FAILED");
x86_32_common.c:65	LOG_DEBUG("num_regs=%d, reg_class=%d", (*reg_list_size), reg_class);
x86_32_common.c:74	LOG_DEBUG("value %s = %08" PRIx32, x86_32->cache->reg_list[i].name,
x86_32_common.c:164	LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:269	LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:305	LOG_DEBUG("invalid read size");
x86_32_common.c:573	LOG_DEBUG("addr=" TARGET_ADDR_FMT ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:630	LOG_DEBUG("addr=" TARGET_ADDR_FMT ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:688	LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", buf=%p", addr, size, buf);
x86_32_common.c:766	LOG_DEBUG("addr=0x%08" PRIx32 ", size=%" PRIu32 ", buf=%p", addr, size, buf);
x86_32_common.c:861	LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:872	LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:885	LOG_DEBUG("addr=0x%08" PRIx32 ", bp_num=%" PRIu8 ", bp_type=%" PRIu8 ", pb_length=%" PRIu8,
x86_32_common.c:945	LOG_DEBUG("bp_num=%" PRIu8, bp_num);
x86_32_common.c:1020	LOG_DEBUG("id %" PRIx32, bp->unique_id);
x86_32_common.c:1030	LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8 "", *bp->orig_instr);
x86_32_common.c:1076	LOG_DEBUG("id %" PRIx32, bp->unique_id);
x86_32_common.c:1125	LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1155	LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1183	LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, wp->rw, wp->address);
x86_32_common.c:1239	LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, wp->rw, wp->address);
x86_32_common.c:1247	LOG_DEBUG("Invalid FP Comparator number in watchpoint");
x86_32_common.c:1310	LOG_DEBUG("reg %s value 0x%08" PRIx32,
x86_32_common.c:1326	LOG_DEBUG("reg %s value 0x%08" PRIx32, x86_32->cache->reg_list[num].name,
x86_32_common.c:1432	LOG_DEBUG("address=0x%08" PRIx32 ", data_size=%u, b=0x%08" PRIx32,
xcf.c:470	LOG_DEBUG("written %d bytes from %d", dbg_written, dbg_count);
xds110.c:633	LOG_DEBUG("XDS110: command 0x%02x return %" PRIu32 " bytes, expected %" PRIu32,
xds110.c:640	LOG_DEBUG("XDS110: command 0x%02x returned error %d",
xds110.c:1101	LOG_DEBUG("JTAG-to-SWD");
xds110.c:1118	LOG_DEBUG("SWD-to-JTAG");
xds110.c:1333	LOG_DEBUG("XDS110: refusing to enable sticky overrun detection");
xilinx_bit.c:116	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
xmc1xxx.c:93	LOG_DEBUG("Infineon XMC1000 erase sectors %u to %u", first, last);
xmc1xxx.c:203	LOG_DEBUG("Erase-checking 0x%08" PRIx32, start);
xmc1xxx.c:254	LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
xmc1xxx.c:307	LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
xmc1xxx.c:330	LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
xmc1xxx.c:394	LOG_DEBUG("NVMCONF = %08" PRIx32, nvmconf);
xmc1xxx.c:421	LOG_DEBUG("ID[%d] = %08" PRIX32, i, chipid[i]);
xmc1xxx.c:428	LOG_DEBUG("ID[7] = %08" PRIX32, chipid[7]);
xmc1xxx.c:467	LOG_DEBUG("IDCHIP = %08" PRIx32, idchip);
xmc4xxx.c:272	LOG_DEBUG("%u sectors", bank->num_sectors);
xmc4xxx.c:306	LOG_DEBUG("\t%d: %uk", i, capacity[i]);
xmc4xxx.c:348	LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
xmc4xxx.c:365	LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
xmc4xxx.c:369	LOG_DEBUG("XMC4xxx: XMC4400 detected.");
xmc4xxx.c:373	LOG_DEBUG("XMC4xxx: XMC4500 detected.");
xmc4xxx.c:377	LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
xmc4xxx.c:556	LOG_DEBUG("Erasing sector %u @ 0x%08"PRIx32, i, tmp_addr);
xmc4xxx.c:655	LOG_DEBUG("WLO: %08"PRIx32, w_lo);
xmc4xxx.c:656	LOG_DEBUG("WHI: %08"PRIx32, w_hi);
xmc4xxx.c:1082	LOG_DEBUG("Setting flash protection with procon:");
xmc4xxx.c:1083	LOG_DEBUG("PROCON: %"PRIx32, procon);
xscale.c:403	LOG_DEBUG("waiting 100ms");
xscale.c:452	LOG_DEBUG("polling RX");
xscale.c:474	LOG_DEBUG("waiting 100ms");
xscale.c:642	LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
xscale.c:862	LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
xscale.c:868	LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
xscale.c:875	LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
xscale.c:879	LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
xscale.c:886	LOG_DEBUG("target entered debug state in %s mode",
xscale.c:1012	LOG_DEBUG("target->state: %s",
xscale.c:1016	LOG_DEBUG("target was already halted");
xscale.c:1023	LOG_DEBUG("target->state == TARGET_RESET");
xscale.c:1118	LOG_DEBUG("-");
xscale.c:1155	LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
xscale.c:1169	LOG_DEBUG("enable single-step");
xscale.c:1183	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
xscale.c:1190	LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
xscale.c:1197	LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
xscale.c:1210	LOG_DEBUG("disable single-step");
xscale.c:1213	LOG_DEBUG("set breakpoint at " TARGET_ADDR_FMT "",
xscale.c:1248	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
xscale.c:1254	LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
xscale.c:1260	LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
xscale.c:1275	LOG_DEBUG("target resumed");
xscale.c:1304	LOG_DEBUG("enable single-step");
xscale.c:1334	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
xscale.c:1343	LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
xscale.c:1352	LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
xscale.c:1365	LOG_DEBUG("disable single-step");
xscale.c:1401	LOG_DEBUG("current pc %" PRIx32, current_pc);
xscale.c:1426	LOG_DEBUG("target stepped");
xscale.c:1443	LOG_DEBUG("target->state: %s",
xscale.c:1485	LOG_DEBUG("-");
xscale.c:1632	LOG_DEBUG("-");
xscale.c:1778	LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
xscale.c:1877	LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
xscale.c:2529	LOG_DEBUG("no trace data collected");
xsvf.c:297	LOG_DEBUG("XSTATE 0x%02X %s", uc,
xsvf.c:349	LOG_DEBUG("XCOMPLETE");
xsvf.c:359	LOG_DEBUG("XTDOMASK");
xsvf.c:375	LOG_DEBUG("XRUNTEST %d 0x%08X", xruntest, xruntest);
xsvf.c:387	LOG_DEBUG("XREPEAT %d", xrepeat);
xsvf.c:402	LOG_DEBUG("XSDRSIZE %d", xsdrsize);
xsvf.c:439	LOG_DEBUG("%s %d", op_name, xsdrsize);
xsvf.c:575	LOG_DEBUG("XSTATE 0x%02X %s", uc, tap_state_name(mystate));
xsvf.c:627	LOG_DEBUG("XENDIR 0x%02X %s", uc, tap_state_name(xendir));
xsvf.c:648	LOG_DEBUG("XENDDR %02X %s", uc, tap_state_name(xenddr));
xsvf.c:666	LOG_DEBUG("XSIR %d", bitcount);
xsvf.c:673	LOG_DEBUG("XSIR2 %d", bitcount);
xsvf.c:762	LOG_DEBUG("XWAIT %s %s usecs:%d", tap_state_name(
xsvf.c:810	LOG_DEBUG("XWAITSTATE %s %s clocks:%i usecs:%i",
xsvf.c:854	LOG_DEBUG("LCOUNT %d", loop_count);
xsvf.c:879	LOG_DEBUG("LDELAY %s clocks:%d usecs:%d", tap_state_name(
xsvf.c:893	LOG_DEBUG("LSDR");
xsvf.c:983	LOG_DEBUG("xsvf failed, setting taps to reasonable state");
xtensa.c:474	LOG_DEBUG("Scratch reg %s [0x%08" PRIx32 "] set from gdb", reg->name,
xtensa.c:476	LOG_DEBUG("scratch_ars mapping: a3/%s, a4/%s",
xtensa.c:654	LOG_DEBUG("AR conflict: a%d -> ar%d", a_name, j - XT_REG_IDX_AR0);
xtensa.c:657	LOG_DEBUG("AR conflict: ar%d -> a%d", j - XT_REG_IDX_AR0, a_name);
xtensa.c:909	LOG_DEBUG("OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id);
xtensa.c:1426	LOG_DEBUG("%s = 0x%x", rlist[ridx].name, regval);
xtensa.c:1508	LOG_DEBUG("reg_class=%i, num_regs=%d", (int)reg_class, num_regs);
xtensa.c:1537	LOG_DEBUG("SPARSE GDB reg 0x%x getting EPS%d 0x%x",
xtensa.c:1893	LOG_DEBUG("Stepping out of window exception, PC=%" PRIX32, cur_pc);
xtensa.c:1903	LOG_DEBUG("Stepped from %" PRIX32 " to %" PRIX32, oldpc, cur_pc);
xtensa.c:1909	LOG_DEBUG("Done stepping, PC=%" PRIX32, cur_pc);
xtensa.c:1920	LOG_DEBUG("Restoring %s after stepping: 0x%08" PRIx32,
xtensa.c:2017	LOG_DEBUG("address " TARGET_ADDR_FMT " not readable", address);
xtensa.c:2502	LOG_DEBUG("DHWB dcache line for address "TARGET_ADDR_FMT, address);
xtensa.c:2789	LOG_DEBUG("setting core_mode: 0x%x", algorithm_info->core_mode);
xtensa.c:2853	LOG_DEBUG("Read mem params");
xtensa.c:2855	LOG_DEBUG("Check mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
xtensa.c:2857	LOG_DEBUG("Read mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
xtensa.c:2874	LOG_DEBUG("Skip restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32,
xtensa.c:2883	LOG_DEBUG("restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32,
xtensa.c:2888	LOG_DEBUG("restoring register %s: 0x%8.8" PRIx64 " -> 0x%8.8" PRIx64,
xtensa.c:2893	LOG_DEBUG("restoring register %s %u-bits", xtensa->core_cache->reg_list[i].name, reg->size);
xtensa.c:3157	LOG_DEBUG("TIE reg 0x%08" PRIx32 " %s (%d bytes)", regnum, iswrite ? "write" : "read", reglen);
xtensa.c:3489	LOG_DEBUG("start");
xtensa.c:3980	LOG_DEBUG("Setting PS (%s) index to %d", rptr->name, xtensa->eps_dbglevel_idx);
xtensa.c:4005	LOG_DEBUG("NX reg %s: index %d (%d)",
xtensa.c:4020	LOG_DEBUG("Added %s register %-16s: 0x%04x/0x%02x t%d (%d of %d)",
xtensa_chip.c:103	LOG_DEBUG("DAP: ap_num %" PRId64 " DAP %p\n", pc->ap_num, pc->dap);
xtensa_chip.c:106	LOG_DEBUG("JTAG: %s:%s pos %u", target->tap->chip, target->tap->tapname,
xtensa_debug_module.c:120	LOG_DEBUG("DM examine: DAP AP select %d", dm->debug_apsel);
xtensa_debug_module.c:126	LOG_DEBUG("DM examine: search for APB-type MEM-AP...");
xtensa_debug_module.c:139	LOG_DEBUG("DM examine: Setting apsel to %d", dm->debug_apsel);
zephyr.c:436	LOG_DEBUG("ARC EM board has security subsystem, changing offsets");
zephyr.c:560	LOG_DEBUG("Fetched thread%" PRIx32 ": {entry@0x%" PRIx32
zephyr.c:611	LOG_DEBUG("Got information for %zu threads", thread_array.elements);
zephyr.c:726	LOG_DEBUG("Zephyr OpenOCD support version %" PRId32,

LOG_DEBUG macro

Syntax

Arguments

expr

References