OpenOCD
reg_cache::reg_list is only used within OpenOCD.
 
Symbols
loading...
Files
loading...
CodeScopeDevelopment ToolsOpenOCDreg_cache::reg_list

reg_cache::reg_list field

Syntax

struct reg *reg_list;

References

LocationReferrerText
register.h:147
struct reg *reg_list;
arc.c:85arc_reg_get_by_name()
if (!strcmp(cache->reg_list[i].name, name))
arc.c:86arc_reg_get_by_name()
return &(cache->reg_list[i]);
arc.c:365arc_build_reg_cache()
cache->reg_list = reg_list;
arc.c:456arc_build_bcr_reg_cache()
cache->reg_list = reg_list;
arc.c:520arc_get_gdb_reg_list()
(*reg_list)[i] = &reg_cache->reg_list[j];
arc.c:533arc_get_gdb_reg_list()
if (reg_cache->reg_list[j].exist) {
arc.c:534arc_get_gdb_reg_list()
(*reg_list)[i] = &reg_cache->reg_list[j];
arc.c:847arc_save_context()
struct reg *reg_list = arc->core_and_aux_cache->reg_list;
arc.c:1175arc_restore_context()
struct reg *reg_list = arc->core_and_aux_cache->reg_list;
arc.c:1280arc_resume()
struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
arc.c:1381arc_free_reg_cache()
free(cache->reg_list);
arc.c:2093arc_step()
struct reg *pc = &(arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]);
arm11.c:823arm11_read_memory_inner()
arm11->arm.core_cache->reg_list[1].dirty = true;
arm11.c:842arm11_read_memory_inner()
arm11->arm.core_cache->reg_list[1].dirty = true;
arm11.c:932arm11_write_memory_inner()
arm11->arm.core_cache->reg_list[1].dirty = true;
arm11.c:955arm11_write_memory_inner()
arm11->arm.core_cache->reg_list[1].dirty = true;
arm720t.c:311arm720t_soft_reset_halt()
.eice_cache->reg_list[EICE_DBG_STAT];
arm7_9_common.c:63arm7_9_clear_watchpoints()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
arm7_9_common.c:64arm7_9_clear_watchpoints()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
arm7_9_common.c:131arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
arm7_9_common.c:132arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
arm7_9_common.c:133arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
arm7_9_common.c:134arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
arm7_9_common.c:135arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
arm7_9_common.c:137arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
arm7_9_common.c:138arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
arm7_9_common.c:139arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
arm7_9_common.c:140arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
arm7_9_common.c:141arm7_9_set_software_breakpoints()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
arm7_9_common.c:200arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
arm7_9_common.c:201arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
arm7_9_common.c:202arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
arm7_9_common.c:203arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
arm7_9_common.c:204arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
arm7_9_common.c:206arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
arm7_9_common.c:207arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
arm7_9_common.c:208arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
arm7_9_common.c:209arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
arm7_9_common.c:210arm7_9_set_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
arm7_9_common.c:307arm7_9_unset_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
arm7_9_common.c:311arm7_9_unset_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
arm7_9_common.c:354arm7_9_unset_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[
arm7_9_common.c:357arm7_9_unset_breakpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[
arm7_9_common.c:469arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE],
arm7_9_common.c:471arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
arm7_9_common.c:472arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK],
arm7_9_common.c:475arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE],
arm7_9_common.c:477arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
arm7_9_common.c:479arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
arm7_9_common.c:488arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE],
arm7_9_common.c:490arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
arm7_9_common.c:491arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK],
arm7_9_common.c:494arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE],
arm7_9_common.c:496arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
arm7_9_common.c:498arm7_9_set_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE],
arm7_9_common.c:538arm7_9_unset_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
arm7_9_common.c:544arm7_9_unset_watchpoint()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
arm7_9_common.c:616arm7_9_execute_sys_speed()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm7_9_common.c:669arm7_9_execute_fast_sys_speed()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm7_9_common.c:747arm7_9_handle_target_request()
struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
arm7_9_common.c:800arm7_9_poll()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm7_9_common.c:912arm7_9_assert_reset()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
arm7_9_common.c:923arm7_9_assert_reset()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
arm7_9_common.c:924arm7_9_assert_reset()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
arm7_9_common.c:925arm7_9_assert_reset()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
arm7_9_common.c:926arm7_9_assert_reset()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
arm7_9_common.c:927arm7_9_assert_reset()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
arm7_9_common.c:1013arm7_9_clear_halt()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
arm7_9_common.c:1027arm7_9_clear_halt()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
arm7_9_common.c:1033arm7_9_clear_halt()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
arm7_9_common.c:1035arm7_9_clear_halt()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
arm7_9_common.c:1037arm7_9_clear_halt()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
arm7_9_common.c:1039arm7_9_clear_halt()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
arm7_9_common.c:1045arm7_9_clear_halt()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
arm7_9_common.c:1066arm7_9_soft_reset_halt()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm7_9_common.c:1067arm7_9_soft_reset_halt()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
arm7_9_common.c:1176arm7_9_halt()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
arm7_9_common.c:1201arm7_9_halt()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
arm7_9_common.c:1202arm7_9_halt()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
arm7_9_common.c:1203arm7_9_halt()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
arm7_9_common.c:1205arm7_9_halt()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
arm7_9_common.c:1235arm7_9_debug_entry()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm7_9_common.c:1236arm7_9_debug_entry()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
arm7_9_common.c:1415arm7_9_full_context()
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid)
arm7_9_common.c:1430arm7_9_full_context()
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1432arm7_9_full_context()
read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(
arm7_9_common.c:1439arm7_9_full_context()
ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1442arm7_9_full_context()
ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1453arm7_9_full_context()
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
arm7_9_common.c:1455arm7_9_full_context()
read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1459arm7_9_full_context()
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
arm7_9_common.c:1461arm7_9_full_context()
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
arm7_9_common.c:1533arm7_9_restore_context()
reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
arm7_9_common.c:1572arm7_9_restore_context()
reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1592arm7_9_restore_context()
&ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(
arm7_9_common.c:1707arm7_9_resume()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
arm7_9_common.c:1860arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
arm7_9_common.c:1861arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
arm7_9_common.c:1862arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
arm7_9_common.c:1864arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
arm7_9_common.c:1866arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE],
arm7_9_common.c:1868arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
arm7_9_common.c:1869arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
arm7_9_common.c:1870arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
arm7_9_common.c:1871arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
arm7_9_common.c:1874arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
arm7_9_common.c:1875arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
arm7_9_common.c:1876arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
arm7_9_common.c:1877arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
arm7_9_common.c:1878arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
arm7_9_common.c:1879arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
arm7_9_common.c:1880arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
arm7_9_common.c:1881arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE],
arm7_9_common.c:1883arm7_9_enable_eice_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
arm7_9_common.c:1892arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
arm7_9_common.c:1893arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
arm7_9_common.c:1894arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
arm7_9_common.c:1895arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
arm7_9_common.c:1896arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
arm7_9_common.c:1897arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
arm7_9_common.c:1898arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
arm7_9_common.c:1899arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
arm7_9_common.c:1900arm7_9_disable_eice_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
arm7_9_common.c:2280arm7_9_write_memory()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
arm7_9_common.c:2538arm7_9_dcc_completion()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
arm7_9_common.c:2543arm7_9_dcc_completion()
arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
arm7_9_common.c:2551arm7_9_dcc_completion()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
arm7_9_common.c:2556arm7_9_dcc_completion()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
arm7_9_common.c:2829arm7_9_setup_semihosting()
->reg_list[EICE_VEC_CATCH];
arm7tdmi.c:539arm7tdmi_branch_resume_thumb()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm7tdmi.c:581arm7tdmi_branch_resume_thumb()
arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), 0);
arm920t.c:240arm920t_read_cp15_interpreted()
struct reg *r = arm->core_cache->reg_list;
arm920t.c:288arm920t_write_cp15_interpreted()
struct reg *r = arm->core_cache->reg_list;
arm920t.c:737arm920t_soft_reset_halt()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm920t.c:1116arm920t_handle_read_cache_command()
r = arm->core_cache->reg_list;
arm920t.c:1428arm920t_handle_read_mmu_command()
r = arm->core_cache->reg_list;
arm926ejs.c:210arm926ejs_examine_debug_reason()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm926ejs.c:532arm926ejs_soft_reset_halt()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm9tdmi.c:619arm9tdmi_branch_resume_thumb()
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm9tdmi.c:660arm9tdmi_branch_resume_thumb()
buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0);
arm9tdmi.c:678arm9tdmi_enable_single_step()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
arm9tdmi.c:679arm9tdmi_enable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
arm9tdmi.c:689arm9tdmi_disable_single_step()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
arm9tdmi.c:690arm9tdmi_disable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
arm9tdmi.c:808handle_arm9tdmi_catch_vectors_command()
vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
arm_dpm.c:392arm_dpm_read_current_registers()
r = arm->core_cache->reg_list + i;
arm_dpm.c:550arm_dpm_write_dirty_registers()
if (arm->cpsr == cache->reg_list + i)
arm_dpm.c:552arm_dpm_write_dirty_registers()
if (!cache->reg_list[i].exist || !cache->reg_list[i].dirty)
arm_dpm.c:555arm_dpm_write_dirty_registers()
r = cache->reg_list[i].arch_info;
arm_dpm.c:594arm_dpm_write_dirty_registers()
&cache->reg_list[i],
arm_dpm.c:631arm_dpm_write_dirty_registers()
retval = dpm_write_reg(dpm, &cache->reg_list[i], i);
arm_dpm.c:634arm_dpm_write_dirty_registers()
cache->reg_list[i].dirty = false;
arm_dpm.c:801arm_dpm_full_context()
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
arm_dpm.c:803arm_dpm_full_context()
r = cache->reg_list[i].arch_info;
arm_dpm.c:827arm_dpm_full_context()
&cache->reg_list[i],
arm_semihosting.c:85post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:86post_result()
arm->core_cache->reg_list[0].dirty = true;
arm_semihosting.c:89post_result()
buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32,
arm_semihosting.c:91post_result()
arm->core_cache->reg_list[15].dirty = true;
arm_semihosting.c:109post_result()
buf_set_u64(arm->core_cache->reg_list[0].value, 0, 64, target->semihosting->result);
arm_semihosting.c:110post_result()
arm->core_cache->reg_list[0].dirty = true;
arm_semihosting.c:112post_result()
uint64_t pc = buf_get_u64(arm->core_cache->reg_list[32].value, 0, 64);
arm_semihosting.c:117post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:118post_result()
arm->core_cache->reg_list[0].dirty = true;
arm_semihosting.c:120post_result()
uint32_t pc = buf_get_u32(arm->core_cache->reg_list[32].value, 0, 32);
arm_semihosting.c:125post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:126post_result()
arm->core_cache->reg_list[0].dirty = true;
arm_semihosting.c:128post_result()
uint32_t pc = buf_get_u32(arm->core_cache->reg_list[32].value, 0, 32);
arm_semihosting.c:137post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:138post_result()
arm->core_cache->reg_list[0].dirty = true;
arm_semihosting.c:348arm_semihosting()
semihosting->op = buf_get_u64(arm->core_cache->reg_list[0].value, 0, 64);
arm_semihosting.c:349arm_semihosting()
semihosting->param = buf_get_u64(arm->core_cache->reg_list[1].value, 0, 64);
arm_semihosting.c:353arm_semihosting()
semihosting->op = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
arm_semihosting.c:354arm_semihosting()
semihosting->param = buf_get_u32(arm->core_cache->reg_list[1].value, 0, 32);
arm_simulator.c:641armv4_5_get_reg()
return buf_get_u32(arm->core_cache->reg_list[reg].value, 0, 32);
arm_simulator.c:648armv4_5_set_reg()
buf_set_u32(arm->core_cache->reg_list[reg].value, 0, 32, value);
arm_simulator.c:655armv4_5_get_reg_mode()
return buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_simulator.c:663armv4_5_set_reg_mode()
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:465arm_set_cpsr()
: arm->core_cache->reg_list + arm->map[16];
armv4_5.c:511arm_reg_current()
r = arm->core_cache->reg_list + regnum;
armv4_5.c:513arm_reg_current()
r = arm->core_cache->reg_list + arm->map[regnum];
armv4_5.c:520arm_reg_current()
r = arm->core_cache->reg_list + regnum;
armv4_5.c:667arm_build_reg_cache()
cache->reg_list = reg_list;
armv4_5.c:769arm_free_reg_cache()
struct reg *reg = &cache->reg_list[i];
armv4_5.c:775arm_free_reg_cache()
free(cache->reg_list[0].arch_info);
armv4_5.c:776arm_free_reg_cache()
free(cache->reg_list);
armv4_5.c:841handle_armv4_5_reg_command()
regs = arm->core_cache->reg_list;
armv4_5.c:1322arm_get_gdb_reg_list()
int reg_index = arm->core_cache->reg_list[i].number;
armv4_5.c:1331arm_get_gdb_reg_list()
(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
armv4_5.c:1345arm_get_gdb_reg_list()
(*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
armv4_5.c:1435armv4_5_run_algorithm_inner()
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1551armv4_5_run_algorithm_inner()
regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1555armv4_5_run_algorithm_inner()
ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1557armv4_5_run_algorithm_inner()
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1559armv4_5_run_algorithm_inner()
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
armv4_5.c:1561armv4_5_run_algorithm_inner()
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
armv4_5.c:1754arm_full_context()
struct reg *reg = arm->core_cache->reg_list;
armv7m.c:183armv7m_restore_context()
struct reg *r = &cache->reg_list[i];
armv7m.c:337armv7m_read_core_reg()
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
armv7m.c:408armv7m_write_core_reg()
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
armv7m.c:475armv7m_get_gdb_reg_list()
(*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
armv7m.c:534armv7m_start_algorithm()
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
armv7m.c:591armv7m_start_algorithm()
struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
armv7m.c:607armv7m_start_algorithm()
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
armv7m.c:609armv7m_start_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m.c:610armv7m_start_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
armv7m.c:697armv7m_wait_algorithm()
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
armv7m.c:716armv7m_wait_algorithm()
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
armv7m.c:718armv7m_wait_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m.c:719armv7m_wait_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
armv7m.c:738armv7m_arch_state()
ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
armv7m.c:739armv7m_arch_state()
sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
armv7m.c:778armv7m_build_reg_cache()
cache->reg_list = reg_list;
armv7m.c:840armv7m_free_reg_cache()
reg = &cache->reg_list[i];
armv7m.c:846armv7m_free_reg_cache()
free(cache->reg_list[0].arch_info);
armv7m.c:847armv7m_free_reg_cache()
free(cache->reg_list);
armv8.c:684armv8_read_reg_simdfp_aarch32()
struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
armv8.c:818armv8_write_reg_simdfp_aarch32()
struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
armv8.c:1738armv8_get_core_reg32()
reg64 = cache->reg_list + armv8_reg->num;
armv8.c:1757armv8_set_core_reg32()
struct reg *reg64 = cache->reg_list + armv8_reg->num;
armv8.c:1805armv8_build_reg_cache()
cache->reg_list = reg_list;
armv8.c:1852armv8_build_reg_cache()
cache32->reg_list = reg_list32;
armv8.c:1891armv8_reg_current()
r = arm->core_cache->reg_list + regnum;
armv8.c:1904armv8_free_cache()
reg = &cache->reg_list[i];
armv8.c:1911armv8_free_cache()
free(cache->reg_list[0].arch_info);
armv8.c:1912armv8_free_cache()
free(cache->reg_list);
armv8.c:2002armv8_get_gdb_reg_list()
(*reg_list)[i] = cache32->reg_list + i;
armv8.c:2010armv8_get_gdb_reg_list()
(*reg_list)[i] = cache32->reg_list + i;
armv8_dpm.c:751armv8_dpm_read_current_registers()
r = cache->reg_list + ARMV8_R0;
armv8_dpm.c:760armv8_dpm_read_current_registers()
r = cache->reg_list + ARMV8_R1;
armv8_dpm.c:927armv8_dpm_write_dirty_registers()
if (!cache->reg_list[i].exist)
armv8_dpm.c:933armv8_dpm_write_dirty_registers()
if (!cache->reg_list[i].valid)
armv8_dpm.c:936armv8_dpm_write_dirty_registers()
if (!cache->reg_list[i].dirty)
armv8_dpm.c:940armv8_dpm_write_dirty_registers()
r = cache->reg_list[i].arch_info;
armv8_dpm.c:945armv8_dpm_write_dirty_registers()
retval = dpmv8_write_reg(dpm, &cache->reg_list[i], i);
armv8_dpm.c:952armv8_dpm_write_dirty_registers()
retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_XPSR], ARMV8_XPSR);
armv8_dpm.c:954armv8_dpm_write_dirty_registers()
retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
armv8_dpm.c:957armv8_dpm_write_dirty_registers()
retval = dpmv8_write_reg(dpm, &cache->reg_list[0], 0);
armv8_dpm.c:1054armv8_dpm_full_context()
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
armv8_dpm.c:1056armv8_dpm_full_context()
r = cache->reg_list[i].arch_info;
armv8_dpm.c:1080armv8_dpm_full_context()
&cache->reg_list[i],
armv8_dpm.c:1332armv8_dpm_handle_exception()
cache->reg_list[clobbered_regs_by_el[el-1][i]].dirty = true;
avr32_ap7k.c:65avr32_ap7k_save_context()
if (!ap7k->core_cache->reg_list[i].valid)
avr32_ap7k.c:80avr32_ap7k_restore_context()
if (ap7k->core_cache->reg_list[i].dirty)
avr32_ap7k.c:101avr32_read_core_reg()
buf_set_u32(ap7k->core_cache->reg_list[num].value, 0, 32, reg_value);
avr32_ap7k.c:102avr32_read_core_reg()
ap7k->core_cache->reg_list[num].valid = true;
avr32_ap7k.c:103avr32_read_core_reg()
ap7k->core_cache->reg_list[num].dirty = false;
avr32_ap7k.c:118avr32_write_core_reg()
reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32);
avr32_ap7k.c:121avr32_write_core_reg()
ap7k->core_cache->reg_list[num].valid = true;
avr32_ap7k.c:122avr32_write_core_reg()
ap7k->core_cache->reg_list[num].dirty = false;
avr32_ap7k.c:176avr32_build_reg_cache()
cache->reg_list = reg_list;
avr32_ap7k.c:332avr32_ap7k_resume()
resume_pc = buf_get_u32(ap7k->core_cache->reg_list[AVR32_REG_PC].value, 0, 32);
cortex_m.c:242cortex_m_slow_read_all_regs()
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
cortex_m.c:300cortex_m_fast_read_all_regs()
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
cortex_m.c:363cortex_m_fast_read_all_regs()
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
cortex_m.c:373cortex_m_fast_read_all_regs()
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
cortex_m.c:902cortex_m_debug_entry()
->reg_list[ARMV7M_CONTROL].value, 0, 3);
cortex_m.c:1323cortex_m_restore_one()
r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
cortex_m.c:2642cortex_m_dwt_setup()
cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
cortex_m.c:2643cortex_m_dwt_setup()
if (!cache->reg_list) {
cortex_m.c:2649cortex_m_dwt_setup()
cortex_m_dwt_addreg(target, cache->reg_list + reg,
cortex_m.c:2658cortex_m_dwt_setup()
cortex_m_dwt_addreg(target, cache->reg_list + reg,
cortex_m.c:2690cortex_m_dwt_free()
if (cache->reg_list) {
cortex_m.c:2692cortex_m_dwt_free()
free(cache->reg_list[i].arch_info);
cortex_m.c:2693cortex_m_dwt_free()
free(cache->reg_list);
cortex_m.c:2863cortex_m_examine()
armv7m->arm.core_cache->reg_list[idx].exist = false;
cortex_m.c:2867cortex_m_examine()
armv7m->arm.core_cache->reg_list[idx].exist = false;
dsp563xx.c:360dsp563xx_get_gdb_reg_list()
(*reg_list)[i] = &dsp563xx->core_cache->reg_list[gdb_reg_list_idx[i]];
dsp563xx.c:375dsp563xx_read_core_reg()
buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
dsp563xx.c:376dsp563xx_read_core_reg()
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx.c:377dsp563xx_read_core_reg()
dsp563xx->core_cache->reg_list[num].dirty = false;
dsp563xx.c:390dsp563xx_write_core_reg()
reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
dsp563xx.c:392dsp563xx_write_core_reg()
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx.c:393dsp563xx_write_core_reg()
dsp563xx->core_cache->reg_list[num].dirty = false;
dsp563xx.c:449dsp563xx_build_reg_cache()
cache->reg_list = reg_list;
dsp563xx.c:483dsp563xx_reg_read_high_io()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:501dsp563xx_reg_read_high_io()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
dsp563xx.c:513dsp563xx_reg_write_high_io()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:527dsp563xx_reg_write_high_io()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
dsp563xx.c:565dsp563xx_reg_pc_read()
if (dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty)
dsp563xx.c:606dsp563xx_reg_ssh_read()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
dsp563xx.c:666dsp563xx_reg_ssh_write()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
dsp563xx.c:708dsp563xx_reg_ssl_read()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info;
dsp563xx.c:738dsp563xx_read_register()
dsp563xx->core_cache->reg_list[num].valid = false;
dsp563xx.c:740dsp563xx_read_register()
if (!dsp563xx->core_cache->reg_list[num].valid) {
dsp563xx.c:741dsp563xx_read_register()
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
dsp563xx.c:788dsp563xx_write_register()
dsp563xx->core_cache->reg_list[num].dirty = true;
dsp563xx.c:790dsp563xx_write_register()
if (dsp563xx->core_cache->reg_list[num].dirty) {
dsp563xx.c:791dsp563xx_write_register()
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
dsp563xx.c:820dsp563xx_write_register()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid =
dsp563xx.c:822dsp563xx_write_register()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid =
dsp563xx.c:873dsp563xx_invalidate_x_context()
arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
dsp563xx.c:877dsp563xx_invalidate_x_context()
dsp563xx->core_cache->reg_list[i].valid = false;
dsp563xx.c:878dsp563xx_invalidate_x_context()
dsp563xx->core_cache->reg_list[i].dirty = false;
dsp563xx.c:963dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info;
dsp563xx.c:978dsp563xx_debug_init()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true;
dsp563xx.c:995dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info;
dsp563xx.c:1000dsp563xx_debug_init()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true;
dsp563xx.c:1003dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
dsp563xx.c:1008dsp563xx_debug_init()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true;
dsp563xx.c:1011dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
dsp563xx.c:1016dsp563xx_debug_init()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true;
dsp563xx.c:1019dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
dsp563xx.c:1024dsp563xx_debug_init()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true;
dsp563xx.c:1132dsp563xx_resume()
if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
dsp563xx.c:1196dsp563xx_step_ex()
if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
dsp563xx.c:1547dsp563xx_read_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:1550dsp563xx_read_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
dsp563xx.c:1554dsp563xx_read_memory_core()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
dsp563xx.c:1556dsp563xx_read_memory_core()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
dsp563xx.c:1729dsp563xx_write_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:1732dsp563xx_write_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
dsp563xx.c:1736dsp563xx_write_memory_core()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
dsp563xx.c:1738dsp563xx_write_memory_core()
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
embeddedice.c:185embeddedice_build_reg_cache()
reg_cache->reg_list = reg_list;
embeddedice.c:304embeddedice_free_reg_cache()
free(reg_cache->reg_list[i].value);
embeddedice.c:306embeddedice_free_reg_cache()
free(reg_cache->reg_list[0].arch_info);
embeddedice.c:307embeddedice_free_reg_cache()
free(reg_cache->reg_list);
embeddedice.c:325embeddedice_setup()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
esirisc.c:287esirisc_save_context()
struct reg *reg = esirisc->reg_cache->reg_list + i;
esirisc.c:304esirisc_restore_context()
struct reg *reg = esirisc->reg_cache->reg_list + i;
esirisc.c:1285esirisc_get_gdb_reg_list()
(*reg_list)[i] = esirisc->reg_cache->reg_list + i;
esirisc.c:1288esirisc_get_gdb_reg_list()
(*reg_list)[i] = esirisc->reg_cache->reg_list + i;
esirisc.c:1290esirisc_get_gdb_reg_list()
(*reg_list)[ESIRISC_PC] = esirisc->reg_cache->reg_list + ESIRISC_PC;
esirisc.c:1291esirisc_get_gdb_reg_list()
(*reg_list)[ESIRISC_CAS] = esirisc->reg_cache->reg_list + ESIRISC_CAS;
esirisc.c:1436esirisc_build_reg_cache()
cache->reg_list = reg_list;
esirisc.c:1493esirisc_free_reg_cache()
struct reg *reg_list = cache->reg_list;
etb.c:128etb_build_reg_cache()
reg_cache->reg_list = reg_list;
etb.c:445etb_init()
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
etb.c:446etb_init()
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
etb.c:449etb_init()
etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
etb.c:450etb_init()
etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
etb.c:460etb_status()
struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
etb.c:461etb_status()
struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
etb.c:517etb_read_trace()
etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
etb.c:518etb_read_trace()
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
etb.c:525etb_read_trace()
if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
etb.c:526etb_read_trace()
first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value,
etb.c:530etb_read_trace()
num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value,
etb.c:534etb_read_trace()
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
etb.c:660etb_start_capture()
etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
etb.c:661etb_start_capture()
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
etb.c:662etb_start_capture()
etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
etb.c:674etb_stop_capture()
struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
etm.c:229etm_reg_lookup()
struct etm_reg *reg = cache->reg_list[i].arch_info;
etm.c:232etm_reg_lookup()
return &cache->reg_list[i];
etm.c:245etm_reg_add()
struct reg *reg = cache->reg_list;
etm.c:298etm_build_reg_cache()
reg_cache->reg_list = reg_list;
feroceon.c:336feroceon_branch_resume_thumb()
uint32_t r0 = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
feroceon.c:411feroceon_set_dbgrq()
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
feroceon.c:423feroceon_enable_single_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
feroceon.c:424feroceon_enable_single_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0);
feroceon.c:425feroceon_enable_single_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
feroceon.c:426feroceon_enable_single_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
feroceon.c:427feroceon_enable_single_step()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
feroceon.c:435feroceon_disable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
feroceon.c:436feroceon_disable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
feroceon.c:437feroceon_disable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
feroceon.c:438feroceon_disable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
feroceon.c:439feroceon_disable_single_step()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
feroceon.c:519feroceon_bulk_write_memory()
save[i] = buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32);
feroceon.c:523feroceon_bulk_write_memory()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
feroceon.c:524feroceon_bulk_write_memory()
arm->core_cache->reg_list[0].valid = true;
feroceon.c:525feroceon_bulk_write_memory()
arm->core_cache->reg_list[0].dirty = true;
feroceon.c:528feroceon_bulk_write_memory()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
feroceon.c:538feroceon_bulk_write_memory()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
feroceon.c:542feroceon_bulk_write_memory()
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
feroceon.c:554feroceon_bulk_write_memory()
buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
feroceon.c:566feroceon_bulk_write_memory()
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
feroceon.c:567feroceon_bulk_write_memory()
arm->core_cache->reg_list[i].valid = true;
feroceon.c:568feroceon_bulk_write_memory()
arm->core_cache->reg_list[i].dirty = true;
feroceon.c:671feroceon_examine()
if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
feroceon.c:674feroceon_examine()
arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
feroceon.c:675feroceon_examine()
arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
feroceon.c:679feroceon_examine()
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
feroceon.c:682feroceon_examine()
embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
feroceon.c:684feroceon_examine()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
feroceon.c:685feroceon_examine()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
feroceon.c:686feroceon_examine()
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
hla_target.c:220adapter_load_context()
struct reg *r = &armv7m->arm.core_cache->reg_list[i];
hla_target.c:262adapter_debug_entry()
->reg_list[ARMV7M_CONTROL].value, 0, 3);
lakemont.c:314restore_context()
x86_32->cache->reg_list[i].dirty = false;
lakemont.c:315restore_context()
x86_32->cache->reg_list[i].valid = false;
lakemont.c:384lakemont_build_reg_cache()
cache->reg_list = reg_list;
lakemont.c:504halt_prep()
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
lakemont.c:505halt_prep()
uint32_t csar = buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32);
lakemont.c:506halt_prep()
uint32_t ssar = buf_get_u32(x86_32->cache->reg_list[SSAR].value, 0, 32);
lakemont.c:507halt_prep()
uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
lakemont.c:514halt_prep()
x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
lakemont.c:515halt_prep()
if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
lakemont.c:518halt_prep()
x86_32->pm_regs[I(EFLAGS)],
lakemont.c:519halt_prep()
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
lakemont.c:520halt_prep()
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
lakemont.c:525halt_prep()
x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
lakemont.c:526halt_prep()
if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
lakemont.c:528halt_prep()
LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
lakemont.c:531halt_prep()
x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;
lakemont.c:532halt_prep()
if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
lakemont.c:534halt_prep()
LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
lakemont.c:541halt_prep()
x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
lakemont.c:542halt_prep()
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
lakemont.c:544halt_prep()
LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:548halt_prep()
x86_32->pm_regs[I(CR0)] =
lakemont.c:549halt_prep()
x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
lakemont.c:550halt_prep()
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
lakemont.c:552halt_prep()
LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:608read_all_core_hw_regs()
__func__, x86_32->cache->reg_list[i].name);
lakemont.c:627write_all_core_hw_regs()
__func__, x86_32->cache->reg_list[i].name);
lakemont.c:640read_hw_reg()
arch_info = x86_32->cache->reg_list[reg].arch_info;
lakemont.c:658read_hw_reg()
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
lakemont.c:659read_hw_reg()
x86_32->cache->reg_list[reg].valid = true;
lakemont.c:660read_hw_reg()
x86_32->cache->reg_list[reg].dirty = false;
lakemont.c:663read_hw_reg()
x86_32->cache->reg_list[reg].name,
lakemont.c:674write_hw_reg()
arch_info = x86_32->cache->reg_list[reg].arch_info;
lakemont.c:678write_hw_reg()
regval = buf_get_u32(x86_32->cache->reg_list[reg].value, 0, 32);
lakemont.c:681write_hw_reg()
x86_32->cache->reg_list[reg].name,
lakemont.c:701write_hw_reg()
x86_32->cache->reg_list[reg].dirty = false;
lakemont.c:702write_hw_reg()
x86_32->cache->reg_list[reg].valid = false;
lakemont.c:710is_paging_enabled()
if (x86_32->pm_regs[I(CR0)] & CR0_PG)
lakemont.c:725disable_paging()
x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;
lakemont.c:726disable_paging()
int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
lakemont.c:737enable_paging()
x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);
lakemont.c:738enable_paging()
int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
lakemont.c:886lakemont_poll()
uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
lakemont.c:887lakemont_poll()
uint32_t dr6 = buf_get_u32(x86_32->cache->reg_list[DR6].value, 0, 32);
lakemont.c:900lakemont_poll()
uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
lakemont.c:909lakemont_poll()
address = buf_get_u32(x86_32->cache->reg_list[DR0].value, 0, 32);
lakemont.c:912lakemont_poll()
address = buf_get_u32(x86_32->cache->reg_list[DR1].value, 0, 32);
lakemont.c:915lakemont_poll()
address = buf_get_u32(x86_32->cache->reg_list[DR2].value, 0, 32);
lakemont.c:918lakemont_poll()
address = buf_get_u32(x86_32->cache->reg_list[DR3].value, 0, 32);
lakemont.c:938lakemont_poll()
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
lakemont.c:939lakemont_poll()
x86_32->cache->reg_list[EIP].dirty = true;
lakemont.c:940lakemont_poll()
x86_32->cache->reg_list[EIP].valid = true;
lakemont.c:972lakemont_arch_state()
buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32),
lakemont.c:973lakemont_arch_state()
(buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32) & CR0_PE) ? "protected" : "real");
lakemont.c:1003lakemont_resume()
uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
lakemont.c:1022lakemont_resume()
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
lakemont.c:1036lakemont_step()
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
lakemont.c:1037lakemont_step()
uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
lakemont.c:1038lakemont_step()
uint32_t pmcr = buf_get_u32(x86_32->cache->reg_list[PMCR].value, 0, 32);
lakemont.c:1057lakemont_step()
buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
lakemont.c:1058lakemont_step()
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
lakemont.c:1084lakemont_step()
buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32));
mips32.c:275mips32_set_all_fpr_width()
struct reg *reg_list = cache->reg_list;
mips32.c:335mips32_read_core_reg()
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32.c:342mips32_read_core_reg()
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32.c:347mips32_read_core_reg()
buf_set_u64(mips32->core_cache->reg_list[num].value, 0, 64, reg_value);
mips32.c:352mips32_read_core_reg()
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32.c:355mips32_read_core_reg()
mips32->core_cache->reg_list[num].valid = true;
mips32.c:356mips32_read_core_reg()
mips32->core_cache->reg_list[num].dirty = false;
mips32.c:377mips32_write_core_reg()
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32.c:384mips32_write_core_reg()
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32.c:389mips32_write_core_reg()
reg_value = buf_get_u64(mips32->core_cache->reg_list[num].value, 0, 64);
mips32.c:394mips32_write_core_reg()
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32.c:399mips32_write_core_reg()
mips32->core_cache->reg_list[num].valid = true;
mips32.c:400mips32_write_core_reg()
mips32->core_cache->reg_list[num].dirty = false;
mips32.c:417mips32_get_gdb_reg_list()
(*reg_list)[i] = &mips32->core_cache->reg_list[i];
mips32.c:437mips32_save_context()
if (!mips32->core_cache->reg_list[i].valid)
mips32.c:452mips32_restore_context()
if (mips32->core_cache->reg_list[i].dirty)
mips32.c:467mips32_arch_state()
buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
mips32.c:493mips32_build_reg_cache()
cache->reg_list = reg_list;
mips32.c:586mips32_run_and_wait()
pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
mips32.c:624mips32_run_algorithm()
if (!mips32->core_cache->reg_list[i].valid)
mips32.c:626mips32_run_algorithm()
context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
mips32.c:695mips32_run_algorithm()
regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
mips32.c:698mips32_run_algorithm()
mips32->core_cache->reg_list[i].name, context[i]);
mips32.c:699mips32_run_algorithm()
buf_set_u32(mips32->core_cache->reg_list[i].value,
mips32.c:701mips32_run_algorithm()
mips32->core_cache->reg_list[i].valid = true;
mips32.c:702mips32_run_algorithm()
mips32->core_cache->reg_list[i].dirty = true;
mips32.c:1555mips32_cp0_set_reg_by_name()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
mips32.c:1559mips32_cp0_set_reg_by_name()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
mips32.c:1563mips32_cp0_set_reg_by_name()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
mips32.c:1567mips32_cp0_set_reg_by_name()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
mips32.c:1606mips32_cp0_set_reg_by_number()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
mips32.c:1610mips32_cp0_set_reg_by_number()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
mips32.c:1614mips32_cp0_set_reg_by_number()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
mips32.c:1618mips32_cp0_set_reg_by_number()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
mips64.c:267mips64_read_core_reg()
buf_set_u64(mips64->core_cache->reg_list[num].value, 0, 64, reg_value);
mips64.c:268mips64_read_core_reg()
mips64->core_cache->reg_list[num].valid = true;
mips64.c:269mips64_read_core_reg()
mips64->core_cache->reg_list[num].dirty = false;
mips64.c:284mips64_write_core_reg()
reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
mips64.c:287mips64_write_core_reg()
mips64->core_cache->reg_list[num].valid = true;
mips64.c:288mips64_write_core_reg()
mips64->core_cache->reg_list[num].dirty = false;
mips64.c:300mips64_invalidate_core_regs()
mips64->core_cache->reg_list[i].valid = false;
mips64.c:301mips64_invalidate_core_regs()
mips64->core_cache->reg_list[i].dirty = false;
mips64.c:320mips64_get_gdb_reg_list()
(*reg_list)[i] = &mips64->core_cache->reg_list[i];
mips64.c:347mips64_restore_context()
if (mips64->core_cache->reg_list[i].dirty)
mips64.c:357mips64_arch_state()
struct reg *pc = &mips64->core_cache->reg_list[MIPS64_PC];
mips64.c:426mips64_build_reg_cache()
cache->reg_list = reg_list;
mips_m4k.c:111mips_m4k_debug_entry()
if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1))
mips_m4k.c:115mips_m4k_debug_entry()
buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32),
mips_m4k.c:446mips_m4k_internal_restore()
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
mips_m4k.c:447mips_m4k_internal_restore()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true;
mips_m4k.c:448mips_m4k_internal_restore()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
mips_m4k.c:452mips_m4k_internal_restore()
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode);
mips_m4k.c:457mips_m4k_internal_restore()
resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
mips_m4k.c:540mips_m4k_step()
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
mips_m4k.c:541mips_m4k_step()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true;
mips_m4k.c:542mips_m4k_step()
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
mips_m4k.c:548mips_m4k_step()
buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
mips_mips64.c:51mips_mips64_debug_entry()
struct reg *pc = &mips64->core_cache->reg_list[MIPS64_PC];
mips_mips64.c:624mips_mips64_resume()
pc = &mips64->core_cache->reg_list[MIPS64_PC];
mips_mips64.c:704mips_mips64_step()
struct reg *pc = &mips64->core_cache->reg_list[MIPS64_PC];
or1k.c:339or1k_save_context()
if (!or1k->core_cache->reg_list[i].valid) {
or1k.c:373or1k_restore_context()
if (or1k->core_cache->reg_list[i].dirty) {
or1k.c:414or1k_read_core_reg()
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
or1k.c:416or1k_read_core_reg()
or1k->core_cache->reg_list[num].valid = true;
or1k.c:417or1k_read_core_reg()
or1k->core_cache->reg_list[num].dirty = false;
or1k.c:426or1k_read_core_reg()
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
or1k.c:442or1k_write_core_reg()
uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
or1k.c:445or1k_write_core_reg()
or1k->core_cache->reg_list[num].valid = true;
or1k.c:446or1k_write_core_reg()
or1k->core_cache->reg_list[num].dirty = false;
or1k.c:514or1k_build_reg_cache()
cache->reg_list = reg_list;
or1k.c:559or1k_debug_entry()
retval = or1k_set_core_reg(&or1k->core_cache->reg_list[OR1K_REG_NPC],
or1k.c:801or1k_resume_or_step()
buf_set_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value, 0,
or1k.c:845or1k_resume_or_step()
resume_pc = buf_get_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value,
or1k.c:1179or1k_get_gdb_reg_list()
(*reg_list)[i] = &or1k->core_cache->reg_list[i];
or1k.c:1185or1k_get_gdb_reg_list()
(*reg_list)[i] = &or1k->core_cache->reg_list[i];
register.c:35register_get_by_number()
if (!cache->reg_list[i].exist)
register.c:37register_get_by_number()
if (cache->reg_list[i].number == reg_num)
register.c:38register_get_by_number()
return &(cache->reg_list[i]);
register.c:57register_get_by_name()
if (!cache->reg_list[i].exist)
register.c:59register_get_by_name()
if (strcmp(cache->reg_list[i].name, name) == 0)
register.c:60register_get_by_name()
return &(cache->reg_list[i]);
register.c:97register_cache_invalidate()
struct reg *reg = &cache->reg_list[n];
riscv-011.c:1127execute_resume()
struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
riscv-011.c:1207reg_cache_get()
struct reg *r = &target->reg_cache->reg_list[number];
riscv-011.c:1220reg_cache_set()
struct reg *r = &target->reg_cache->reg_list[number];
riscv-011.c:1228update_mstatus_actual()
struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
riscv-011.c:1380get_register()
target->reg_cache->reg_list[regid].valid = true;
riscv-013.c:880access_register_command()
riscv_reg_info_t *reg_info = target->reg_cache->reg_list[number].arch_info;
riscv-013.c:1279register_size()
return target->reg_cache->reg_list[number].size;
riscv-013.c:1376register_write_direct()
struct reg *reg = &target->reg_cache->reg_list[number];
riscv-013.c:1404register_read()
struct reg *reg = &target->reg_cache->reg_list[number];
riscv.c:476riscv_free_registers()
if (target->reg_cache->reg_list) {
riscv.c:477riscv_free_registers()
free(target->reg_cache->reg_list[0].arch_info);
riscv.c:480riscv_free_registers()
free(target->reg_cache->reg_list[i].arch_info);
riscv.c:482riscv_free_registers()
free(target->reg_cache->reg_list[i].value);
riscv.c:483riscv_free_registers()
free(target->reg_cache->reg_list);
riscv.c:1794riscv_get_gdb_reg_list_internal()
(*reg_list)[i] = &target->reg_cache->reg_list[i];
riscv.c:1796riscv_get_gdb_reg_list_internal()
target->reg_cache->reg_list[i].exist &&
riscv.c:1797riscv_get_gdb_reg_list_internal()
!target->reg_cache->reg_list[i].valid) {
riscv.c:1798riscv_get_gdb_reg_list_internal()
if (target->reg_cache->reg_list[i].type->get(
riscv.c:1799riscv_get_gdb_reg_list_internal()
&target->reg_cache->reg_list[i]) != ERROR_OK)
riscv.c:3234riscv_invalidate_register_cache()
struct reg *reg = &target->reg_cache->reg_list[i];
riscv.c:3321riscv_set_register()
struct reg *reg = &target->reg_cache->reg_list[regid];
riscv.c:3341riscv_get_register()
struct reg *reg = &target->reg_cache->reg_list[regid];
riscv.c:3811riscv_init_registers()
target->reg_cache->reg_list =
riscv.c:3813riscv_init_registers()
if (!target->reg_cache->reg_list)
riscv.c:3976riscv_init_registers()
struct reg *r = &target->reg_cache->reg_list[number];
stm8.c:474stm8_debug_entry()
buf_get_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32),
stm8.c:582stm8_save_context()
if (!stm8->core_cache->reg_list[i].valid)
stm8.c:597stm8_restore_context()
if (stm8->core_cache->reg_list[i].dirty)
stm8.c:1012stm8_resume()
buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value,
stm8.c:1014stm8_resume()
stm8->core_cache->reg_list[STM8_PC].dirty = true;
stm8.c:1015stm8_resume()
stm8->core_cache->reg_list[STM8_PC].valid = true;
stm8.c:1022stm8_resume()
stm8->core_cache->reg_list[STM8_PC].value,
stm8.c:1135stm8_read_core_reg()
buf_set_u32(stm8->core_cache->reg_list[num].value, 0, 32, reg_value);
stm8.c:1136stm8_read_core_reg()
stm8->core_cache->reg_list[num].valid = true;
stm8.c:1137stm8_read_core_reg()
stm8->core_cache->reg_list[num].dirty = false;
stm8.c:1152stm8_write_core_reg()
reg_value = buf_get_u32(stm8->core_cache->reg_list[num].value, 0, 32);
stm8.c:1155stm8_write_core_reg()
stm8->core_cache->reg_list[num].valid = true;
stm8.c:1156stm8_write_core_reg()
stm8->core_cache->reg_list[num].dirty = false;
stm8.c:1177stm8_get_gdb_reg_list()
(*reg_list)[i] = &stm8->core_cache->reg_list[i];
stm8.c:1204stm8_build_reg_cache()
cache->reg_list = reg_list;
stm8.c:1259stm8_free_reg_cache()
reg = &cache->reg_list[i];
stm8.c:1266stm8_free_reg_cache()
free(cache->reg_list[0].arch_info);
stm8.c:1267stm8_free_reg_cache()
free(cache->reg_list);
stm8.c:1290stm8_arch_state()
buf_get_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32));
stm8.c:1312stm8_step()
buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32, address);
stm8.c:1313stm8_step()
stm8->core_cache->reg_list[STM8_PC].dirty = true;
stm8.c:1314stm8_step()
stm8->core_cache->reg_list[STM8_PC].valid = true;
stm8.c:1320stm8_step()
buf_get_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32));
stm8.c:1810stm8_run_and_wait()
pc = buf_get_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32);
stm8.c:1847stm8_run_algorithm()
if (!stm8->core_cache->reg_list[i].valid)
stm8.c:1849stm8_run_algorithm()
context[i] = buf_get_u32(stm8->core_cache->reg_list[i].value, 0, 32);
stm8.c:1921stm8_run_algorithm()
regvalue = buf_get_u32(stm8->core_cache->reg_list[i].value, 0, 32);
stm8.c:1924stm8_run_algorithm()
stm8->core_cache->reg_list[i].name, context[i]);
stm8.c:1925stm8_run_algorithm()
buf_set_u32(stm8->core_cache->reg_list[i].value,
stm8.c:1927stm8_run_algorithm()
stm8->core_cache->reg_list[i].valid = true;
stm8.c:1928stm8_run_algorithm()
stm8->core_cache->reg_list[i].dirty = true;
target.c:3052handle_reg_command()
for (i = 0, reg = cache->reg_list;
target.c:3092handle_reg_command()
reg = &cache->reg_list[i];
x86_32_common.c:73x86_32_get_gdb_reg_list()
(*reg_list)[i] = &x86_32->cache->reg_list[i];
x86_32_common.c:74x86_32_get_gdb_reg_list()
LOG_DEBUG("value %s = %08" PRIx32, x86_32->cache->reg_list[i].name,
x86_32_common.c:75x86_32_get_gdb_reg_list()
buf_get_u32(x86_32->cache->reg_list[i].value, 0, 32));
x86_32_common.c:117x86_32_common_virt2phys()
uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
x86_32_common.c:121x86_32_common_virt2phys()
uint32_t dsb = buf_get_u32(x86_32->cache->reg_list[DSB].value, 0, 32);
x86_32_common.c:326read_mem()
bool use32 = (buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32)) & CSAR_D;
x86_32_common.c:394write_mem()
bool use32 = (buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32)) & CSAR_D;
x86_32_common.c:456calcaddr_physfromlin()
uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
x86_32_common.c:463calcaddr_physfromlin()
uint32_t cr4 = buf_get_u32(x86_32->cache->reg_list[CR4].value, 0, 32);
x86_32_common.c:466calcaddr_physfromlin()
uint32_t cr3 = buf_get_u32(x86_32->cache->reg_list[CR3].value, 0, 32);
x86_32_common.c:685x86_32_common_read_io()
bool use32 = (buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32)) & CSAR_D;
x86_32_common.c:765x86_32_common_write_io()
bool use32 = (buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32)) & CSAR_D;
x86_32_common.c:889set_debug_regs()
uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
x86_32_common.c:930set_debug_regs()
buf_set_u32(x86_32->cache->reg_list[bp_num+DR0].value, 0, 32, address);
x86_32_common.c:931set_debug_regs()
x86_32->cache->reg_list[bp_num+DR0].dirty = true;
x86_32_common.c:932set_debug_regs()
x86_32->cache->reg_list[bp_num+DR0].valid = true;
x86_32_common.c:933set_debug_regs()
buf_set_u32(x86_32->cache->reg_list[DR6].value, 0, 32, PM_DR6);
x86_32_common.c:934set_debug_regs()
x86_32->cache->reg_list[DR6].dirty = true;
x86_32_common.c:935set_debug_regs()
x86_32->cache->reg_list[DR6].valid = true;
x86_32_common.c:936set_debug_regs()
buf_set_u32(x86_32->cache->reg_list[DR7].value, 0, 32, dr7);
x86_32_common.c:937set_debug_regs()
x86_32->cache->reg_list[DR7].dirty = true;
x86_32_common.c:938set_debug_regs()
x86_32->cache->reg_list[DR7].valid = true;
x86_32_common.c:947unset_debug_regs()
uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
x86_32_common.c:961unset_debug_regs()
buf_set_u32(x86_32->cache->reg_list[bp_num+DR0].value, 0, 32, 0);
x86_32_common.c:962unset_debug_regs()
x86_32->cache->reg_list[bp_num+DR0].dirty = true;
x86_32_common.c:963unset_debug_regs()
x86_32->cache->reg_list[bp_num+DR0].valid = true;
x86_32_common.c:964unset_debug_regs()
buf_set_u32(x86_32->cache->reg_list[DR6].value, 0, 32, PM_DR6);
x86_32_common.c:965unset_debug_regs()
x86_32->cache->reg_list[DR6].dirty = true;
x86_32_common.c:966unset_debug_regs()
x86_32->cache->reg_list[DR6].valid = true;
x86_32_common.c:967unset_debug_regs()
buf_set_u32(x86_32->cache->reg_list[DR7].value, 0, 32, dr7);
x86_32_common.c:968unset_debug_regs()
x86_32->cache->reg_list[DR7].dirty = true;
x86_32_common.c:969unset_debug_regs()
x86_32->cache->reg_list[DR7].valid = true;
x86_32_common.c:1307read_hw_reg_to_cache()
LOG_ERROR("%s fail for %s", x86_32->cache->reg_list[num].name, __func__);
x86_32_common.c:1311read_hw_reg_to_cache()
x86_32->cache->reg_list[num].name, reg_value);
x86_32_common.c:1323write_hw_reg_from_cache()
LOG_ERROR("%s fail for %s", x86_32->cache->reg_list[num].name, __func__);
x86_32_common.c:1326write_hw_reg_from_cache()
LOG_DEBUG("reg %s value 0x%08" PRIx32, x86_32->cache->reg_list[num].name,
x86_32_common.c:1327write_hw_reg_from_cache()
buf_get_u32(x86_32->cache->reg_list[num].value, 0, 32));
xscale.c:186xscale_read_dcsr()
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
xscale.c:204xscale_read_dcsr()
xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
xscale.c:205xscale_read_dcsr()
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
xscale.c:211xscale_read_dcsr()
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
xscale.c:365xscale_read_tx()
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
xscale.c:441xscale_write_rx()
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
xscale.c:561xscale_send_u32()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
xscale.c:598xscale_write_dcsr()
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
xscale.c:616xscale_write_dcsr()
xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
xscale.c:617xscale_write_dcsr()
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
xscale.c:859xscale_debug_entry()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
xscale.c:860xscale_debug_entry()
arm->core_cache->reg_list[0].dirty = true;
xscale.c:861xscale_debug_entry()
arm->core_cache->reg_list[0].valid = true;
xscale.c:872xscale_debug_entry()
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
xscale.c:873xscale_debug_entry()
arm->core_cache->reg_list[i].dirty = true;
xscale.c:874xscale_debug_entry()
arm->core_cache->reg_list[i].valid = true;
xscale.c:912xscale_debug_entry()
xscale->reg_cache->reg_list[i].valid = false;
xscale.c:916xscale_debug_entry()
moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
xscale.c:972xscale_debug_entry()
xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
xscale.c:973xscale_debug_entry()
cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value,
xscale.c:982xscale_debug_entry()
xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
xscale.c:984xscale_debug_entry()
buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
xscale.c:1038xscale_enable_single_step()
struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
xscale.c:1064xscale_disable_single_step()
struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
xscale.c:1189xscale_resume()
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
xscale.c:1191xscale_resume()
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
xscale.c:1253xscale_resume()
xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
xscale.c:1255xscale_resume()
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
xscale.c:1340xscale_step_inner()
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
xscale.c:1344xscale_step_inner()
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
xscale.c:1461xscale_assert_reset()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale.c:1462xscale_assert_reset()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale.c:1532xscale_deassert_reset()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale.c:1533xscale_deassert_reset()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale.c:1585xscale_deassert_reset()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale.c:1586xscale_deassert_reset()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale.c:1656xscale_full_context()
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1674xscale_full_context()
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1687xscale_full_context()
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1726xscale_restore_banked()
if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1733xscale_restore_banked()
if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1752xscale_restore_banked()
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1760xscale_restore_banked()
r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1844xscale_read_memory()
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
xscale.c:1942xscale_write_memory()
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
xscale.c:1976xscale_get_ttb()
retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
xscale.c:1979xscale_get_ttb()
ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
xscale.c:1994xscale_disable_mmu_caches()
retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
xscale.c:1997xscale_disable_mmu_caches()
cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
xscale.c:2028xscale_disable_mmu_caches()
retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
xscale.c:2045xscale_enable_mmu_caches()
retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
xscale.c:2048xscale_enable_mmu_caches()
cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
xscale.c:2060xscale_enable_mmu_caches()
retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
xscale.c:2088xscale_set_breakpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
xscale.c:2093xscale_set_breakpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
xscale.c:2177xscale_unset_breakpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
xscale.c:2180xscale_unset_breakpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
xscale.c:2231xscale_set_watchpoint()
struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
xscale.c:2263xscale_set_watchpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
xscale.c:2270xscale_set_watchpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
xscale.c:2276xscale_set_watchpoint()
xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
xscale.c:2335xscale_unset_watchpoint()
struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
xscale.c:2414xscale_get_reg()
buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
xscale.c:2432xscale_set_reg()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
xscale.c:2435xscale_set_reg()
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
xscale.c:2461xscale_write_dcsr_sw()
struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
xscale.c:2876xscale_build_reg_cache()
(*cache_p)->reg_list = calloc(num_regs, sizeof(struct reg));
xscale.c:2880xscale_build_reg_cache()
(*cache_p)->reg_list[i].name = xscale_reg_list[i];
xscale.c:2881xscale_build_reg_cache()
(*cache_p)->reg_list[i].value = calloc(4, 1);
xscale.c:2882xscale_build_reg_cache()
(*cache_p)->reg_list[i].dirty = false;
xscale.c:2883xscale_build_reg_cache()
(*cache_p)->reg_list[i].valid = false;
xscale.c:2884xscale_build_reg_cache()
(*cache_p)->reg_list[i].size = 32;
xscale.c:2885xscale_build_reg_cache()
(*cache_p)->reg_list[i].arch_info = &arch_info[i];
xscale.c:2886xscale_build_reg_cache()
(*cache_p)->reg_list[i].type = &xscale_reg_type;
xscale.c:2887xscale_build_reg_cache()
(*cache_p)->reg_list[i].exist = true;
xscale.c:2901xscale_free_reg_cache()
free(cache->reg_list[i].value);
xscale.c:2903xscale_free_reg_cache()
free(cache->reg_list[0].arch_info);
xscale.c:2904xscale_free_reg_cache()
free(cache->reg_list);
xscale.c:3236xscale_handle_vector_catch_command()
struct reg *dcsr_reg = &xscale->reg_cache->reg_list[XSCALE_DCSR];
xscale.c:3392xscale_handle_trace_buffer_command()
dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
xscale.c:3554xscale_handle_cp15()
reg = &xscale->reg_cache->reg_list[reg_no];
xtensa.c:523xtensa_mark_register_dirty()
struct reg *reg_list = xtensa->core_cache->reg_list;
xtensa.c:669xtensa_write_dirty_registers()
struct reg *reg_list = xtensa->core_cache->reg_list;
xtensa.c:995xtensa_imprecise_exception_occurred()
xtensa->core_cache->reg_list[ridx].name, reg);
xtensa.c:1012xtensa_imprecise_exception_clear()
xtensa->core_cache->reg_list[ridx].name, value);
xtensa.c:1066xtensa_reg_get()
struct reg *reg = &xtensa->core_cache->reg_list[reg_id];
xtensa.c:1073xtensa_reg_set()
struct reg *reg = &xtensa->core_cache->reg_list[reg_id];
xtensa.c:1147xtensa_cause_clear()
xtensa->core_cache->reg_list[XT_REG_IDX_DEBUGCAUSE].dirty = false;
xtensa.c:1213xtensa_fetch_all_regs()
struct reg *reg_list = xtensa->core_cache->reg_list;
xtensa.c:1526xtensa_get_gdb_reg_list()
if (xtensa->core_cache->reg_list[i].exist) {
xtensa.c:1535xtensa_get_gdb_reg_list()
(*reg_list)[sparse_idx] = &xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx];
xtensa.c:1541xtensa_get_gdb_reg_list()
(*reg_list)[sparse_idx - XT_REG_IDX_ARFIRST] = &xtensa->core_cache->reg_list[i];
xtensa.c:1543xtensa_get_gdb_reg_list()
(*reg_list)[sparse_idx] = &xtensa->core_cache->reg_list[i];
xtensa.c:1547xtensa_get_gdb_reg_list()
(*reg_list)[XT_PC_DBREG_NUM_BASE] = &xtensa->core_cache->reg_list[i];
xtensa.c:1823xtensa_do_step()
xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx].name,
xtensa.c:1921xtensa_do_step()
xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx].name,
xtensa.c:2733xtensa_start_algorithm()
struct reg *reg = &xtensa->core_cache->reg_list[i];
xtensa.c:2778xtensa_start_algorithm()
reg = &xtensa->core_cache->reg_list[reg_id];
xtensa.c:2795xtensa_start_algorithm()
xtensa->core_cache->reg_list[eps_reg_idx].valid = 1;
xtensa.c:2868xtensa_wait_algorithm()
struct reg *reg = &xtensa->core_cache->reg_list[i];
xtensa.c:2875xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].name,
xtensa.c:2879xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].dirty = 0;
xtensa.c:2880xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].valid = 0;
xtensa.c:2884xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].name,
xtensa.c:2889xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].name,
xtensa.c:2893xtensa_wait_algorithm()
LOG_DEBUG("restoring register %s %u-bits", xtensa->core_cache->reg_list[i].name, reg->size);
xtensa.c:2896xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].dirty = 1;
xtensa.c:2897xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].valid = 1;
xtensa.c:2994xtensa_build_reg_cache()
reg_cache->reg_list = reg_list;
xtensa.c:3033xtensa_build_reg_cache()
if (!strcmp(reg_cache->reg_list[j].name, xtensa->contiguous_regs_desc[i]->name)) {
xtensa.c:3039xtensa_build_reg_cache()
reg_cache->reg_list[j].number = i;
xtensa.c:3040xtensa_build_reg_cache()
xtensa->contiguous_regs_list[i] = &(reg_cache->reg_list[j]);
xtensa.c:3060xtensa_build_reg_cache()
struct reg *reg = &reg_cache->reg_list[i];
xtensa.c:3460xtensa_free_reg_cache()
free(cache->reg_list[i].value);
xtensa.c:3463xtensa_free_reg_cache()
free(cache->reg_list);

Data Use

Functions writing reg_cache::reg_list
Functions reading reg_cache::reg_list
all items filtered out
reg_cache::reg_list
all items filtered out
Type of reg_cache::reg_list
reg_cache::reg_list
all items filtered out