ARMV4_5_CORE_REG_MODE - syntax, references, description

References

Location	Text
armv4_5.h:32	#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
arm7_9_common.c:1415	if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid)
arm7_9_common.c:1430	if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1432	read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(
arm7_9_common.c:1439	ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1442	ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1453	if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
arm7_9_common.c:1455	read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1459	ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
arm7_9_common.c:1461	ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
arm7_9_common.c:1533	reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
arm7_9_common.c:1572	reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm7_9_common.c:1592	&ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(
arm_simulator.c:655	return buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_simulator.c:663	buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1435	r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1551	regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1555	ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1557	buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5.c:1559	ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
armv4_5.c:1561	ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
xscale.c:1656	if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1674	r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1687	r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1726	if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1733	if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1752	r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
xscale.c:1760	r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,

ARMV4_5_CORE_REG_MODE macro

Syntax

Arguments

cache

mode

num

References