OpenOCD
reg::valid
is only used within OpenOCD.
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OpenOCD
reg::valid
reg::valid field
Syntax
from
register.h:126
bool
valid
;
References
Location
Referrer
Text
register.h:126
bool
valid
;
aarch64.c:622
aarch64_restore_one()
arm
->
pc
->
valid
=
true
;
arc.c:229
arc_get_register()
if
(
reg
->
valid
)
{
arc.c:252
arc_get_register()
reg
->
valid
=
true
;
arc.c:254
arc_get_register()
reg
->
valid
=
false
;
arc.c:287
arc_set_register()
reg
->
valid
=
true
;
arc.c:584
arc_reg_get_field()
if
(
!
reg
->
valid
)
arc.c:607
arc_get_register_value()
if
(
!
reg
->
valid
)
arc.c:881
arc_save_context()
if
(
!
reg
->
valid
&&
reg
->
exist
)
arc.c:888
arc_save_context()
if
(
!
reg
->
valid
&&
reg
->
exist
)
arc.c:915
arc_save_context()
if
(
!
reg
->
valid
&&
reg
->
exist
)
{
arc.c:917
arc_save_context()
reg
->
valid
=
true
;
arc.c:930
arc_save_context()
if
(
!
reg
->
valid
&&
reg
->
exist
)
{
arc.c:932
arc_save_context()
reg
->
valid
=
true
;
arc.c:1203
arc_restore_context()
if
(
reg
->
valid
&&
reg
->
exist
&&
reg
->
dirty
)
{
arc.c:1214
arc_restore_context()
if
(
reg
->
valid
&&
reg
->
exist
&&
reg
->
dirty
)
{
arc.c:1306
arc_resume()
pc
->
valid
=
true
;
arc.c:1318
arc_resume()
resume_pc
,
pc
->
dirty
,
pc
->
valid
)
;
arc.c:1321
arc_resume()
if
(
pc
->
valid
&&
resume_pc
==
target_buffer_get_u32
(
target
,
pc
->
value
)
)
{
arc.c:2104
arc_step()
pc
->
valid
=
true
;
arm11.c:434
arm11_nextpc()
arm11
->
arm
.
pc
->
valid
=
true
;
arm720t.c:352
arm720t_soft_reset_halt()
arm
->
pc
->
valid
=
true
;
arm7_9_common.c:1140
arm7_9_soft_reset_halt()
arm
->
pc
->
valid
=
true
;
arm7_9_common.c:1148
arm7_9_soft_reset_halt()
r
->
valid
=
true
;
arm7_9_common.c:1340
arm7_9_debug_entry()
r
->
valid
=
true
;
arm7_9_common.c:1354
arm7_9_debug_entry()
arm
->
spsr
->
valid
=
true
;
arm7_9_common.c:1415
arm7_9_full_context()
if
(
!
ARMV4_5_CORE_REG_MODE
(
arm
->
core_cache
,
armv4_5_number_to_mode
(
i
)
,
j
)
.
valid
)
arm7_9_common.c:1431
arm7_9_full_context()
armv4_5_number_to_mode
(
i
)
,
j
)
.
valid
)
{
arm7_9_common.c:1441
arm7_9_full_context()
j
)
.
valid
=
true
;
arm7_9_common.c:1454
arm7_9_full_context()
16
)
.
valid
)
{
arm7_9_common.c:1460
arm7_9_full_context()
16
)
.
valid
=
true
;
arm7_9_common.c:1535
arm7_9_restore_context()
if
(
reg
->
valid
)
{
arm7_9_common.c:1580
arm7_9_restore_context()
reg
->
valid
=
true
;
arm7_9_common.c:1623
arm7_9_restore_context()
arm
->
cpsr
->
valid
=
true
;
arm7_9_common.c:2032
arm7_9_read_core_reg()
r
->
valid
=
true
;
arm7_9_common.c:2089
arm7_9_write_core_reg()
r
->
valid
=
true
;
arm7_9_common.c:2244
arm7_9_read_memory()
r
->
dirty
=
r
->
valid
;
arm7_9_common.c:2458
arm7_9_write_memory()
r
->
dirty
=
r
->
valid
;
arm7_9_common.c:2831
arm7_9_setup_semihosting()
if
(
!
vector_catch
->
valid
)
arm920t.c:778
arm920t_soft_reset_halt()
arm
->
pc
->
valid
=
true
;
arm920t.c:1117
arm920t_handle_read_cache_command()
r
[
0
]
.
dirty
=
r
[
0
]
.
valid
;
arm920t.c:1118
arm920t_handle_read_cache_command()
r
[
1
]
.
dirty
=
r
[
1
]
.
valid
;
arm920t.c:1119
arm920t_handle_read_cache_command()
r
[
2
]
.
dirty
=
r
[
2
]
.
valid
;
arm920t.c:1120
arm920t_handle_read_cache_command()
r
[
3
]
.
dirty
=
r
[
3
]
.
valid
;
arm920t.c:1121
arm920t_handle_read_cache_command()
r
[
4
]
.
dirty
=
r
[
4
]
.
valid
;
arm920t.c:1122
arm920t_handle_read_cache_command()
r
[
5
]
.
dirty
=
r
[
5
]
.
valid
;
arm920t.c:1123
arm920t_handle_read_cache_command()
r
[
6
]
.
dirty
=
r
[
6
]
.
valid
;
arm920t.c:1124
arm920t_handle_read_cache_command()
r
[
7
]
.
dirty
=
r
[
7
]
.
valid
;
arm920t.c:1127
arm920t_handle_read_cache_command()
r
->
dirty
=
r
->
valid
;
arm920t.c:1130
arm920t_handle_read_cache_command()
r
->
dirty
=
r
->
valid
;
arm920t.c:1429
arm920t_handle_read_mmu_command()
r
[
0
]
.
dirty
=
r
[
0
]
.
valid
;
arm920t.c:1430
arm920t_handle_read_mmu_command()
r
[
1
]
.
dirty
=
r
[
1
]
.
valid
;
arm920t.c:1431
arm920t_handle_read_mmu_command()
r
[
2
]
.
dirty
=
r
[
2
]
.
valid
;
arm920t.c:1432
arm920t_handle_read_mmu_command()
r
[
3
]
.
dirty
=
r
[
3
]
.
valid
;
arm920t.c:1433
arm920t_handle_read_mmu_command()
r
[
4
]
.
dirty
=
r
[
4
]
.
valid
;
arm920t.c:1434
arm920t_handle_read_mmu_command()
r
[
5
]
.
dirty
=
r
[
5
]
.
valid
;
arm920t.c:1435
arm920t_handle_read_mmu_command()
r
[
6
]
.
dirty
=
r
[
6
]
.
valid
;
arm920t.c:1436
arm920t_handle_read_mmu_command()
r
[
7
]
.
dirty
=
r
[
7
]
.
valid
;
arm920t.c:1439
arm920t_handle_read_mmu_command()
r
->
dirty
=
r
->
valid
;
arm920t.c:1442
arm920t_handle_read_mmu_command()
r
->
dirty
=
r
->
valid
;
arm926ejs.c:573
arm926ejs_soft_reset_halt()
arm
->
pc
->
valid
=
true
;
arm9tdmi.c:811
handle_arm9tdmi_catch_vectors_command()
if
(
!
vector_catch
->
valid
)
arm_dpm.c:199
dpm_read_reg_u64()
r
->
valid
=
true
;
arm_dpm.c:267
arm_dpm_read_reg()
r
->
valid
=
true
;
arm_dpm.c:393
arm_dpm_read_current_registers()
if
(
!
r
->
valid
)
{
arm_dpm.c:411
arm_dpm_read_current_registers()
if
(
r
->
valid
)
arm_dpm.c:801
arm_dpm_full_context()
if
(
!
cache
->
reg_list
[
i
]
.
exist
||
cache
->
reg_list
[
i
]
.
valid
)
arm_semihosting.c:223
arm_semihosting()
if
(
!
arm
->
spsr
->
valid
)
{
armv4_5.c:449
arm_set_cpsr()
arm
->
cpsr
->
valid
=
true
;
armv4_5.c:541
.
valid
=
true
,
armv4_5.c:558
.
valid
=
true
,
armv4_5.c:588
armv4_5_get_core_reg()
reg
->
valid
=
true
;
armv4_5.c:634
armv4_5_set_core_reg()
reg
->
valid
=
true
;
armv4_5.c:892
handle_armv4_5_reg_command()
if
(
!
reg
->
valid
)
armv4_5.c:1437
armv4_5_run_algorithm_inner()
if
(
!
r
->
valid
)
armv4_5.c:1490
armv4_5_run_algorithm_inner()
arm
->
cpsr
->
valid
=
true
;
armv4_5.c:1560
armv4_5_run_algorithm_inner()
i
)
.
valid
=
true
;
armv4_5.c:1758
arm_full_context()
if
(
!
reg
->
exist
||
reg
->
valid
)
armv7m.c:241
armv7m_set_core_reg()
reg
->
valid
=
true
;
armv7m.c:340
armv7m_read_core_reg()
if
(
!
r32
->
valid
)
{
armv7m.c:363
armv7m_read_core_reg()
r
->
valid
=
false
;
armv7m.c:375
armv7m_read_core_reg()
r
->
valid
=
true
;
armv7m.c:410
armv7m_write_core_reg()
if
(
!
r32
->
valid
)
{
armv7m.c:445
armv7m_write_core_reg()
r
->
valid
=
true
;
armv7m.c:538
armv7m_start_algorithm()
if
(
!
reg
->
valid
)
armv7m.c:541
armv7m_start_algorithm()
if
(
!
reg
->
valid
)
armv7m.c:593
armv7m_start_algorithm()
reg
->
valid
=
true
;
armv7m.c:610
armv7m_start_algorithm()
armv7m
->
arm
.
core_cache
->
reg_list
[
ARMV7M_CONTROL
]
.
valid
=
true
;
armv7m.c:708
armv7m_wait_algorithm()
reg
->
valid
=
true
;
armv7m.c:719
armv7m_wait_algorithm()
armv7m
->
arm
.
core_cache
->
reg_list
[
ARMV7M_CONTROL
]
.
valid
=
true
;
armv7m.c:791
armv7m_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
armv7m.c:1086
armv7m_maybe_skip_bkpt_inst()
r
->
valid
=
true
;
armv8.c:934
armv8_set_cpsr()
arm
->
cpsr
->
valid
=
true
;
armv8.c:1705
armv8_set_core_reg()
reg
->
valid
=
true
;
armv8.c:1712
armv8_set_core_reg()
reg
->
valid
=
true
;
armv8.c:1739
armv8_get_core_reg32()
if
(
reg64
->
valid
)
{
armv8.c:1740
armv8_get_core_reg32()
reg
->
valid
=
true
;
armv8.c:1746
armv8_get_core_reg32()
reg
->
valid
=
reg64
->
valid
;
armv8.c:1772
armv8_set_core_reg32()
reg
->
valid
=
true
;
armv8.c:1773
armv8_set_core_reg32()
reg64
->
valid
=
true
;
armv8_dpm.c:655
dpmv8_read_reg()
r
->
valid
=
true
;
armv8_dpm.c:668
dpmv8_read_reg()
r
->
valid
=
true
;
armv8_dpm.c:752
armv8_dpm_read_current_registers()
if
(
!
r
->
valid
)
{
armv8_dpm.c:761
armv8_dpm_read_current_registers()
if
(
!
r
->
valid
)
{
armv8_dpm.c:786
armv8_dpm_read_current_registers()
if
(
!
r
->
exist
||
r
->
valid
)
armv8_dpm.c:933
armv8_dpm_write_dirty_registers()
if
(
!
cache
->
reg_list
[
i
]
.
valid
)
armv8_dpm.c:1054
armv8_dpm_full_context()
if
(
!
cache
->
reg_list
[
i
]
.
exist
||
cache
->
reg_list
[
i
]
.
valid
)
avr32_ap7k.c:65
avr32_ap7k_save_context()
if
(
!
ap7k
->
core_cache
->
reg_list
[
i
]
.
valid
)
avr32_ap7k.c:102
avr32_read_core_reg()
ap7k
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
avr32_ap7k.c:121
avr32_write_core_reg()
ap7k
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
avr32_ap7k.c:152
avr32_set_core_reg()
reg
->
valid
=
true
;
avr32_ap7k.c:189
avr32_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
cortex_a.c:884
cortex_a_internal_restore()
arm
->
pc
->
valid
=
true
;
cortex_m.c:391
cortex_m_fast_read_all_regs()
r
->
valid
=
true
;
cortex_m.c:1337
cortex_m_restore_one()
r
->
valid
=
true
;
cortex_m.c:1348
cortex_m_restore_one()
r
->
valid
=
true
;
cortex_m.c:1356
cortex_m_restore_one()
r
->
valid
=
true
;
cortex_m.c:1502
cortex_m_step()
pc
->
valid
=
true
;
dsp563xx.c:376
dsp563xx_read_core_reg()
dsp563xx
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
dsp563xx.c:392
dsp563xx_write_core_reg()
dsp563xx
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
dsp563xx.c:425
dsp563xx_set_core_reg()
reg
->
valid
=
true
;
dsp563xx.c:466
dsp563xx_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
dsp563xx.c:483
dsp563xx_reg_read_high_io()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_R0
]
.
valid
)
dsp563xx.c:513
dsp563xx_reg_write_high_io()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_R0
]
.
valid
)
dsp563xx.c:738
dsp563xx_read_register()
dsp563xx
->
core_cache
->
reg_list
[
num
]
.
valid
=
false
;
dsp563xx.c:740
dsp563xx_read_register()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
num
]
.
valid
)
{
dsp563xx.c:820
dsp563xx_write_register()
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_SSH
]
.
valid
=
dsp563xx.c:822
dsp563xx_write_register()
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_SSL
]
.
valid
=
dsp563xx.c:877
dsp563xx_invalidate_x_context()
dsp563xx
->
core_cache
->
reg_list
[
i
]
.
valid
=
false
;
dsp563xx.c:1547
dsp563xx_read_memory_core()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_R0
]
.
valid
)
dsp563xx.c:1550
dsp563xx_read_memory_core()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_R1
]
.
valid
)
dsp563xx.c:1729
dsp563xx_write_memory_core()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_R0
]
.
valid
)
dsp563xx.c:1732
dsp563xx_write_memory_core()
if
(
!
dsp563xx
->
core_cache
->
reg_list
[
DSP563XX_REG_IDX_R1
]
.
valid
)
embeddedice.c:198
embeddedice_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
embeddedice.c:478
embeddedice_set_reg()
reg
->
valid
=
true
;
esirisc.c:290
esirisc_save_context()
if
(
reg
->
exist
&&
!
reg
->
valid
)
esirisc.c:876
esirisc_resume_or_step()
esirisc
->
epc
->
valid
=
true
;
esirisc.c:1315
esirisc_read_reg()
reg
->
valid
=
true
;
esirisc.c:1337
esirisc_write_reg()
reg
->
valid
=
true
;
esirisc.c:1360
esirisc_read_csr()
reg
->
valid
=
true
;
esirisc.c:1382
esirisc_write_csr()
reg
->
valid
=
true
;
esirisc.c:1415
esirisc_set_reg()
reg
->
valid
=
true
;
etb.c:136
etb_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
etb.c:264
etb_set_reg()
reg
->
valid
=
true
;
etm.c:555
etm_set_reg()
reg
->
valid
=
true
;
feroceon.c:524
feroceon_bulk_write_memory()
arm
->
core_cache
->
reg_list
[
0
]
.
valid
=
true
;
feroceon.c:567
feroceon_bulk_write_memory()
arm
->
core_cache
->
reg_list
[
i
]
.
valid
=
true
;
feroceon.c:571
feroceon_bulk_write_memory()
arm
->
pc
->
valid
=
true
;
gdb_server.c:1222
gdb_get_reg_value_as_str()
if
(
!
reg
->
valid
)
hla_target.c:221
adapter_load_context()
if
(
r
->
exist
&&
!
r
->
valid
)
hla_target.c:466
adapter_resume()
pc
->
valid
=
true
;
hla_target.c:548
adapter_step()
pc
->
valid
=
true
;
hwthread.c:272
hwthread_get_thread_reg_list()
if
(
!
reg_list
[
i
]
->
valid
)
{
lakemont.c:315
restore_context()
x86_32
->
cache
->
reg_list
[
i
]
.
valid
=
false
;
lakemont.c:350
lakemont_set_core_reg()
reg
->
valid
=
true
;
lakemont.c:398
lakemont_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
lakemont.c:659
read_hw_reg()
x86_32
->
cache
->
reg_list
[
reg
]
.
valid
=
true
;
lakemont.c:702
write_hw_reg()
x86_32
->
cache
->
reg_list
[
reg
]
.
valid
=
false
;
lakemont.c:940
lakemont_poll()
x86_32
->
cache
->
reg_list
[
EIP
]
.
valid
=
true
;
linux.c:210
linux_os_thread_reg_list()
if
(
!
gdb_reg_list
[
i
]
->
valid
)
linux.c:414
get_current()
if
(
!
reg_list
[
13
]
->
valid
)
mips32.c:260
mips32_set_core_reg()
reg
->
valid
=
true
;
mips32.c:355
mips32_read_core_reg()
mips32
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
mips32.c:399
mips32_write_core_reg()
mips32
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
mips32.c:437
mips32_save_context()
if
(
!
mips32
->
core_cache
->
reg_list
[
i
]
.
valid
)
mips32.c:507
mips32_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
mips32.c:624
mips32_run_algorithm()
if
(
!
mips32
->
core_cache
->
reg_list
[
i
]
.
valid
)
mips32.c:701
mips32_run_algorithm()
mips32
->
core_cache
->
reg_list
[
i
]
.
valid
=
true
;
mips64.c:251
mips64_set_core_reg()
reg
->
valid
=
true
;
mips64.c:268
mips64_read_core_reg()
mips64
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
mips64.c:287
mips64_write_core_reg()
mips64
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
mips64.c:300
mips64_invalidate_core_regs()
mips64
->
core_cache
->
reg_list
[
i
]
.
valid
=
false
;
mips_m4k.c:448
mips_m4k_internal_restore()
mips32
->
core_cache
->
reg_list
[
MIPS32_REGLIST_C0_PC_INDEX
]
.
valid
=
true
;
mips_m4k.c:542
mips_m4k_step()
mips32
->
core_cache
->
reg_list
[
MIPS32_REGLIST_C0_PC_INDEX
]
.
valid
=
true
;
mips_mips64.c:629
mips_mips64_resume()
pc
->
valid
=
true
;
mips_mips64.c:721
mips_mips64_step()
pc
->
valid
=
true
;
or1k.c:339
or1k_save_context()
if
(
!
or1k
->
core_cache
->
reg_list
[
i
]
.
valid
)
{
or1k.c:416
or1k_read_core_reg()
or1k
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
or1k.c:445
or1k_write_core_reg()
or1k
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
or1k.c:480
or1k_set_core_reg()
reg
->
valid
=
true
;
or1k.c:534
or1k_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
register.c:100
register_cache_invalidate()
reg
->
valid
=
false
;
register.c:113
register_set_dummy_core_reg()
reg
->
valid
=
true
;
riscv-011.c:1128
execute_resume()
if
(
mstatus_reg
->
valid
)
{
riscv-011.c:1208
reg_cache_get()
if
(
!
r
->
valid
)
{
riscv-011.c:1222
reg_cache_set()
r
->
valid
=
true
;
riscv-011.c:1229
update_mstatus_actual()
if
(
mstatus_reg
->
valid
)
{
riscv-011.c:1380
get_register()
target
->
reg_cache
->
reg_list
[
regid
]
.
valid
=
true
;
riscv.c:1797
riscv_get_gdb_reg_list_internal()
!
target
->
reg_cache
->
reg_list
[
i
]
.
valid
)
{
riscv.c:3235
riscv_invalidate_register_cache()
reg
->
valid
=
false
;
riscv.c:3326
riscv_set_register()
reg
->
valid
=
gdb_regno_cacheable
(
regid
,
true
)
;
riscv.c:3328
riscv_set_register()
reg
->
valid
=
false
;
riscv.c:3330
riscv_set_register()
target_name
(
target
)
,
value
,
reg
->
name
,
reg
->
valid
)
;
riscv.c:3348
riscv_get_register()
if
(
reg
&&
reg
->
valid
)
{
riscv.c:3365
riscv_get_register()
reg
->
valid
=
gdb_regno_cacheable
(
regid
,
false
)
;
riscv.c:3719
register_get()
reg
->
valid
=
gdb_regno_cacheable
(
reg
->
number
,
false
)
;
riscv.c:3722
register_get()
str
,
reg
->
name
,
reg
->
valid
)
;
riscv.c:3735
register_set()
str
,
reg
->
name
,
reg
->
valid
)
;
riscv.c:3744
register_set()
reg
->
valid
=
gdb_regno_cacheable
(
reg
->
number
,
true
)
;
riscv.c:3978
riscv_init_registers()
r
->
valid
=
false
;
stm8.c:566
stm8_set_core_reg()
reg
->
valid
=
true
;
stm8.c:582
stm8_save_context()
if
(
!
stm8
->
core_cache
->
reg_list
[
i
]
.
valid
)
stm8.c:1015
stm8_resume()
stm8
->
core_cache
->
reg_list
[
STM8_PC
]
.
valid
=
true
;
stm8.c:1136
stm8_read_core_reg()
stm8
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
stm8.c:1155
stm8_write_core_reg()
stm8
->
core_cache
->
reg_list
[
num
]
.
valid
=
true
;
stm8.c:1217
stm8_build_reg_cache()
reg_list
[
i
]
.
valid
=
false
;
stm8.c:1314
stm8_step()
stm8
->
core_cache
->
reg_list
[
STM8_PC
]
.
valid
=
true
;
stm8.c:1847
stm8_run_algorithm()
if
(
!
stm8
->
core_cache
->
reg_list
[
i
]
.
valid
)
stm8.c:1927
stm8_run_algorithm()
stm8
->
core_cache
->
reg_list
[
i
]
.
valid
=
true
;
target.c:3058
handle_reg_command()
if
(
reg
->
valid
)
{
target.c:3123
handle_reg_command()
reg
->
valid
=
false
;
target.c:3125
handle_reg_command()
if
(
!
reg
->
valid
)
{
target.c:4871
target_jim_get_reg()
if
(
force
||
!
reg
->
valid
)
{
x86_32_common.c:932
set_debug_regs()
x86_32
->
cache
->
reg_list
[
bp_num
+
DR0
]
.
valid
=
true
;
x86_32_common.c:935
set_debug_regs()
x86_32
->
cache
->
reg_list
[
DR6
]
.
valid
=
true
;
x86_32_common.c:938
set_debug_regs()
x86_32
->
cache
->
reg_list
[
DR7
]
.
valid
=
true
;
x86_32_common.c:963
unset_debug_regs()
x86_32
->
cache
->
reg_list
[
bp_num
+
DR0
]
.
valid
=
true
;
x86_32_common.c:966
unset_debug_regs()
x86_32
->
cache
->
reg_list
[
DR6
]
.
valid
=
true
;
x86_32_common.c:969
unset_debug_regs()
x86_32
->
cache
->
reg_list
[
DR7
]
.
valid
=
true
;
xscale.c:205
xscale_read_dcsr()
xscale
->
reg_cache
->
reg_list
[
XSCALE_DCSR
]
.
valid
=
true
;
xscale.c:617
xscale_write_dcsr()
xscale
->
reg_cache
->
reg_list
[
XSCALE_DCSR
]
.
valid
=
true
;
xscale.c:861
xscale_debug_entry()
arm
->
core_cache
->
reg_list
[
0
]
.
valid
=
true
;
xscale.c:867
xscale_debug_entry()
arm
->
pc
->
valid
=
true
;
xscale.c:874
xscale_debug_entry()
arm
->
core_cache
->
reg_list
[
i
]
.
valid
=
true
;
xscale.c:894
xscale_debug_entry()
arm
->
spsr
->
valid
=
true
;
xscale.c:906
xscale_debug_entry()
r
->
valid
=
true
;
xscale.c:912
xscale_debug_entry()
xscale
->
reg_cache
->
reg_list
[
i
]
.
valid
=
false
;
xscale.c:1657
xscale_full_context()
mode
,
j
)
.
valid
)
xscale.c:1681
xscale_full_context()
r
->
valid
=
true
;
xscale.c:1692
xscale_full_context()
r
->
valid
=
true
;
xscale.c:2417
xscale_get_reg()
reg
->
valid
=
true
;
xscale.c:2883
xscale_build_reg_cache()
(
*
cache_p
)
->
reg_list
[
i
]
.
valid
=
false
;
xtensa.c:485
xtensa_core_reg_set()
reg
->
valid
=
true
;
xtensa.c:1446
xtensa_fetch_all_regs()
reg_list
[
i
]
.
valid
=
true
;
xtensa.c:1450
xtensa_fetch_all_regs()
reg_list
[
i
]
.
valid
=
true
;
xtensa.c:1453
xtensa_fetch_all_regs()
reg_list
[
i
]
.
valid
=
false
;
xtensa.c:2781
xtensa_start_algorithm()
reg
->
valid
=
1
;
xtensa.c:2795
xtensa_start_algorithm()
xtensa
->
core_cache
->
reg_list
[
eps_reg_idx
]
.
valid
=
1
;
xtensa.c:2880
xtensa_wait_algorithm()
xtensa
->
core_cache
->
reg_list
[
i
]
.
valid
=
0
;
xtensa.c:2897
xtensa_wait_algorithm()
xtensa
->
core_cache
->
reg_list
[
i
]
.
valid
=
1
;
xtensa.c:2974
xtensa_build_reg_cache()
reg_list
[
didx
]
.
valid
=
false
;
Data Use
Functions writing
reg::valid
Functions reading
reg::valid
or1k_read_core_reg()
or1k_write_core_reg()
or1k_set_core_reg()
or1k_build_reg_cache()
arm11_nextpc()
arm720t_soft_reset_halt()
arm7_9_soft_reset_halt()
arm7_9_debug_entry()
arm7_9_full_context()
arm7_9_restore_context()
arm7_9_read_core_reg()
arm7_9_write_core_reg()
arm920t_soft_reset_halt()
arm926ejs_soft_reset_halt()
arm_set_cpsr()
armv4_5_get_core_reg()
armv4_5_set_core_reg()
armv4_5_run_algorithm_inner()
armv7m_set_core_reg()
armv7m_read_core_reg()
armv7m_write_core_reg()
armv7m_start_algorithm()
armv7m_wait_algorithm()
armv7m_build_reg_cache()
armv7m_maybe_skip_bkpt_inst()
armv8_set_cpsr()
armv8_set_core_reg()
armv8_get_core_reg32()
armv8_set_core_reg32()
dpmv8_read_reg()
dpm_read_reg_u64()
arm_dpm_read_reg()
avr32_read_core_reg()
avr32_write_core_reg()
avr32_set_core_reg()
avr32_build_reg_cache()
cortex_a_internal_restore()
cortex_m_fast_read_all_regs()
cortex_m_restore_one()
cortex_m_step()
dsp563xx_read_core_reg()
dsp563xx_write_core_reg()
dsp563xx_set_core_reg()
dsp563xx_build_reg_cache()
dsp563xx_read_register()
dsp563xx_write_register()
dsp563xx_invalidate_x_context()
embeddedice_build_reg_cache()
embeddedice_set_reg()
etb_build_reg_cache()
etb_set_reg()
etm_set_reg()
feroceon_bulk_write_memory()
adapter_resume()
adapter_step()
restore_context()
lakemont_set_core_reg()
lakemont_build_reg_cache()
read_hw_reg()
write_hw_reg()
lakemont_poll()
mips32_set_core_reg()
mips32_read_core_reg()
mips32_write_core_reg()
mips32_build_reg_cache()
mips32_run_algorithm()
mips_m4k_internal_restore()
mips_m4k_step()
register_cache_invalidate()
register_set_dummy_core_reg()
handle_reg_command()
set_debug_regs()
unset_debug_regs()
xscale_read_dcsr()
xscale_write_dcsr()
xscale_debug_entry()
xscale_full_context()
xscale_get_reg()
xscale_build_reg_cache()
aarch64_restore_one()
stm8_set_core_reg()
stm8_resume()
stm8_read_core_reg()
stm8_write_core_reg()
stm8_build_reg_cache()
stm8_step()
stm8_run_algorithm()
riscv_invalidate_register_cache()
riscv_set_register()
riscv_get_register()
register_get()
register_set()
riscv_init_registers()
reg_cache_set()
get_register()
esirisc_resume_or_step()
esirisc_read_reg()
esirisc_write_reg()
esirisc_read_csr()
esirisc_write_csr()
esirisc_set_reg()
mips_mips64_resume()
mips_mips64_step()
mips64_set_core_reg()
mips64_read_core_reg()
mips64_write_core_reg()
mips64_invalidate_core_regs()
arc_get_register()
arc_set_register()
arc_save_context()
arc_resume()
arc_step()
xtensa_core_reg_set()
xtensa_fetch_all_regs()
xtensa_start_algorithm()
xtensa_wait_algorithm()
xtensa_build_reg_cache()
all items filtered out
reg::valid
or1k_save_context()
linux_os_thread_reg_list()
get_current()
hwthread_get_thread_reg_list()
gdb_get_reg_value_as_str()
arm7_9_full_context()
arm7_9_restore_context()
arm7_9_read_memory()
arm7_9_write_memory()
arm7_9_setup_semihosting()
arm920t_handle_read_cache_command()
arm920t_handle_read_mmu_command()
handle_arm9tdmi_catch_vectors_command()
handle_armv4_5_reg_command()
armv4_5_run_algorithm_inner()
arm_full_context()
armv7m_read_core_reg()
armv7m_write_core_reg()
armv7m_start_algorithm()
armv8_get_core_reg32()
armv8_dpm_read_current_registers()
armv8_dpm_write_dirty_registers()
armv8_dpm_full_context()
arm_dpm_read_current_registers()
arm_dpm_full_context()
arm_semihosting()
avr32_ap7k_save_context()
dsp563xx_reg_read_high_io()
dsp563xx_reg_write_high_io()
dsp563xx_read_register()
dsp563xx_read_memory_core()
dsp563xx_write_memory_core()
adapter_load_context()
mips32_save_context()
mips32_run_algorithm()
handle_reg_command()
target_jim_get_reg()
xscale_full_context()
stm8_save_context()
stm8_run_algorithm()
riscv_get_gdb_reg_list_internal()
riscv_set_register()
riscv_get_register()
register_get()
register_set()
execute_resume()
reg_cache_get()
update_mstatus_actual()
esirisc_save_context()
arc_get_register()
arc_reg_get_field()
arc_get_register_value()
arc_save_context()
arc_restore_context()
arc_resume()
all items filtered out