reg::valid is only used within OpenOCD.
 
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reg::valid field

Syntax

bool valid;

References

LocationReferrerText
register.h:126
bool valid;
aarch64.c:622aarch64_restore_one()
arm->pc->valid = true;
arc.c:229arc_get_register()
if (reg->valid) {
arc.c:252arc_get_register()
reg->valid = true;
arc.c:254arc_get_register()
reg->valid = false;
arc.c:287arc_set_register()
reg->valid = true;
arc.c:584arc_reg_get_field()
if (!reg->valid)
arc.c:607arc_get_register_value()
if (!reg->valid)
arc.c:881arc_save_context()
if (!reg->valid && reg->exist)
arc.c:888arc_save_context()
if (!reg->valid && reg->exist)
arc.c:915arc_save_context()
if (!reg->valid && reg->exist) {
arc.c:917arc_save_context()
reg->valid = true;
arc.c:930arc_save_context()
if (!reg->valid && reg->exist) {
arc.c:932arc_save_context()
reg->valid = true;
arc.c:1203arc_restore_context()
if (reg->valid && reg->exist && reg->dirty) {
arc.c:1214arc_restore_context()
if (reg->valid && reg->exist && reg->dirty) {
arc.c:1306arc_resume()
pc->valid = true;
arc.c:1318arc_resume()
resume_pc, pc->dirty, pc->valid);
arc.c:1321arc_resume()
if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) {
arc.c:2104arc_step()
pc->valid = true;
arm11.c:434arm11_nextpc()
arm11->arm.pc->valid = true;
arm720t.c:352arm720t_soft_reset_halt()
arm->pc->valid = true;
arm7_9_common.c:1140arm7_9_soft_reset_halt()
arm->pc->valid = true;
arm7_9_common.c:1148arm7_9_soft_reset_halt()
r->valid = true;
arm7_9_common.c:1340arm7_9_debug_entry()
r->valid = true;
arm7_9_common.c:1354arm7_9_debug_entry()
arm->spsr->valid = true;
arm7_9_common.c:1415arm7_9_full_context()
arm7_9_common.c:1431arm7_9_full_context()
armv4_5_number_to_mode(i), j).valid) {
arm7_9_common.c:1441arm7_9_full_context()
j).valid = true;
arm7_9_common.c:1454arm7_9_full_context()
16).valid) {
arm7_9_common.c:1460arm7_9_full_context()
16).valid = true;
arm7_9_common.c:1535arm7_9_restore_context()
if (reg->valid) {
arm7_9_common.c:1580arm7_9_restore_context()
reg->valid = true;
arm7_9_common.c:1623arm7_9_restore_context()
arm->cpsr->valid = true;
arm7_9_common.c:2032arm7_9_read_core_reg()
r->valid = true;
arm7_9_common.c:2089arm7_9_write_core_reg()
r->valid = true;
arm7_9_common.c:2244arm7_9_read_memory()
r->dirty = r->valid;
arm7_9_common.c:2458arm7_9_write_memory()
r->dirty = r->valid;
arm7_9_common.c:2831arm7_9_setup_semihosting()
if (!vector_catch->valid)
arm920t.c:778arm920t_soft_reset_halt()
arm->pc->valid = true;
arm920t.c:1117arm920t_handle_read_cache_command()
r[0].dirty = r[0].valid;
arm920t.c:1118arm920t_handle_read_cache_command()
r[1].dirty = r[1].valid;
arm920t.c:1119arm920t_handle_read_cache_command()
r[2].dirty = r[2].valid;
arm920t.c:1120arm920t_handle_read_cache_command()
r[3].dirty = r[3].valid;
arm920t.c:1121arm920t_handle_read_cache_command()
r[4].dirty = r[4].valid;
arm920t.c:1122arm920t_handle_read_cache_command()
r[5].dirty = r[5].valid;
arm920t.c:1123arm920t_handle_read_cache_command()
r[6].dirty = r[6].valid;
arm920t.c:1124arm920t_handle_read_cache_command()
r[7].dirty = r[7].valid;
arm920t.c:1127arm920t_handle_read_cache_command()
r->dirty = r->valid;
arm920t.c:1130arm920t_handle_read_cache_command()
r->dirty = r->valid;
arm920t.c:1429arm920t_handle_read_mmu_command()
r[0].dirty = r[0].valid;
arm920t.c:1430arm920t_handle_read_mmu_command()
r[1].dirty = r[1].valid;
arm920t.c:1431arm920t_handle_read_mmu_command()
r[2].dirty = r[2].valid;
arm920t.c:1432arm920t_handle_read_mmu_command()
r[3].dirty = r[3].valid;
arm920t.c:1433arm920t_handle_read_mmu_command()
r[4].dirty = r[4].valid;
arm920t.c:1434arm920t_handle_read_mmu_command()
r[5].dirty = r[5].valid;
arm920t.c:1435arm920t_handle_read_mmu_command()
r[6].dirty = r[6].valid;
arm920t.c:1436arm920t_handle_read_mmu_command()
r[7].dirty = r[7].valid;
arm920t.c:1439arm920t_handle_read_mmu_command()
r->dirty = r->valid;
arm920t.c:1442arm920t_handle_read_mmu_command()
r->dirty = r->valid;
arm926ejs.c:573arm926ejs_soft_reset_halt()
arm->pc->valid = true;
arm9tdmi.c:811handle_arm9tdmi_catch_vectors_command()
if (!vector_catch->valid)
arm_dpm.c:199dpm_read_reg_u64()
r->valid = true;
arm_dpm.c:267arm_dpm_read_reg()
r->valid = true;
arm_dpm.c:393arm_dpm_read_current_registers()
if (!r->valid) {
arm_dpm.c:411arm_dpm_read_current_registers()
if (r->valid)
arm_dpm.c:801arm_dpm_full_context()
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
arm_semihosting.c:223arm_semihosting()
if (!arm->spsr->valid) {
armv4_5.c:449arm_set_cpsr()
arm->cpsr->valid = true;
armv4_5.c:541
.valid = true,
armv4_5.c:558
.valid = true,
armv4_5.c:588armv4_5_get_core_reg()
reg->valid = true;
armv4_5.c:634armv4_5_set_core_reg()
reg->valid = true;
armv4_5.c:892handle_armv4_5_reg_command()
if (!reg->valid)
armv4_5.c:1437armv4_5_run_algorithm_inner()
if (!r->valid)
armv4_5.c:1490armv4_5_run_algorithm_inner()
arm->cpsr->valid = true;
armv4_5.c:1560armv4_5_run_algorithm_inner()
i).valid = true;
armv4_5.c:1758arm_full_context()
if (!reg->exist || reg->valid)
armv7m.c:241armv7m_set_core_reg()
reg->valid = true;
armv7m.c:340armv7m_read_core_reg()
if (!r32->valid) {
armv7m.c:363armv7m_read_core_reg()
r->valid = false;
armv7m.c:375armv7m_read_core_reg()
r->valid = true;
armv7m.c:410armv7m_write_core_reg()
if (!r32->valid) {
armv7m.c:445armv7m_write_core_reg()
r->valid = true;
armv7m.c:538armv7m_start_algorithm()
if (!reg->valid)
armv7m.c:541armv7m_start_algorithm()
if (!reg->valid)
armv7m.c:593armv7m_start_algorithm()
reg->valid = true;
armv7m.c:610armv7m_start_algorithm()
armv7m.c:708armv7m_wait_algorithm()
reg->valid = true;
armv7m.c:719armv7m_wait_algorithm()
armv7m.c:791armv7m_build_reg_cache()
reg_list[i].valid = false;
armv7m.c:1086armv7m_maybe_skip_bkpt_inst()
r->valid = true;
armv8.c:934armv8_set_cpsr()
arm->cpsr->valid = true;
armv8.c:1705armv8_set_core_reg()
reg->valid = true;
armv8.c:1712armv8_set_core_reg()
reg->valid = true;
armv8.c:1739armv8_get_core_reg32()
if (reg64->valid) {
armv8.c:1740armv8_get_core_reg32()
reg->valid = true;
armv8.c:1746armv8_get_core_reg32()
reg->valid = reg64->valid;
armv8.c:1772armv8_set_core_reg32()
reg->valid = true;
armv8.c:1773armv8_set_core_reg32()
reg64->valid = true;
armv8_dpm.c:655dpmv8_read_reg()
r->valid = true;
armv8_dpm.c:668dpmv8_read_reg()
r->valid = true;
armv8_dpm.c:752armv8_dpm_read_current_registers()
if (!r->valid) {
armv8_dpm.c:761armv8_dpm_read_current_registers()
if (!r->valid) {
armv8_dpm.c:786armv8_dpm_read_current_registers()
if (!r->exist || r->valid)
armv8_dpm.c:933armv8_dpm_write_dirty_registers()
if (!cache->reg_list[i].valid)
armv8_dpm.c:1054armv8_dpm_full_context()
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
avr32_ap7k.c:65avr32_ap7k_save_context()
if (!ap7k->core_cache->reg_list[i].valid)
avr32_ap7k.c:102avr32_read_core_reg()
ap7k->core_cache->reg_list[num].valid = true;
avr32_ap7k.c:121avr32_write_core_reg()
ap7k->core_cache->reg_list[num].valid = true;
avr32_ap7k.c:152avr32_set_core_reg()
reg->valid = true;
avr32_ap7k.c:189avr32_build_reg_cache()
reg_list[i].valid = false;
cortex_a.c:884cortex_a_internal_restore()
arm->pc->valid = true;
cortex_m.c:391cortex_m_fast_read_all_regs()
r->valid = true;
cortex_m.c:1337cortex_m_restore_one()
r->valid = true;
cortex_m.c:1348cortex_m_restore_one()
r->valid = true;
cortex_m.c:1356cortex_m_restore_one()
r->valid = true;
cortex_m.c:1502cortex_m_step()
pc->valid = true;
dsp563xx.c:376dsp563xx_read_core_reg()
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx.c:392dsp563xx_write_core_reg()
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx.c:425dsp563xx_set_core_reg()
reg->valid = true;
dsp563xx.c:466dsp563xx_build_reg_cache()
reg_list[i].valid = false;
dsp563xx.c:483dsp563xx_reg_read_high_io()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:513dsp563xx_reg_write_high_io()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:738dsp563xx_read_register()
dsp563xx->core_cache->reg_list[num].valid = false;
dsp563xx.c:740dsp563xx_read_register()
if (!dsp563xx->core_cache->reg_list[num].valid) {
dsp563xx.c:820dsp563xx_write_register()
dsp563xx.c:822dsp563xx_write_register()
dsp563xx.c:877dsp563xx_invalidate_x_context()
dsp563xx->core_cache->reg_list[i].valid = false;
dsp563xx.c:1547dsp563xx_read_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:1550dsp563xx_read_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
dsp563xx.c:1729dsp563xx_write_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
dsp563xx.c:1732dsp563xx_write_memory_core()
if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
embeddedice.c:198embeddedice_build_reg_cache()
reg_list[i].valid = false;
embeddedice.c:478embeddedice_set_reg()
reg->valid = true;
esirisc.c:290esirisc_save_context()
if (reg->exist && !reg->valid)
esirisc.c:876esirisc_resume_or_step()
esirisc->epc->valid = true;
esirisc.c:1315esirisc_read_reg()
reg->valid = true;
esirisc.c:1337esirisc_write_reg()
reg->valid = true;
esirisc.c:1360esirisc_read_csr()
reg->valid = true;
esirisc.c:1382esirisc_write_csr()
reg->valid = true;
esirisc.c:1415esirisc_set_reg()
reg->valid = true;
etb.c:136etb_build_reg_cache()
reg_list[i].valid = false;
etb.c:264etb_set_reg()
reg->valid = true;
etm.c:555etm_set_reg()
reg->valid = true;
feroceon.c:524feroceon_bulk_write_memory()
arm->core_cache->reg_list[0].valid = true;
feroceon.c:567feroceon_bulk_write_memory()
arm->core_cache->reg_list[i].valid = true;
feroceon.c:571feroceon_bulk_write_memory()
arm->pc->valid = true;
gdb_server.c:1222gdb_get_reg_value_as_str()
if (!reg->valid)
hla_target.c:221adapter_load_context()
if (r->exist && !r->valid)
hla_target.c:466adapter_resume()
pc->valid = true;
hla_target.c:548adapter_step()
pc->valid = true;
hwthread.c:272hwthread_get_thread_reg_list()
if (!reg_list[i]->valid) {
lakemont.c:315restore_context()
x86_32->cache->reg_list[i].valid = false;
lakemont.c:350lakemont_set_core_reg()
reg->valid = true;
lakemont.c:398lakemont_build_reg_cache()
reg_list[i].valid = false;
lakemont.c:659read_hw_reg()
x86_32->cache->reg_list[reg].valid = true;
lakemont.c:702write_hw_reg()
x86_32->cache->reg_list[reg].valid = false;
lakemont.c:940lakemont_poll()
x86_32->cache->reg_list[EIP].valid = true;
linux.c:210linux_os_thread_reg_list()
if (!gdb_reg_list[i]->valid)
linux.c:414get_current()
if (!reg_list[13]->valid)
mips32.c:260mips32_set_core_reg()
reg->valid = true;
mips32.c:355mips32_read_core_reg()
mips32->core_cache->reg_list[num].valid = true;
mips32.c:399mips32_write_core_reg()
mips32->core_cache->reg_list[num].valid = true;
mips32.c:437mips32_save_context()
if (!mips32->core_cache->reg_list[i].valid)
mips32.c:507mips32_build_reg_cache()
reg_list[i].valid = false;
mips32.c:624mips32_run_algorithm()
if (!mips32->core_cache->reg_list[i].valid)
mips32.c:701mips32_run_algorithm()
mips32->core_cache->reg_list[i].valid = true;
mips64.c:251mips64_set_core_reg()
reg->valid = true;
mips64.c:268mips64_read_core_reg()
mips64->core_cache->reg_list[num].valid = true;
mips64.c:287mips64_write_core_reg()
mips64->core_cache->reg_list[num].valid = true;
mips64.c:300mips64_invalidate_core_regs()
mips64->core_cache->reg_list[i].valid = false;
mips_m4k.c:448mips_m4k_internal_restore()
mips_m4k.c:542mips_m4k_step()
mips_mips64.c:629mips_mips64_resume()
pc->valid = true;
mips_mips64.c:721mips_mips64_step()
pc->valid = true;
or1k.c:339or1k_save_context()
if (!or1k->core_cache->reg_list[i].valid) {
or1k.c:416or1k_read_core_reg()
or1k->core_cache->reg_list[num].valid = true;
or1k.c:445or1k_write_core_reg()
or1k->core_cache->reg_list[num].valid = true;
or1k.c:480or1k_set_core_reg()
reg->valid = true;
or1k.c:534or1k_build_reg_cache()
reg_list[i].valid = false;
register.c:100register_cache_invalidate()
reg->valid = false;
register.c:113register_set_dummy_core_reg()
reg->valid = true;
riscv-011.c:1128execute_resume()
if (mstatus_reg->valid) {
riscv-011.c:1208reg_cache_get()
if (!r->valid) {
riscv-011.c:1222reg_cache_set()
r->valid = true;
riscv-011.c:1229update_mstatus_actual()
if (mstatus_reg->valid) {
riscv-011.c:1380get_register()
riscv.c:1797riscv_get_gdb_reg_list_internal()
!target->reg_cache->reg_list[i].valid) {
riscv.c:3235riscv_invalidate_register_cache()
reg->valid = false;
riscv.c:3326riscv_set_register()
reg->valid = gdb_regno_cacheable(regid, true);
riscv.c:3328riscv_set_register()
reg->valid = false;
riscv.c:3330riscv_set_register()
target_name(target), value, reg->name, reg->valid);
riscv.c:3348riscv_get_register()
if (reg && reg->valid) {
riscv.c:3365riscv_get_register()
reg->valid = gdb_regno_cacheable(regid, false);
riscv.c:3719register_get()
riscv.c:3722register_get()
str, reg->name, reg->valid);
riscv.c:3735register_set()
str, reg->name, reg->valid);
riscv.c:3744register_set()
riscv.c:3978riscv_init_registers()
r->valid = false;
stm8.c:566stm8_set_core_reg()
reg->valid = true;
stm8.c:582stm8_save_context()
if (!stm8->core_cache->reg_list[i].valid)
stm8.c:1015stm8_resume()
stm8->core_cache->reg_list[STM8_PC].valid = true;
stm8.c:1136stm8_read_core_reg()
stm8->core_cache->reg_list[num].valid = true;
stm8.c:1155stm8_write_core_reg()
stm8->core_cache->reg_list[num].valid = true;
stm8.c:1217stm8_build_reg_cache()
reg_list[i].valid = false;
stm8.c:1314stm8_step()
stm8->core_cache->reg_list[STM8_PC].valid = true;
stm8.c:1847stm8_run_algorithm()
if (!stm8->core_cache->reg_list[i].valid)
stm8.c:1927stm8_run_algorithm()
stm8->core_cache->reg_list[i].valid = true;
target.c:3058handle_reg_command()
if (reg->valid) {
target.c:3123handle_reg_command()
reg->valid = false;
target.c:3125handle_reg_command()
if (!reg->valid) {
target.c:4871target_jim_get_reg()
if (force || !reg->valid) {
x86_32_common.c:932set_debug_regs()
x86_32->cache->reg_list[bp_num+DR0].valid = true;
x86_32_common.c:935set_debug_regs()
x86_32->cache->reg_list[DR6].valid = true;
x86_32_common.c:938set_debug_regs()
x86_32->cache->reg_list[DR7].valid = true;
x86_32_common.c:963unset_debug_regs()
x86_32->cache->reg_list[bp_num+DR0].valid = true;
x86_32_common.c:966unset_debug_regs()
x86_32->cache->reg_list[DR6].valid = true;
x86_32_common.c:969unset_debug_regs()
x86_32->cache->reg_list[DR7].valid = true;
xscale.c:205xscale_read_dcsr()
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
xscale.c:617xscale_write_dcsr()
xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
xscale.c:861xscale_debug_entry()
arm->core_cache->reg_list[0].valid = true;
xscale.c:867xscale_debug_entry()
arm->pc->valid = true;
xscale.c:874xscale_debug_entry()
arm->core_cache->reg_list[i].valid = true;
xscale.c:894xscale_debug_entry()
arm->spsr->valid = true;
xscale.c:906xscale_debug_entry()
r->valid = true;
xscale.c:912xscale_debug_entry()
xscale->reg_cache->reg_list[i].valid = false;
xscale.c:1657xscale_full_context()
mode, j).valid)
xscale.c:1681xscale_full_context()
r->valid = true;
xscale.c:1692xscale_full_context()
r->valid = true;
xscale.c:2417xscale_get_reg()
reg->valid = true;
xscale.c:2883xscale_build_reg_cache()
(*cache_p)->reg_list[i].valid = false;
xtensa.c:485xtensa_core_reg_set()
reg->valid = true;
xtensa.c:1446xtensa_fetch_all_regs()
reg_list[i].valid = true;
xtensa.c:1450xtensa_fetch_all_regs()
reg_list[i].valid = true;
xtensa.c:1453xtensa_fetch_all_regs()
reg_list[i].valid = false;
xtensa.c:2781xtensa_start_algorithm()
reg->valid = 1;
xtensa.c:2795xtensa_start_algorithm()
xtensa->core_cache->reg_list[eps_reg_idx].valid = 1;
xtensa.c:2880xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].valid = 0;
xtensa.c:2897xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].valid = 1;
xtensa.c:2974xtensa_build_reg_cache()
reg_list[didx].valid = false;

Data Use

Functions writing reg::valid
Functions reading reg::valid
all items filtered out
reg::valid