OpenOCD
xtensa::core_cache is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDxtensa::core_cache

xtensa::core_cache field

Syntax

struct reg_cache *core_cache;

References

LocationReferrerText
xtensa.h:246
struct reg_cache *core_cache;
xtensa.c:523xtensa_mark_register_dirty()
struct reg *reg_list = xtensa->core_cache->reg_list;
xtensa.c:669xtensa_write_dirty_registers()
struct reg *reg_list = xtensa->core_cache->reg_list;
xtensa.c:670xtensa_write_dirty_registers()
unsigned int reg_list_size = xtensa->core_cache->num_regs;
xtensa.c:995xtensa_imprecise_exception_occurred()
xtensa->core_cache->reg_list[ridx].name, reg);
xtensa.c:1012xtensa_imprecise_exception_clear()
xtensa->core_cache->reg_list[ridx].name, value);
xtensa.c:1066xtensa_reg_get()
struct reg *reg = &xtensa->core_cache->reg_list[reg_id];
xtensa.c:1073xtensa_reg_set()
struct reg *reg = &xtensa->core_cache->reg_list[reg_id];
xtensa.c:1147xtensa_cause_clear()
xtensa->core_cache->reg_list[XT_REG_IDX_DEBUGCAUSE].dirty = false;
xtensa.c:1177xtensa_assert_reset()
register_cache_invalidate(xtensa->core_cache);
xtensa.c:1213xtensa_fetch_all_regs()
struct reg *reg_list = xtensa->core_cache->reg_list;
xtensa.c:1214xtensa_fetch_all_regs()
unsigned int reg_list_size = xtensa->core_cache->num_regs;
xtensa.c:1525xtensa_get_gdb_reg_list()
for (unsigned int i = 0; i < xtensa->core_cache->num_regs && k < num_regs; i++) {
xtensa.c:1526xtensa_get_gdb_reg_list()
if (xtensa->core_cache->reg_list[i].exist) {
xtensa.c:1535xtensa_get_gdb_reg_list()
(*reg_list)[sparse_idx] = &xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx];
xtensa.c:1541xtensa_get_gdb_reg_list()
(*reg_list)[sparse_idx - XT_REG_IDX_ARFIRST] = &xtensa->core_cache->reg_list[i];
xtensa.c:1543xtensa_get_gdb_reg_list()
(*reg_list)[sparse_idx] = &xtensa->core_cache->reg_list[i];
xtensa.c:1547xtensa_get_gdb_reg_list()
(*reg_list)[XT_PC_DBREG_NUM_BASE] = &xtensa->core_cache->reg_list[i];
xtensa.c:1823xtensa_do_step()
xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx].name,
xtensa.c:1921xtensa_do_step()
xtensa->core_cache->reg_list[xtensa->eps_dbglevel_idx].name,
xtensa.c:2732xtensa_start_algorithm()
for (unsigned int i = 0; i < xtensa->core_cache->num_regs; i++) {
xtensa.c:2733xtensa_start_algorithm()
struct reg *reg = &xtensa->core_cache->reg_list[i];
xtensa.c:2764xtensa_start_algorithm()
struct reg *reg = register_get_by_name(xtensa->core_cache, reg_params[i].reg_name, 0);
xtensa.c:2778xtensa_start_algorithm()
reg = &xtensa->core_cache->reg_list[reg_id];
xtensa.c:2795xtensa_start_algorithm()
xtensa->core_cache->reg_list[eps_reg_idx].valid = 1;
xtensa.c:2840xtensa_wait_algorithm()
struct reg *reg = register_get_by_name(xtensa->core_cache, reg_params[i].reg_name, 0);
xtensa.c:2867xtensa_wait_algorithm()
for (int i = xtensa->core_cache->num_regs - 1; i >= 0; i--) {
xtensa.c:2868xtensa_wait_algorithm()
struct reg *reg = &xtensa->core_cache->reg_list[i];
xtensa.c:2875xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].name,
xtensa.c:2879xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].dirty = 0;
xtensa.c:2880xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].valid = 0;
xtensa.c:2884xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].name,
xtensa.c:2889xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].name,
xtensa.c:2893xtensa_wait_algorithm()
LOG_DEBUG("restoring register %s %u-bits", xtensa->core_cache->reg_list[i].name, reg->size);
xtensa.c:2896xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].dirty = 1;
xtensa.c:2897xtensa_wait_algorithm()
xtensa->core_cache->reg_list[i].valid = 1;
xtensa.c:3067xtensa_build_reg_cache()
xtensa->core_cache = reg_cache;
xtensa.c:3454xtensa_free_reg_cache()
struct reg_cache *cache = xtensa->core_cache;
xtensa.c:3466xtensa_free_reg_cache()
xtensa->core_cache = NULL;

Data Use

Type of xtensa::core_cache
xtensa::core_cache
all items filtered out