OpenOCD
armv7m_common::arm is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDarmv7m_common::arm

armv7m_common::arm field

Syntax

struct arm arm;

References

LocationReferrerText
armv7m.h:225
struct arm arm;
armv7m.c:172armv7m_restore_context()
struct reg_cache *cache = armv7m->arm.core_cache;
armv7m.c:186armv7m_restore_context()
int retval = armv7m->arm.write_core_reg(target, r, i, ARM_MODE_ANY, r->value);
armv7m.c:337armv7m_read_core_reg()
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
armv7m.c:408armv7m_write_core_reg()
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
armv7m.c:466armv7m_get_gdb_reg_list()
size = armv7m->arm.core_cache->num_regs;
armv7m.c:475armv7m_get_gdb_reg_list()
(*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
armv7m.c:516armv7m_start_algorithm()
enum arm_mode core_mode = armv7m->arm.core_mode;
armv7m.c:533armv7m_start_algorithm()
for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
armv7m.c:534armv7m_start_algorithm()
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
armv7m.c:562armv7m_start_algorithm()
register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, false);
armv7m.c:591armv7m_start_algorithm()
struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
armv7m.c:607armv7m_start_algorithm()
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
armv7m.c:609armv7m_start_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m.c:610armv7m_start_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
armv7m.c:654armv7m_wait_algorithm()
uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
armv7m.c:676armv7m_wait_algorithm()
struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
armv7m.c:696armv7m_wait_algorithm()
for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
armv7m.c:697armv7m_wait_algorithm()
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
armv7m.c:714armv7m_wait_algorithm()
if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
armv7m.c:716armv7m_wait_algorithm()
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
armv7m.c:718armv7m_wait_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m.c:719armv7m_wait_algorithm()
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
armv7m.c:722armv7m_wait_algorithm()
armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
armv7m.c:731armv7m_arch_state()
struct arm *arm = &armv7m->arm;
armv7m.c:766armv7m_build_reg_cache()
struct arm *arm = &armv7m->arm;
armv7m.c:829armv7m_free_reg_cache()
struct arm *arm = &armv7m->arm;
armv7m.c:862armv7m_init_arch_info()
struct arm *arm = &armv7m->arm;
armv7m.c:1068armv7m_maybe_skip_bkpt_inst()
struct reg *r = armv7m->arm.pc;
armv7m.h:264target_to_armv7m()
return container_of(target->arch_info, struct armv7m_common, arm);
cortex_m.c:235cortex_m_slow_read_all_regs()
const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
cortex_m.c:242cortex_m_slow_read_all_regs()
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
cortex_m.c:244cortex_m_slow_read_all_regs()
int retval = armv7m->arm.read_core_reg(target, r, reg_id, ARM_MODE_ANY);
cortex_m.c:289cortex_m_fast_read_all_regs()
const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
cortex_m.c:300cortex_m_fast_read_all_regs()
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
cortex_m.c:363cortex_m_fast_read_all_regs()
struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
cortex_m.c:373cortex_m_fast_read_all_regs()
struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
cortex_m.c:611cortex_m_endreset_event()
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
cortex_m.c:690cortex_m_endreset_event()
register_cache_invalidate(armv7m->arm.core_cache);
cortex_m.c:735cortex_m_examine_exception_reason()
struct adiv5_dap *swjdp = armv7m->arm.dap;
cortex_m.c:814cortex_m_erratum_check_breakpoint()
struct arm *arm = &armv7m->arm;
cortex_m.c:849cortex_m_debug_entry()
struct arm *arm = &armv7m->arm;
cortex_m.c:870cortex_m_debug_entry()
if (armv7m->arm.arch == ARM_ARCH_V8M) {
cortex_m.c:1021cortex_m_poll_one()
struct arm *arm = &armv7m->arm;
cortex_m.c:1033cortex_m_poll_one()
register_cache_invalidate(armv7m->arm.core_cache);
cortex_m.c:1076cortex_m_poll_one()
register_cache_invalidate(armv7m->arm.core_cache);
cortex_m.c:1262cortex_m_soft_reset_halt()
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
cortex_m.c:1323cortex_m_restore_one()
r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
cortex_m.c:1345cortex_m_restore_one()
r = armv7m->arm.cpsr;
cortex_m.c:1352cortex_m_restore_one()
r = armv7m->arm.pc;
cortex_m.c:1407cortex_m_restart_one()
register_cache_invalidate(armv7m->arm.core_cache);
cortex_m.c:1483cortex_m_step()
struct reg *pc = armv7m->arm.pc;
cortex_m.c:1645cortex_m_step()
register_cache_invalidate(armv7m->arm.core_cache);
cortex_m.c:1848cortex_m_assert_reset()
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
cortex_m.c:1885cortex_m_assert_reset()
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
cortex_m.c:1942cortex_m_assert_reset()
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
cortex_m.c:1991cortex_m_assert_reset()
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
cortex_m.c:2397cortex_m_read_memory()
if (armv7m->arm.arch == ARM_ARCH_V6M) {
cortex_m.c:2411cortex_m_write_memory()
if (armv7m->arm.arch == ARM_ARCH_V6M) {
cortex_m.c:2705cortex_m_has_tz()
if (armv7m->arm.arch != ARM_ARCH_V8M)
cortex_m.c:2742cortex_m_examine()
struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
cortex_m.c:2795cortex_m_examine()
armv7m->arm.arch = cortex_m->core_info->arch;
cortex_m.c:2858cortex_m_examine()
cortex_m->vectreset_supported = armv7m->arm.arch == ARM_ARCH_V7M;
cortex_m.c:2863cortex_m_examine()
armv7m->arm.core_cache->reg_list[idx].exist = false;
cortex_m.c:2867cortex_m_examine()
armv7m->arm.core_cache->reg_list[idx].exist = false;
cortex_m.c:3048cortex_m_init_arch_info()
armv7m->arm.dap = dap;
cortex_m.h:291target_to_cm()
struct cortex_m_common, armv7m.arm);
hla_target.c:216adapter_load_context()
int num_regs = armv7m->arm.core_cache->num_regs;
hla_target.c:220adapter_load_context()
struct reg *r = &armv7m->arm.core_cache->reg_list[i];
hla_target.c:222adapter_load_context()
armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY);
hla_target.c:232adapter_debug_entry()
struct arm *arm = &armv7m->arm;
hla_target.c:323adapter_poll()
LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
hla_target.c:386hl_assert_reset()
register_cache_invalidate(armv7m->arm.core_cache);
hla_target.c:462adapter_resume()
pc = armv7m->arm.pc;
hla_target.c:489adapter_resume()
register_cache_invalidate(armv7m->arm.core_cache);
hla_target.c:535adapter_step()
struct reg *pc = armv7m->arm.pc;
hla_target.c:579adapter_step()
register_cache_invalidate(armv7m->arm.core_cache);
hla_target.c:587adapter_step()
LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
kinetis.c:511kinetis_mdm_halt()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
kinetis.c:574kinetis_mdm_reset()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
kinetis.c:615kinetis_mdm_mass_erase()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
kinetis.c:767kinetis_check_flash_security_status()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
kinetis_ke.c:508kinetis_ke_mdm_mass_erase()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
kinetis_ke.c:585kinetis_ke_check_flash_security_status()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
numicro.c:547numicro_get_arm_arch()
if (armv7m->arm.arch != ARM_ARCH_V6M) {
psoc6.c:227ipc_poll_lock_stat()
bool is_cm0 = (armv7m->arm.arch == ARM_ARCH_V6M);
psoc6.c:892handle_reset_halt()
bool is_cm0 = (armv7m->arm.arch == ARM_ARCH_V6M);
riot.c:408riot_create()
if (armv7m_target->arm.arch == ARM_ARCH_V6M)
rsl10.c:729rsl10_unlock_command()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
sim3x.c:939sim3x_mass_erase()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
sim3x.c:984sim3x_lock()
struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
stm32lx.c:722stm32lx_read_id_code()
if (armv7m->arm.arch == ARM_ARCH_V6M)

Data Use

Type of armv7m_common::arm
armv7m_common::arm
all items filtered out