buf_set_u32() is only used within OpenOCD.
 
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buf_set_u32() function

@file Support functions to access arbitrary bits in a byte array Sets @c num bits in @c _buffer, starting at the @c first bit, using the bits in @c value. This routine fast-paths writes of little-endian, byte-aligned, 32-bit words.

Syntax

static inline void buf_set_u32(uint8_t *_buffer,     unsigned first,     unsigned num,     uint32_t value);

Arguments

_buffer

The buffer whose bits will be set. Do not use uninitialized buffer or clang static analyzer emits a warning.

first

The bit offset in @c _buffer to start writing (0-31).

num

The number of bits from @c value to copy (1-32).

value

Up to 32 bits that will be copied to _buffer.

References

LocationReferrerText
binarybuffer.h:34
static inline void buf_set_u32(uint8_t *_buffer,
FLASHPlugin.c:202loaded_plugin_load()
buf_set_u32(reg_params[0].value, 0, 32, plugin->sp);
FLASHPlugin.c:439plugin_write_async()
buf_set_u32(reg_params[0].value, 0, 32, offset);
FLASHPlugin.c:440plugin_write_async()
buf_set_u32(reg_params[1].value, 0, 32, plugin_info->WorkArea.Address);
FLASHPlugin.c:441plugin_write_async()
buf_set_u32(reg_params[2].value, 0, 32, plugin_info->WorkArea.Address + workAreaSize);
FLASHPlugin.c:442plugin_write_async()
buf_set_u32(reg_params[3].value, 0, 32, size);
FLASHPlugin.c:443plugin_write_async()
buf_set_u32(reg_params[4].value, 0, 32, sp);
FLASHPlugin.c:444plugin_write_async()
buf_set_u32(reg_params[5].value, 0, 32, plugin_make_return_addr(return_addr));
FLASHPlugin.c:537call_plugin_func()
buf_set_u32(reg_params[1].value, 0, 32, plugin_make_return_addr(sp)); //Forced thumb mode!
FLASHPlugin.c:562call_plugin_func()
buf_set_u32(reg_params[r0ParamIndex + arg].value, 0, 32, argVal);
FLASHPlugin.c:571call_plugin_func()
buf_set_u32(reg_params[0].value, 0, 32, sp);
aarch64.c:1324aarch64_set_breakpoint()
buf_set_u32(code, 0, 32, opcode);
adi_v5_jtag.c:261adi_jtag_dp_scan_cmd()
buf_set_u32(&cmd->out_addr_buf, 0, 3, ((cmd->reg_addr >> 1) & 0x6) | (cmd->rnw & 0x1));
adi_v5_jtag.c:366adi_jtag_dp_scan_u32()
buf_set_u32(out_value_buf, 0, 32, (uint32_t)sel);
adi_v5_jtag.c:376adi_jtag_dp_scan_u32()
buf_set_u32(out_value_buf, 0, 32, outvalue);
adi_v5_jtag.c:582jtagdp_overrun_check()
buf_set_u32(out_value_buf, 0, 32, (uint32_t)(el->dp_select));
aduc702x.c:221aduc702x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
aduc702x.c:222aduc702x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, thisrun_count/2);
aduc702x.c:223aduc702x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
aduc702x.c:224aduc702x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
aducm302x.c:401aducm302x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
aducm302x.c:402aducm302x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
aducm302x.c:403aducm302x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
aducm302x.c:404aducm302x_write_block()
buf_set_u32(reg_params[3].value, 0, 32, dwcount);
aducm302x.c:405aducm302x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, FLASH_CTRL_BASE);
aducm302x.c:406aducm302x_write_block()
buf_set_u32(reg_params[5].value, 0, 32, CMD_WRITE);
aducm360.c:263aducm360_write_block_sync()
buf_set_u32(reg_params[0].value, 0, 32, target_buffer->address); /*SRC */
aducm360.c:264aducm360_write_block_sync()
buf_set_u32(reg_params[1].value, 0, 32, address); /*DST */
aducm360.c:265aducm360_write_block_sync()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count); /*COUNT */
aducm360.c:266aducm360_write_block_sync()
buf_set_u32(reg_params[3].value, 0, 32, 0); /*NOT USED*/
aducm360.c:377aducm360_write_block_async()
buf_set_u32(reg_params[0].value, 0, 32, target_buffer->address);
aducm360.c:378aducm360_write_block_async()
buf_set_u32(reg_params[1].value, 0, 32, target_buffer->address + target_buffer->size);
aducm360.c:379aducm360_write_block_async()
buf_set_u32(reg_params[2].value, 0, 32, address);
aducm360.c:380aducm360_write_block_async()
buf_set_u32(reg_params[3].value, 0, 32, wcount);
arc.c:631arc_set_register_value()
buf_set_u32(value_buf, 0, 32, value);
arc.c:2102arc_step()
buf_set_u32(pc->value, 0, 32, address);
arc_jtag.c:45arc_jtag_enque_write_ir()
buf_set_u32(instr_buffer, 0, field.num_bits, new_instr);
arc_jtag.c:98arc_jtag_enque_write_dr()
buf_set_u32(out_value, 0, 32, data);
arc_jtag.c:135arc_jtag_enque_set_transaction()
buf_set_u32(out_value, 0, ARC_TRANSACTION_CMD_REG_LENGTH, new_trans);
arm-jtag-ew.c:175armjtagew_speed()
buf_set_u32(usb_out_buffer + 1, 0, 32, speed*1000);
arm-jtag-ew.c:602armjtagew_tap_execute()
buf_set_u32(usb_out_buffer + 1, 0, 16, byte_length);
arm11.c:432arm11_nextpc()
buf_set_u32(value, 0, 32, address);
arm720t.c:43arm720t_scan_cp15()
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
arm720t.c:350arm720t_soft_reset_halt()
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm7_9_common.c:690arm7_9_execute_fast_sys_speed()
buf_set_u32(check_value, 0, 32, 0x9);
arm7_9_common.c:691arm7_9_execute_fast_sys_speed()
buf_set_u32(check_mask, 0, 32, 0x9);
arm7_9_common.c:1019arm7_9_clear_halt()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
arm7_9_common.c:1105arm7_9_soft_reset_halt()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
arm7_9_common.c:1106arm7_9_soft_reset_halt()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
arm7_9_common.c:1107arm7_9_soft_reset_halt()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
arm7_9_common.c:1138arm7_9_soft_reset_halt()
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm7_9_common.c:1146arm7_9_soft_reset_halt()
buf_set_u32(r->value, 0, 32, 0xffffffff);
arm7_9_common.c:1195arm7_9_halt()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
arm7_9_common.c:1245arm7_9_debug_entry()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
arm7_9_common.c:1246arm7_9_debug_entry()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
arm7_9_common.c:1247arm7_9_debug_entry()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
arm7_9_common.c:1337arm7_9_debug_entry()
buf_set_u32(r->value, 0, 32, context[i]);
arm7_9_common.c:1352arm7_9_debug_entry()
buf_set_u32(arm->spsr->value, 0, 32, spsr);
arm7_9_common.c:1480arm7_9_full_context()
buf_set_u32(read_cache[read_cache_idx].reg_p, 0, 32, read_cache[read_cache_idx].value);
arm7_9_common.c:1722arm7_9_resume()
buf_set_u32(arm->pc->value, 0, 32, address);
arm7_9_common.c:1770arm7_9_resume()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
arm7_9_common.c:1817arm7_9_resume()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
arm7_9_common.c:1820arm7_9_resume()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
arm7_9_common.c:1917arm7_9_step()
buf_set_u32(arm->pc->value, 0, 32, address);
arm7_9_common.c:2034arm7_9_read_core_reg()
buf_set_u32(r->value, 0, 32, value);
arm7_9_common.c:2311arm7_9_write_memory()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
arm7_9_common.c:2450arm7_9_write_memory()
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
arm7_9_common.c:2630arm7_9_bulk_write_memory()
buf_set_u32(reg_params[0].value, 0, 32, address);
arm7_9_common.c:2833arm7_9_setup_semihosting()
buf_set_u32(vector_catch->value, 2, 1, enable);
arm7tdmi.c:88arm7tdmi_clock_out_inner()
buf_set_u32(out_value, 0, 32, flip_u32(out, 32));
arm920t.c:136arm920t_write_cp15_physical()
buf_set_u32(value_buf, 0, 32, value);
arm920t.c:198arm920t_execute_cp15()
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
arm920t.c:776arm920t_soft_reset_halt()
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm926ejs.c:52arm926ejs_cp15_read()
buf_set_u32(address_buf, 0, 14, address);
arm926ejs.c:137arm926ejs_cp15_write()
buf_set_u32(address_buf, 0, 14, address);
arm926ejs.c:138arm926ejs_cp15_write()
buf_set_u32(value_buf, 0, 32, value);
arm926ejs.c:571arm926ejs_soft_reset_halt()
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm946e.c:186arm946e_write_cp15()
buf_set_u32(value_buf, 0, 32, value);
arm966e.c:136arm966e_write_cp15()
buf_set_u32(value_buf, 0, 32, value);
arm9tdmi.c:134arm9tdmi_clock_out()
buf_set_u32(out_buf, 0, 32, out);
arm9tdmi.c:136arm9tdmi_clock_out()
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
arm9tdmi.c:139arm9tdmi_clock_out()
buf_set_u32(&sysspeed_buf, 2, 1, 1);
arm9tdmi.c:678arm9tdmi_enable_single_step()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
arm9tdmi.c:689arm9tdmi_disable_single_step()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
arm9tdmi.c:848handle_arm9tdmi_catch_vectors_command()
buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
arm_dpm.c:197dpm_read_reg_u64()
buf_set_u32(r->value, 0, 32, value_r0);
arm_dpm.c:198dpm_read_reg_u64()
buf_set_u32(r->value + 4, 0, 32, value_r1);
arm_dpm.c:266arm_dpm_read_reg()
buf_set_u32(r->value, 0, 32, value);
arm_io.c:160arm_nandwrite()
buf_set_u32(reg_params[0].value, 0, 32, nand->data);
arm_io.c:161arm_nandwrite()
buf_set_u32(reg_params[1].value, 0, 32, target_buf);
arm_io.c:162arm_nandwrite()
buf_set_u32(reg_params[2].value, 0, 32, size);
arm_io.c:266arm_nandread()
buf_set_u32(reg_params[0].value, 0, 32, target_buf);
arm_io.c:267arm_nandread()
buf_set_u32(reg_params[1].value, 0, 32, nand->data);
arm_io.c:268arm_nandread()
buf_set_u32(reg_params[2].value, 0, 32, size);
arm_jtag.c:29arm_jtag_set_instr_inner()
buf_set_u32(t, 0, field.num_bits, new_instr);
arm_jtag.c:49arm_jtag_scann_inner()
buf_set_u32(out_value, 0, jtag_info->scann_size, new_scan_chain);
arm_semihosting.c:85post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:89post_result()
buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32,
arm_semihosting.c:100post_result()
buf_set_u32(arm->cpsr->value, 0, 32, spsr);
arm_semihosting.c:117post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:121post_result()
buf_set_u32(arm->pc->value, 0, 32, pc + 4);
arm_semihosting.c:125post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_semihosting.c:129post_result()
buf_set_u32(arm->pc->value, 0, 32, pc + 2);
arm_semihosting.c:137post_result()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm_simulator.c:648armv4_5_set_reg()
buf_set_u32(arm->core_cache->reg_list[reg].value, 0, 32, value);
arm_simulator.c:663armv4_5_set_reg_mode()
armv4_5.c:448arm_set_cpsr()
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
armv4_5.c:624armv4_5_set_core_reg()
buf_set_u32(t, 0, 32, value);
armv4_5.c:629armv4_5_set_core_reg()
buf_set_u32(reg->value, 0, 32, value);
armv4_5.c:632armv4_5_set_core_reg()
buf_set_u32(reg->value + 4, 0, 32, value);
armv4_5.c:1487armv4_5_run_algorithm_inner()
buf_set_u32(arm->cpsr->value, 0, 5,
armv4_5.c:1544armv4_5_run_algorithm_inner()
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
armv4_5.c:1557armv4_5_run_algorithm_inner()
armv4_5.c:1638arm_checksum_memory()
buf_set_u32(reg_params[0].value, 0, 32, address);
armv4_5.c:1639arm_checksum_memory()
buf_set_u32(reg_params[1].value, 0, 32, count);
armv4_5.c:1717arm_blank_check_memory()
buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
armv4_5.c:1720arm_blank_check_memory()
buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
armv4_5.c:1723arm_blank_check_memory()
buf_set_u32(reg_params[2].value, 0, 32, erased_value);
armv7m.c:358armv7m_read_core_reg()
buf_set_u32(r->value, 0, 32, reg_value);
armv7m.c:366armv7m_read_core_reg()
buf_set_u32(r->value + 4, 0, 32, reg_value);
armv7m.c:592armv7m_start_algorithm()
buf_set_u32(reg->value, 0, 32, 0x01000000);
armv7m.c:607armv7m_start_algorithm()
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
armv7m.c:692armv7m_wait_algorithm()
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
armv7m.c:706armv7m_wait_algorithm()
buf_set_u32(reg->value,
armv7m.c:716armv7m_wait_algorithm()
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
armv7m.c:909armv7m_checksum_memory()
buf_set_u32(reg_params[0].value, 0, 32, address);
armv7m.c:910armv7m_checksum_memory()
buf_set_u32(reg_params[1].value, 0, 32, count);
armv7m.c:1013armv7m_blank_check_memory()
buf_set_u32(reg_params[0].value, 0, 32, erase_check_params->address);
armv7m.c:1016armv7m_blank_check_memory()
buf_set_u32(reg_params[1].value, 0, 32, erased_word);
armv7m.c:1084armv7m_maybe_skip_bkpt_inst()
buf_set_u32(r->value, 0, 32, pc);
armv8.c:933armv8_set_cpsr()
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
armv8.c:1767armv8_set_core_reg32()
buf_set_u32(reg->value, 0, 32, value);
atsame5.c:560same5_modify_user_row()
buf_set_u32(buf_val, startb, endb + 1 - startb, value);
atsame5.c:561same5_modify_user_row()
buf_set_u32(buf_mask, startb, endb + 1 - startb, 0xffffffff);
atsame5.c:604same5_protect()
buf_set_u32(mask, first, last + 1 - first, 0xffffffff);
avr32_ap7k.c:101avr32_read_core_reg()
buf_set_u32(ap7k->core_cache->reg_list[num].value, 0, 32, reg_value);
avr32_ap7k.c:150avr32_set_core_reg()
buf_set_u32(reg->value, 0, 32, value);
avr32_jtag.c:32avr32_jtag_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
avr32_jtag.c:61avr32_jtag_nexus_set_address()
buf_set_u32(addr_buf, 0, 1, mode);
avr32_jtag.c:62avr32_jtag_nexus_set_address()
buf_set_u32(addr_buf, 1, 7, addr);
avr32_jtag.c:141avr32_jtag_nexus_write_data()
buf_set_u32(data_buf, 0, 32, data);
avr32_jtag.c:192avr32_jtag_mwa_set_address()
buf_set_u32(slave_buf, 0, 4, slave);
avr32_jtag.c:193avr32_jtag_mwa_set_address()
buf_set_u32(addr_buf, 0, 1, mode);
avr32_jtag.c:194avr32_jtag_mwa_set_address()
buf_set_u32(addr_buf, 1, 30, addr >> 2);
avr32_jtag.c:267avr32_jtag_mwa_write_data()
buf_set_u32(data_buf, 0, 32, data);
bluenrg-x.c:315bluenrgx_write()
buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_stack->address);
bluenrg-x.c:318bluenrgx_write()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
bluenrg-x.c:320bluenrgx_write()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
bluenrg-x.c:322bluenrgx_write()
buf_set_u32(reg_params[2].value, 0, 32, address);
bluenrg-x.c:324bluenrgx_write()
buf_set_u32(reg_params[3].value, 0, 32, count);
bluenrg-x.c:326bluenrgx_write()
buf_set_u32(mem_params[0].value, 0, 32, bluenrgx_info->flash_ptr->flash_regs_base);
cc26xx.c:226cc26xx_mass_erase()
buf_set_u32(algo_params.address, 0, 32, 0);
cc26xx.c:227cc26xx_mass_erase()
buf_set_u32(algo_params.length, 0, 32, 4);
cc26xx.c:228cc26xx_mass_erase()
buf_set_u32(algo_params.command, 0, 32, CC26XX_CMD_ERASE_ALL);
cc26xx.c:229cc26xx_mass_erase()
buf_set_u32(algo_params.status, 0, 32, CC26XX_BUFFER_FULL);
cc26xx.c:298cc26xx_erase()
buf_set_u32(algo_params.address, 0, 32, address);
cc26xx.c:299cc26xx_erase()
buf_set_u32(algo_params.length, 0, 32, length);
cc26xx.c:300cc26xx_erase()
buf_set_u32(algo_params.command, 0, 32, CC26XX_CMD_ERASE_SECTORS);
cc26xx.c:301cc26xx_erase()
buf_set_u32(algo_params.status, 0, 32, CC26XX_BUFFER_FULL);
cc26xx.c:341cc26xx_write()
buf_set_u32(algo_params[0].command, 0, 32, CC26XX_CMD_PROGRAM);
cc26xx.c:342cc26xx_write()
buf_set_u32(algo_params[1].command, 0, 32, CC26XX_CMD_PROGRAM);
cc26xx.c:364cc26xx_write()
buf_set_u32(algo_params[index].address, 0, 32, address);
cc26xx.c:365cc26xx_write()
buf_set_u32(algo_params[index].length, 0, 32, size);
cc26xx.c:366cc26xx_write()
buf_set_u32(algo_params[index].status, 0, 32, CC26XX_BUFFER_FULL);
cc3220sf.c:273cc3220sf_write()
buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address);
cc3220sf.c:274cc3220sf_write()
buf_set_u32(reg_params[1].value, 0, 32, head_address);
cc3220sf.c:275cc3220sf_write()
buf_set_u32(reg_params[2].value, 0, 32, 1);
cc3220sf.c:306cc3220sf_write()
buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address);
cc3220sf.c:307cc3220sf_write()
buf_set_u32(reg_params[1].value, 0, 32, address);
cc3220sf.c:343cc3220sf_write()
buf_set_u32(reg_params[2].value, 0, 32, words);
cc3220sf.c:387cc3220sf_write()
buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address);
cc3220sf.c:388cc3220sf_write()
buf_set_u32(reg_params[1].value, 0, 32, address);
cc3220sf.c:389cc3220sf_write()
buf_set_u32(reg_params[2].value, 0, 32, 1);
cfi.c:1300cfi_intel_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
cfi.c:1301cfi_intel_write_block()
buf_set_u32(reg_params[1].value, 0, 32, address);
cfi.c:1302cfi_intel_write_block()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
cfi.c:1304cfi_intel_write_block()
buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
cfi.c:1305cfi_intel_write_block()
buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
cfi.c:1306cfi_intel_write_block()
buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
cfi.c:1532cfi_spansion_write_block_mips()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
cfi.c:1533cfi_spansion_write_block_mips()
buf_set_u32(reg_params[1].value, 0, 32, address);
cfi.c:1534cfi_spansion_write_block_mips()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
cfi.c:1535cfi_spansion_write_block_mips()
buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
cfi.c:1536cfi_spansion_write_block_mips()
buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
cfi.c:1537cfi_spansion_write_block_mips()
buf_set_u32(reg_params[6].value, 0, 32, cfi_flash_address(bank, 0, pri_ext->_unlock1));
cfi.c:1538cfi_spansion_write_block_mips()
buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
cfi.c:1539cfi_spansion_write_block_mips()
buf_set_u32(reg_params[8].value, 0, 32, cfi_flash_address(bank, 0, pri_ext->_unlock2));
cfi.c:1540cfi_spansion_write_block_mips()
buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
cfi.c:1911cfi_spansion_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
cfi.c:1912cfi_spansion_write_block()
buf_set_u32(reg_params[1].value, 0, 32, address);
cfi.c:1913cfi_spansion_write_block()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
cfi.c:1914cfi_spansion_write_block()
buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
cfi.c:1915cfi_spansion_write_block()
buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
cfi.c:1916cfi_spansion_write_block()
buf_set_u32(reg_params[6].value, 0, 32, cfi_flash_address(bank, 0, pri_ext->_unlock1));
cfi.c:1917cfi_spansion_write_block()
buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
cfi.c:1918cfi_spansion_write_block()
buf_set_u32(reg_params[8].value, 0, 32, cfi_flash_address(bank, 0, pri_ext->_unlock2));
cfi.c:1919cfi_spansion_write_block()
buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
core.c:1094jtag_examine_chain_execute()
buf_set_u32(idcode_buffer, i * 32, 32, END_OF_CHAIN_FLAG);
core.c:1464jtag_tap_init()
buf_set_u32(tap->expected, 0, ir_len_bits, tap->ir_capture_value);
core.c:1465jtag_tap_init()
buf_set_u32(tap->expected_mask, 0, ir_len_bits, tap->ir_capture_mask);
cortex_a.c:882cortex_a_internal_restore()
buf_set_u32(arm->pc->value, 0, 32, resume_pc);
cortex_a.c:1190cortex_a_step()
buf_set_u32(r->value, 0, 32, address);
cortex_a.c:1329cortex_a_set_breakpoint()
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
cortex_a.c:1337cortex_a_set_breakpoint()
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
cortex_a.c:1341cortex_a_set_breakpoint()
buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
cortex_m.c:383cortex_m_fast_read_all_regs()
buf_set_u32(r->value, 0, 32, r_vals[ri++]);
cortex_m.c:388cortex_m_fast_read_all_regs()
buf_set_u32(r->value + 4, 0, 32, r_vals[ri++]);
cortex_m.c:1335cortex_m_restore_one()
buf_set_u32(r->value, 0, 1, 1);
cortex_m.c:1346cortex_m_restore_one()
buf_set_u32(r->value, 24, 1, 1);
cortex_m.c:1354cortex_m_restore_one()
buf_set_u32(r->value, 0, 32, *address);
cortex_m.c:1500cortex_m_step()
buf_set_u32(pc->value, 0, 32, address);
cortex_m.c:2082cortex_m_set_breakpoint()
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
cortex_m.c:2532cortex_m_dwt_get_reg()
buf_set_u32(state->value, 0, 32, tmp);
dsp563xx.c:375dsp563xx_read_core_reg()
buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
dsp563xx.c:423dsp563xx_set_core_reg()
buf_set_u32(reg->value, 0, reg->size, value);
dsp563xx.c:1458dsp563xx_run_algorithm()
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
dsp563xx.c:1654dsp563xx_read_memory()
buf_set_u32(buffer + i*sizeof(uint32_t), 0, 32,
dsp563xx.c:1656dsp563xx_read_memory()
buf_set_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32,
dsp563xx.c:1812dsp563xx_write_memory()
buf_set_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32,
dsp563xx.c:1814dsp563xx_write_memory()
buf_set_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32,
efinix.c:133efinix_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
efm32.c:845efm32x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
efm32.c:846efm32x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, count);
efm32.c:847efm32x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
efm32.c:848efm32x_write_block()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
efm32.c:849efm32x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, address);
em357.c:527em357_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
em357.c:528em357_write_block()
buf_set_u32(reg_params[1].value, 0, 32, address);
em357.c:529em357_write_block()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
em357.c:530em357_write_block()
buf_set_u32(reg_params[3].value, 0, 32, 0);
embeddedice.c:331embeddedice_setup()
buf_set_u32(dbg_ctrl->value, 4, 1, 0);
embeddedice.c:477embeddedice_set_reg()
buf_set_u32(reg->value, 0, reg->size, value);
embeddedice.c:563embeddedice_send()
buf_set_u32(field0_out, 0, 32, *data);
embeddedice.h:105embeddedice_write_reg_inner()
buf_set_u32(out_value, 0, 32, value);
esirisc.c:874esirisc_resume_or_step()
buf_set_u32(esirisc->epc->value, 0, esirisc->epc->size, address);
esirisc.c:1313esirisc_read_reg()
buf_set_u32(reg->value, 0, reg->size, data);
esirisc.c:1358esirisc_read_csr()
buf_set_u32(reg->value, 0, reg->size, data);
esirisc.c:1413esirisc_set_reg()
buf_set_u32(reg->value, 0, reg->size, value);
esirisc_jtag.c:32esirisc_jtag_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
esp32.c:299esp32_queue_tdi_idle()
buf_set_u32(t, 0, 1, value);
esp_algorithm.h:401esp_algorithm_user_arg_set_uint()
buf_set_u32(param->value, 0, param->size, val);
esp_xtensa_algorithm.c:60esp_xtensa_algo_regs_init_start()
buf_set_u32(params[0].value, 0, 32, 0); /* a0 TODO: move to tramp */
esp_xtensa_algorithm.c:61esp_xtensa_algo_regs_init_start()
buf_set_u32(params[1].value, 0, 32, stack_addr); /* a1 */
esp_xtensa_algorithm.c:62esp_xtensa_algo_regs_init_start()
buf_set_u32(params[2].value, 0, 32, run->stub.entry); /* a8 */
esp_xtensa_algorithm.c:63esp_xtensa_algo_regs_init_start()
buf_set_u32(params[3].value, 0, 32, 0x0); /* initial window base TODO: move to tramp */
esp_xtensa_algorithm.c:64esp_xtensa_algo_regs_init_start()
buf_set_u32(params[4].value, 0, 32, 0x1); /* initial window start TODO: move to tramp */
esp_xtensa_algorithm.c:65esp_xtensa_algo_regs_init_start()
buf_set_u32(params[5].value, 0, 32, 0x60025); /* enable WOE, UM and debug interrupts level (6) */
etb.c:45etb_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
etb.c:65etb_scann()
buf_set_u32(t, 0, field.num_bits, new_scan_chain);
etb.c:170etb_read_ram()
buf_set_u32(&temp1, 0, 7, 4);
etb.c:176etb_read_ram()
buf_set_u32(&temp2, 0, 1, 0);
etb.c:183etb_read_ram()
buf_set_u32(&temp2, 0, 1, 0);
etb.c:187etb_read_ram()
buf_set_u32(&temp1, 0, 7, 4);
etb.c:189etb_read_ram()
buf_set_u32(&temp1, 0, 7, 0);
etb.c:223etb_read_reg_w_check()
buf_set_u32(&temp1, 0, 7, reg_addr);
etb.c:231etb_read_reg_w_check()
buf_set_u32(&temp2, 0, 1, 0);
etb.c:241etb_read_reg_w_check()
buf_set_u32(&temp1, 0, 7, 0x0);
etb.c:263etb_set_reg()
buf_set_u32(reg->value, 0, reg->size, value);
etb.c:298etb_write_reg()
buf_set_u32(temp0, 0, 32, value);
etb.c:304etb_write_reg()
buf_set_u32(&temp1, 0, 7, reg_addr);
etb.c:310etb_write_reg()
buf_set_u32(&temp2, 0, 1, 1);
etm.c:446etm_setup()
buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
etm.c:522etm_read_reg_w_check()
buf_set_u32(&temp1, 0, 7, reg_addr);
etm.c:530etm_read_reg_w_check()
buf_set_u32(&temp2, 0, 1, 0);
etm.c:554etm_set_reg()
buf_set_u32(reg->value, 0, reg->size, value);
etm.c:603etm_write_reg()
buf_set_u32(tmp1, 0, 32, value);
etm.c:609etm_write_reg()
buf_set_u32(&tmp2, 0, 7, reg_addr);
etm.c:615etm_write_reg()
buf_set_u32(&tmp3, 0, 1, 1);
etm.c:1284handle_etm_tracemode_command()
buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
etm.c:1855handle_etm_start_command()
buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
etm.c:1892handle_etm_stop_command()
buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
etm.c:1940handle_etm_trigger_debug_command()
buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
feroceon.c:77feroceon_dummy_clock_out()
buf_set_u32(out_buf, 0, 32, 0);
feroceon.c:79feroceon_dummy_clock_out()
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
feroceon.c:413feroceon_set_dbgrq()
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
feroceon.c:523feroceon_bulk_write_memory()
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
feroceon.c:566feroceon_bulk_write_memory()
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
feroceon.c:570feroceon_bulk_write_memory()
buf_set_u32(arm->pc->value, 0, 32, save[i]);
feroceon.c:684feroceon_examine()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
feroceon.c:685feroceon_examine()
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
fm3.c:304fm3_erase()
buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
fm3.c:305fm3_erase()
buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
fm3.c:306fm3_erase()
buf_set_u32(reg_params[2].value, 0, 32, offset);
fm3.c:583fm3_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
fm3.c:584fm3_write_block()
buf_set_u32(reg_params[1].value, 0, 32, address);
fm3.c:585fm3_write_block()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
fm3.c:586fm3_write_block()
buf_set_u32(reg_params[3].value, 0, 32, u32_flash_seq_address1);
fm3.c:587fm3_write_block()
buf_set_u32(reg_params[4].value, 0, 32, u32_flash_seq_address2);
fm3.c:903fm3_chip_erase()
buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
fm3.c:904fm3_chip_erase()
buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
fm4.c:155fm4_flash_erase()
buf_set_u32(reg_params[0].value, 0, 32, (addr & ~0xffff) | 0xAA8);
fm4.c:156fm4_flash_erase()
buf_set_u32(reg_params[1].value, 0, 32, (addr & ~0xffff) | 0x554);
fm4.c:157fm4_flash_erase()
buf_set_u32(reg_params[2].value, 0, 32, addr);
fm4.c:290fm4_flash_write()
buf_set_u32(reg_params[0].value, 0, 32, (addr & ~0xffff) | 0xAA8);
fm4.c:291fm4_flash_write()
buf_set_u32(reg_params[1].value, 0, 32, (addr & ~0xffff) | 0x554);
fm4.c:292fm4_flash_write()
buf_set_u32(reg_params[2].value, 0, 32, addr);
fm4.c:293fm4_flash_write()
buf_set_u32(reg_params[3].value, 0, 32, data_workarea->address);
fm4.c:294fm4_flash_write()
buf_set_u32(reg_params[4].value, 0, 32, halfwords);
ftdi.c:392ftdi_execute_pathmove()
buf_set_u32(&tms_byte, bit_count++, 1, 0x0);
ftdi.c:395ftdi_execute_pathmove()
buf_set_u32(&tms_byte, bit_count++, 1, 0x1);
ftdi.c:1171ftdi_swd_queue_cmd()
buf_set_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3 + 1, 32, data);
ftdi.c:1172ftdi_swd_queue_cmd()
buf_set_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(data));
gatemate.c:172gatemate_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
gowin.c:209gowin_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
hla_target.c:464adapter_resume()
buf_set_u32(pc->value, 0, 32, address);
hla_target.c:546adapter_step()
buf_set_u32(pc->value, 0, 32, address);
intel.c:85intel_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
ipdbg.c:353ipdbg_shift_instr()
buf_set_u32(ir_out_val, 0, tap->ir_length, instr);
ipdbg.c:398ipdbg_shift_data()
ipdbg.c:527ipdbg_jtag_transfer_bytes()
buf_set_u32(hub->scratch_memory.dr_out_vals + i * dreg_buffer_size, 0,
ipdbg.c:996ipdbg_create_hub()
jlink.c:2078fill_buffer()
buf_set_u32(buf, tap_pos, 32, val);
jlink.c:2084fill_buffer()
buf_set_u32(buf, tap_pos, len, val);
jlink.c:2246jlink_swd_queue_cmd()
buf_set_u32(data_parity_trn, 0, 32, data);
jlink.c:2247jlink_swd_queue_cmd()
buf_set_u32(data_parity_trn, 32, 1, parity_u32(data));
jtagspi.c:89jtagspi_set_user_ir()
buf_set_u32(buf, 0, info->tap->ir_length, info->ir);
kinetis.c:1083kinetis_disable_wdog_algo()
buf_set_u32(reg_params[0].value, 0, 32, wdog_base);
kinetis.c:1353kinetis_write_block()
buf_set_u32(reg_params[0].value, 0, 32, address);
kinetis.c:1354kinetis_write_block()
buf_set_u32(reg_params[1].value, 0, 32, wcount);
kinetis.c:1355kinetis_write_block()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
kinetis.c:1356kinetis_write_block()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
kinetis.c:1357kinetis_write_block()
buf_set_u32(reg_params[4].value, 0, 32, FTFX_FSTAT);
kinetis_ke.c:713kinetis_ke_write_words()
buf_set_u32(&kinetis_ke_flash_write_code[flash_code_size-16], 0, 32, kinfo->ftmrx_fstat_addr);
kinetis_ke.c:714kinetis_ke_write_words()
buf_set_u32(&kinetis_ke_flash_write_code[flash_code_size-12], 0, 32, kinfo->ftmrx_fccobix_addr);
kinetis_ke.c:715kinetis_ke_write_words()
buf_set_u32(&kinetis_ke_flash_write_code[flash_code_size-8], 0, 32, kinfo->ftmrx_fccobhi_addr);
kinetis_ke.c:716kinetis_ke_write_words()
buf_set_u32(&kinetis_ke_flash_write_code[flash_code_size-4], 0, 32, kinfo->ftmrx_fccoblo_addr);
kinetis_ke.c:740kinetis_ke_write_words()
buf_set_u32(reg_params[0].value, 0, 32, address);
kinetis_ke.c:741kinetis_ke_write_words()
buf_set_u32(reg_params[1].value, 0, 32, words);
kinetis_ke.c:742kinetis_ke_write_words()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
kinetis_ke.c:743kinetis_ke_write_words()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
lakemont.c:348lakemont_set_core_reg()
buf_set_u32(reg->value, 0, 32, value);
lakemont.c:658read_hw_reg()
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
lakemont.c:679write_hw_reg()
buf_set_u32(reg_buf, 0, 32, regval);
lakemont.c:938lakemont_poll()
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
lakemont.c:1022lakemont_resume()
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
lakemont.c:1057lakemont_step()
buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
lakemont.c:1058lakemont_step()
buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
lattice.c:72lattice_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
lpc2000.c:781lpc2000_iap_call()
buf_set_u32(reg_params[0].value, 0, 32, iap_working_area->address + 0x08);
lpc2000.c:787lpc2000_iap_call()
buf_set_u32(reg_params[1].value, 0, 32, iap_working_area->address + 0x20);
lpc2000.c:791lpc2000_iap_call()
buf_set_u32(reg_params[2].value, 0, 32, iap_entry_point);
lpc2000.c:803lpc2000_iap_call()
buf_set_u32(reg_params[3].value, 0, 32,
lpc2000.c:808lpc2000_iap_call()
buf_set_u32(reg_params[4].value, 0, 32, (iap_working_area->address + 0x04) | 1);
lpc2000.c:818lpc2000_iap_call()
buf_set_u32(reg_params[3].value, 0, 32,
lpc2000.c:823lpc2000_iap_call()
buf_set_u32(reg_params[4].value, 0, 32, iap_working_area->address + 0x04);
lpc2000.c:1102lpc2000_write()
buf_set_u32((uint8_t *)buffer + (lpc2000_info->checksum_vector * 4), 0, 32, checksum);
lpc2900.c:1249lpc2900_write()
buf_set_u32(reg_params[0].value, 0, 32, warea->address);
lpc2900.c:1250lpc2900_write()
buf_set_u32(reg_params[1].value, 0, 32, offset);
lpc2900.c:1251lpc2900_write()
buf_set_u32(reg_params[2].value, 0, 32, this_npages);
lpc2900.c:1252lpc2900_write()
buf_set_u32(reg_params[3].value, 0, 32, FCTR);
lpc2900.c:1253lpc2900_write()
buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time);
lpcspifi.c:201lpcspifi_set_hw_mode()
buf_set_u32(reg_params[0].value, 0, 32, 12);
lpcspifi.c:203lpcspifi_set_hw_mode()
buf_set_u32(reg_params[1].value, 0, 32, (spifi_init_algorithm->address +
lpcspifi.c:536lpcspifi_erase()
buf_set_u32(reg_params[0].value, 0, 32, bank->sectors[first].offset);
lpcspifi.c:537lpcspifi_erase()
buf_set_u32(reg_params[1].value, 0, 32, last - first + 1);
lpcspifi.c:538lpcspifi_erase()
buf_set_u32(reg_params[2].value, 0, 32, lpcspifi_info->dev->erase_cmd);
lpcspifi.c:539lpcspifi_erase()
buf_set_u32(reg_params[3].value, 0, 32, bank->sectors[first].size);
lpcspifi.c:725lpcspifi_write()
buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
lpcspifi.c:726lpcspifi_write()
buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
lpcspifi.c:727lpcspifi_write()
buf_set_u32(reg_params[2].value, 0, 32, offset);
lpcspifi.c:728lpcspifi_write()
buf_set_u32(reg_params[3].value, 0, 32, count);
lpcspifi.c:729lpcspifi_write()
buf_set_u32(reg_params[4].value, 0, 32, page_size);
ls1_sap.c:98ls1_sap_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
ls1_sap.c:113ls1_sap_set_addr_high()
buf_set_u32(buf, 0, 16, addr_high);
max32xxx.c:406max32xxx_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
max32xxx.c:407max32xxx_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
max32xxx.c:408max32xxx_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
max32xxx.c:409max32xxx_write_block()
buf_set_u32(reg_params[3].value, 0, 32, wcount);
max32xxx.c:410max32xxx_write_block()
buf_set_u32(reg_params[4].value, 0, 32, info->flc_base);
mdr.c:263mdr_write_block()
buf_set_u32(reg_params[0].value, 0, 32, FLASH_REG_BASE);
mdr.c:264mdr_write_block()
buf_set_u32(reg_params[1].value, 0, 32, count);
mdr.c:265mdr_write_block()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
mdr.c:266mdr_write_block()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
mdr.c:267mdr_write_block()
buf_set_u32(reg_params[4].value, 0, 32, address);
mdr.c:532mdr_read()
buf_set_u32(buffer, i * 8, 32, buf);
mips32.c:257mips32_set_core_reg()
buf_set_u32(reg->value, 0, 32, value);
mips32.c:335mips32_read_core_reg()
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32.c:342mips32_read_core_reg()
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32.c:352mips32_read_core_reg()
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32.c:688mips32_run_algorithm()
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
mips32.c:699mips32_run_algorithm()
buf_set_u32(mips32->core_cache->reg_list[i].value,
mips32.c:1262mips32_checksum_memory()
buf_set_u32(reg_params[0].value, 0, 32, address);
mips32.c:1265mips32_checksum_memory()
buf_set_u32(reg_params[1].value, 0, 32, count);
mips32.c:1331mips32_blank_check_memory()
buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
mips32.c:1334mips32_blank_check_memory()
buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
mips32.c:1337mips32_blank_check_memory()
buf_set_u32(reg_params[2].value, 0, 32, erased_value);
mips_ejtag.c:34mips_ejtag_set_instr()
buf_set_u32(t, 0, field.num_bits, new_instr);
mips_ejtag.c:70mips_ejtag_add_scan_96()
buf_set_u32(out_scan, 0, 32, ctrl);
mips_ejtag.c:71mips_ejtag_add_scan_96()
buf_set_u32(out_scan + 4, 0, 32, data);
mips_ejtag.c:72mips_ejtag_add_scan_96()
buf_set_u32(out_scan + 8, 0, 32, 0);
mips_ejtag.c:122mips_ejtag_drscan_32_queued()
buf_set_u32(scan_out, 0, field.num_bits, data_out);
mips_ejtag.c:436mips_ejtag_fastdata_scan()
buf_set_u32(t, 0, 32, *data);
mips_m4k.c:446mips_m4k_internal_restore()
mips_m4k.c:452mips_m4k_internal_restore()
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode);
mips_m4k.c:540mips_m4k_step()
mrvlqspi.c:722mrvlqspi_flash_write()
buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
mrvlqspi.c:723mrvlqspi_flash_write()
buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
mrvlqspi.c:724mrvlqspi_flash_write()
buf_set_u32(reg_params[2].value, 0, 32, offset);
mrvlqspi.c:725mrvlqspi_flash_write()
buf_set_u32(reg_params[3].value, 0, 32, count);
mrvlqspi.c:726mrvlqspi_flash_write()
buf_set_u32(reg_params[4].value, 0, 32, page_size);
mrvlqspi.c:727mrvlqspi_flash_write()
buf_set_u32(reg_params[5].value, 0, 32, (uint32_t) mrvlqspi_info->reg_base);
msp432.c:173msp432_init_params()
msp432.c:174msp432_init_params()
buf_set_u32(algo_params->return_code, 0, 32, 0);
msp432.c:175msp432_init_params()
buf_set_u32(algo_params->_reserved0, 0, 32, 0);
msp432.c:176msp432_init_params()
buf_set_u32(algo_params->address, 0, 32, 0);
msp432.c:177msp432_init_params()
buf_set_u32(algo_params->length, 0, 32, 0);
msp432.c:178msp432_init_params()
msp432.c:179msp432_init_params()
msp432.c:180msp432_init_params()
msp432.c:181msp432_init_params()
buf_set_u32(algo_params->unlock_bsl, 0, 32, FLASH_LOCK_BSL);
msp432.c:190msp432_exec_cmd()
msp432.c:191msp432_exec_cmd()
buf_set_u32(algo_params->return_code, 0, 32, 0);
msp432.c:192msp432_exec_cmd()
msp432.c:193msp432_exec_cmd()
msp432.c:375msp432_init()
buf_set_u32(reg_params[0].value, 0, 32, ALGO_STACK_POINTER_ADDR);
msp432.c:452msp432_mass_erase()
buf_set_u32(algo_params.erase_param, 0, 32,
msp432.c:455msp432_mass_erase()
buf_set_u32(algo_params.unlock_bsl, 0, 32, FLASH_UNLOCK_BSL);
msp432.c:630msp432_erase()
buf_set_u32(algo_params.erase_param, 0, 32, FLASH_ERASE_INFO);
msp432.c:633msp432_erase()
buf_set_u32(algo_params.unlock_bsl, 0, 32, FLASH_UNLOCK_BSL);
msp432.c:649msp432_erase()
buf_set_u32(algo_params.address, 0, 32, bank->base +
msp432.c:738msp432_write()
buf_set_u32(algo_params.address, 0, 32, bank->base + offset);
msp432.c:739msp432_write()
buf_set_u32(algo_params.length, 0, 32, count);
msp432.c:745msp432_write()
buf_set_u32(algo_params.unlock_bsl, 0, 32, FLASH_UNLOCK_BSL);
niietcm4.c:1327niietcm4_write_block()
buf_set_u32(reg_params[0].value, 0, 32, flash_cmd);
niietcm4.c:1328niietcm4_write_block()
buf_set_u32(reg_params[1].value, 0, 32, count);
niietcm4.c:1329niietcm4_write_block()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
niietcm4.c:1330niietcm4_write_block()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
niietcm4.c:1331niietcm4_write_block()
buf_set_u32(reg_params[4].value, 0, 32, address);
nrf5.c:1196nrf5_ll_flash_write()
buf_set_u32(reg_params[0].value, 0, 32, bytes);
nrf5.c:1197nrf5_ll_flash_write()
buf_set_u32(reg_params[1].value, 0, 32, source->address);
nrf5.c:1198nrf5_ll_flash_write()
buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
nrf5.c:1199nrf5_ll_flash_write()
buf_set_u32(reg_params[3].value, 0, 32, address);
nrf5.c:1200nrf5_ll_flash_write()
buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
nrf5.c:1201nrf5_ll_flash_write()
buf_set_u32(reg_params[5].value, 0, 32, chip->map->watchdog_refresh_addr);
numicro.c:781numicro_writeblock()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
numicro.c:782numicro_writeblock()
buf_set_u32(reg_params[1].value, 0, 32, address);
numicro.c:783numicro_writeblock()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
or1k.c:414or1k_read_core_reg()
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
or1k.c:426or1k_read_core_reg()
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
or1k.c:478or1k_set_core_reg()
buf_set_u32(reg->value, 0, 32, value);
or1k.c:801or1k_resume_or_step()
buf_set_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value, 0,
or1k_tap_vjtag.c:146or1k_tap_vjtag_init()
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER1);
or1k_tap_vjtag.c:178or1k_tap_vjtag_init()
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER0);
or1k_tap_vjtag.c:265or1k_tap_vjtag_init()
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER1);
or1k_tap_vjtag.c:273or1k_tap_vjtag_init()
buf_set_u32(t, 0, dr_length, (vjtag_node_address << m_width) | ALT_VJTAG_CMD_DEBUG);
or1k_tap_vjtag.c:280or1k_tap_vjtag_init()
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER0);
osbdm.c:281osbdm_swap()
buf_set_u32(tdo, bit_idx, bit_count, tdo_data);
osbdm.c:410osbdm_add_pathmove()
buf_set_u32(next->tms, 0, num_states, tms);
osbdm.c:445osbdm_add_statemove()
buf_set_u32(next->tms, 0, len, tms);
osbdm.c:527osbdm_add_scan()
buf_set_u32(queue->tail->tms, queue->tail->len - 1, 1, 1);
pic32mm.c:529pic32mm_call_flash_loader()
buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
pic32mm.c:530pic32mm_call_flash_loader()
buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address_in_flash));
pic32mm.c:531pic32mm_call_flash_loader()
buf_set_u32(reg_params[2].value, 0, 32, word_count);
pic32mx.c:539pic32mx_write_block()
buf_set_u32(reg_params[0].value, 0, 32, virt2phys(source->address));
pic32mx.c:540pic32mx_write_block()
buf_set_u32(reg_params[1].value, 0, 32, virt2phys(address));
pic32mx.c:541pic32mx_write_block()
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
picoprobe.c:279picoprobe_swd_run_queue()
picoprobe.c:352picoprobe_swd_queue_cmd()
buf_set_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3 + 1, 32, data);
picoprobe.c:353picoprobe_swd_queue_cmd()
buf_set_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(data));
psoc4.c:308psoc4_sysreq()
buf_set_u32(reg_params[0].value, 0, 32,
psoc6.c:153sromalgo_prepare()
buf_set_u32(reg_params.value, 0, 32, g_stack_area->address + g_stack_area->size);
riscv-011.c:288dtmcontrol_scan()
buf_set_u32(out_value, 0, 32, out);
riscv-013.c:426dtmcontrol_scan()
buf_set_u32(out_value, 0, 32, out);
riscv-013.c:495dmi_scan()
riscv-013.c:496dmi_scan()
riscv-013.c:497dmi_scan()
buf_set_u32(out, DTM_DMI_ADDRESS_OFFSET, info->abits, address_out);
riscv-013.c:2518read_memory_bus_word()
buf_set_u32(buffer + i * 4, 0, 8 * MIN(size, 4), value);
riscv-013.c:2625read_memory_bus_v0()
buf_set_u32(t_buffer, 0, 8 * size, value);
riscv-013.c:2654read_memory_bus_v0()
buf_set_u32(t_buffer, 0, 8 * size, value);
riscv-013.c:2663read_memory_bus_v0()
buf_set_u32(t_buffer, 0, 8 * size, value);
riscv-013.c:2738read_memory_bus_v1()
buf_set_u32(buffer + next_read - address, 0, 8 * MIN(size, 4), value);
riscv-013.c:2763read_memory_bus_v1()
buf_set_u32(buffer + next_read - address, 0, 8 * MIN(size, 4), value);
riscv.c:301dtmcontrol_scan_via_bscan()
buf_set_u32(out_value, 0, 32, out);
riscv.c:387dtmcontrol_scan()
buf_set_u32(out_value, 0, 32, out);
riscv.c:890riscv_add_breakpoint()
buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
riscv.c:2741riscv_set_ir()
buf_set_u32(ir_idcode, 0, 32, value);
riscv.c:2743riscv_set_ir()
buf_set_u32(ir_dtmcontrol, 0, 32, value);
riscv.c:2745riscv_set_ir()
buf_set_u32(ir_dbus, 0, 32, value);
rp2040.c:113rp2040_call_rom_func()
buf_set_u32(args[i].value, 0, 32, argdata[i]);
rp2040.c:117rp2040_call_rom_func()
buf_set_u32(args[n_args].value, 0, 32, func_offset);
rp2040.c:120rp2040_call_rom_func()
buf_set_u32(args[n_args + 1].value, 0, 32, stacktop);
rs14100.c:273rs14100_erase()
buf_set_u32(reg_params[0].value, 0, 32, first);
rs14100.c:274rs14100_erase()
buf_set_u32(reg_params[1].value, 0, 32, last+1);
rs14100.c:531rs14100_write()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
rs14100.c:532rs14100_write()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
rs14100.c:533rs14100_write()
buf_set_u32(reg_params[2].value, 0, 32, flash_offset);
rs14100.c:534rs14100_write()
buf_set_u32(reg_params[3].value, 0, 32, count);
rs14100.c:535rs14100_write()
buf_set_u32(reg_params[4].value, 0, 32, QSPI_BASE);
rs14100.c:536rs14100_write()
buf_set_u32(reg_params[5].value, 0, 32, check_sum);
rsl10.c:367rsl10_ll_flash_erase()
buf_set_u32(reg_params[0].value, 0, 32, address);
rsl10.c:372rsl10_ll_flash_erase()
buf_set_u32(reg_params[1].value, 0, 32, cmd);
rsl10.c:373rsl10_ll_flash_erase()
buf_set_u32(reg_params[2].value, 0, 32, ALGO_STACK_POINTER_ADDR);
rsl10.c:441rsl10_ll_flash_write()
buf_set_u32(reg_params[4].value, 0, 32, ALGO_STACK_POINTER_ADDR);
rsl10.c:467rsl10_ll_flash_write()
buf_set_u32(reg_params[0].value, 0, 32, write_address);
rsl10.c:468rsl10_ll_flash_write()
buf_set_u32(reg_params[1].value, 0, 32, bytes_to_send / 4);
rsl10.c:469rsl10_ll_flash_write()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
rsl10.c:470rsl10_ll_flash_write()
buf_set_u32(reg_params[3].value, 0, 32, cmd);
rsl10.c:529rsl10_mass_erase()
buf_set_u32(reg_params[1].value, 0, 32, cmd);
rsl10.c:530rsl10_mass_erase()
buf_set_u32(reg_params[2].value, 0, 32, ALGO_STACK_POINTER_ADDR);
sh_qspi.c:560sh_qspi_write()
buf_set_u32(reg_params[0].value, 0, 32, io_base);
sh_qspi.c:561sh_qspi_write()
buf_set_u32(reg_params[1].value, 0, 32, src_base);
sh_qspi.c:562sh_qspi_write()
buf_set_u32(reg_params[2].value, 0, 32,
sh_qspi.c:565sh_qspi_write()
buf_set_u32(reg_params[3].value, 0, 32, offset);
sh_qspi.c:628sh_qspi_read()
buf_set_u32(reg_params[0].value, 0, 32, io_base);
sh_qspi.c:629sh_qspi_read()
buf_set_u32(reg_params[1].value, 0, 32, src_base);
sh_qspi.c:630sh_qspi_read()
buf_set_u32(reg_params[2].value, 0, 32,
sh_qspi.c:633sh_qspi_read()
buf_set_u32(reg_params[3].value, 0, 32, offset);
sim3x.c:435sim3x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, FLASHCTRL0_CONFIG_ALL);
sim3x.c:436sim3x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, count);
sim3x.c:437sim3x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
sim3x.c:438sim3x_write_block()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
sim3x.c:439sim3x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, address);
smp.c:61gdb_read_smp_packet()
buf_set_u32(buffer, 0, len * 8, target->gdb_service->core[0]);
stellaris.c:1075stellaris_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
stellaris.c:1076stellaris_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
stellaris.c:1077stellaris_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
stellaris.c:1078stellaris_write_block()
buf_set_u32(reg_params[3].value, 0, 32, wcount);
stlink_usb.c:1211stlink_usb_set_cbw_transfer_datalength()
buf_set_u32(h->cmdbuf+8, 0, 32, size);
stlink_usb.c:1222stlink_usb_xfer_v1_create_cmd()
buf_set_u32(h->cmdbuf+h->cmdidx, 0, 32, 0);
stlink_usb.c:1225stlink_usb_xfer_v1_create_cmd()
buf_set_u32(h->cmdbuf+h->cmdidx, 0, 32, size);
stm32f1x.c:503stm32x_write_block_async()
buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
stm32f1x.c:504stm32x_write_block_async()
buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
stm32f1x.c:505stm32x_write_block_async()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
stm32f1x.c:506stm32x_write_block_async()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
stm32f1x.c:507stm32x_write_block_async()
buf_set_u32(reg_params[4].value, 0, 32, address);
stm32f1x.c:603stm32x_write_block_riscv()
buf_set_u32(reg_params[0].value, 0, 32, stm32x_get_flash_reg(bank, STM32_FLASH_SR));
stm32f1x.c:604stm32x_write_block_riscv()
buf_set_u32(reg_params[1].value, 0, 32, thisrun_hwords);
stm32f1x.c:605stm32x_write_block_riscv()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
stm32f1x.c:606stm32x_write_block_riscv()
buf_set_u32(reg_params[3].value, 0, 32, address);
stm32f2x.c:752stm32x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
stm32f2x.c:753stm32x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
stm32f2x.c:754stm32x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
stm32f2x.c:755stm32x_write_block()
buf_set_u32(reg_params[3].value, 0, 32, count);
stm32f2x.c:756stm32x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
stm32g0x.c:514stm32x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
stm32g0x.c:515stm32x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, count);
stm32g0x.c:516stm32x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, source->address);
stm32g0x.c:517stm32x_write_block()
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
stm32g0x.c:518stm32x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, address);
stm32g4x.c:709stm32l4_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
stm32g4x.c:710stm32l4_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
stm32g4x.c:711stm32l4_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
stm32g4x.c:712stm32l4_write_block()
buf_set_u32(reg_params[3].value, 0, 32, count / 4);
stm32g4x.c:713stm32l4_write_block()
buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->flash_regs_base);
stm32h7x.c:616stm32x_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
stm32h7x.c:617stm32x_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
stm32h7x.c:618stm32x_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
stm32h7x.c:619stm32x_write_block()
buf_set_u32(reg_params[3].value, 0, 32, count);
stm32h7x.c:620stm32x_write_block()
buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
stm32h7x.c:621stm32x_write_block()
buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
stm32l4x.c:1496stm32l4_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
stm32l4x.c:1497stm32l4_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
stm32l4x.c:1498stm32l4_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
stm32l4x.c:1499stm32l4_write_block()
buf_set_u32(reg_params[3].value, 0, 32, count);
stm32l4x.c:1503stm32l4_write_block()
buf_set_u32(reg_params[4].value, 0, 32, source->address +
stm32l5x.c:603stm32l4_write_block()
buf_set_u32(reg_params[0].value, 0, 32, source->address);
stm32l5x.c:604stm32l4_write_block()
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
stm32l5x.c:605stm32l4_write_block()
buf_set_u32(reg_params[2].value, 0, 32, address);
stm32l5x.c:606stm32l4_write_block()
buf_set_u32(reg_params[3].value, 0, 32, count / 4);
stm32l5x.c:607stm32l4_write_block()
buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_BASE));
stm32lx.c:524stm32lx_write_half_pages()
buf_set_u32(reg_params[0].value, 0, 32, address);
stm32lx.c:526stm32lx_write_half_pages()
buf_set_u32(reg_params[1].value, 0, 32, source->address);
stm32lx.c:528stm32lx_write_half_pages()
buf_set_u32(reg_params[2].value, 0, 32, this_count / hp_nb);
stm32lx.c:530stm32lx_write_half_pages()
buf_set_u32(reg_params[3].value, 0, 32, hp_nb);
stm32lx.c:532stm32lx_write_half_pages()
buf_set_u32(reg_params[4].value, 0, 32, stm32lx_info->flash_base);
stm8.c:564stm8_set_core_reg()
buf_set_u32(reg->value, 0, 32, value);
stm8.c:1012stm8_resume()
buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value,
stm8.c:1135stm8_read_core_reg()
buf_set_u32(stm8->core_cache->reg_list[num].value, 0, 32, reg_value);
stm8.c:1312stm8_step()
buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32, address);
stm8.c:1746stm8_blank_check_memory()
buf_set_u32(mem_params[0].value, 0, 24, blocks[0].address);
stm8.c:1749stm8_blank_check_memory()
buf_set_u32(mem_params[1].value, 0, 24, blocks[0].size);
stm8.c:1752stm8_blank_check_memory()
buf_set_u32(reg_params[0].value, 0, 32, erased_value);
stm8.c:1755stm8_blank_check_memory()
buf_set_u32(reg_params[1].value, 0, 32, erase_check_algorithm->address);
stm8.c:1913stm8_run_algorithm()
buf_set_u32(reg_params[i].value,
stm8.c:1925stm8_run_algorithm()
buf_set_u32(stm8->core_cache->reg_list[i].value,
stmqspi.c:1187stmqspi_blank_check()
buf_set_u32(reg_params[0].value, 0, 32, count);
stmqspi.c:1188stmqspi_blank_check()
buf_set_u32(reg_params[1].value, 0, 32, stmqspi_info->io_base);
stmqspi.c:1325qspi_verify()
buf_set_u32(reg_params[0].value, 0, 32, count);
stmqspi.c:1326qspi_verify()
buf_set_u32(reg_params[1].value, 0, 32, pagesize);
stmqspi.c:1327qspi_verify()
buf_set_u32(reg_params[2].value, 0, 32, offset);
stmqspi.c:1328qspi_verify()
buf_set_u32(reg_params[3].value, 0, 32, stmqspi_info->io_base);
stmqspi.c:1510qspi_read_write_block()
buf_set_u32(reg_params[0].value, 0, 32, count);
stmqspi.c:1511qspi_read_write_block()
buf_set_u32(reg_params[1].value, 0, 32, pagesize);
stmqspi.c:1512qspi_read_write_block()
buf_set_u32(reg_params[2].value, 0, 32, offset);
stmqspi.c:1513qspi_read_write_block()
buf_set_u32(reg_params[3].value, 0, 32, io_base);
stmqspi.c:1514