OpenOCD
reg::arch_info is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDreg::arch_info

reg::arch_info field

Syntax

void *arch_info;

References

LocationReferrerText
register.h:140
void *arch_info;
arc.c:223arc_get_register()
struct arc_reg_desc *desc = reg->arch_info;
arc.c:268arc_set_register()
struct arc_reg_desc *desc = reg->arch_info;
arc.c:317arc_init_reg()
reg->arch_info = reg_desc;
arc.c:880arc_save_context()
struct arc_reg_desc *arc_reg = reg->arch_info;
arc.c:887arc_save_context()
struct arc_reg_desc *arc_reg = reg->arch_info;
arc.c:914arc_save_context()
struct arc_reg_desc *arc_reg = reg->arch_info;
arc.c:929arc_save_context()
struct arc_reg_desc *arc_reg = reg->arch_info;
arc.c:1202arc_restore_context()
struct arc_reg_desc *arc_reg = reg->arch_info;
arc.c:1213arc_restore_context()
struct arc_reg_desc *arc_reg = reg->arch_info;
arm7_9_common.c:1539arm7_9_restore_context()
reg_arch_info = reg->arch_info;
arm7_9_common.c:1595arm7_9_restore_context()
reg_arch_info = reg->arch_info;
arm7_9_common.c:1995arm7_9_read_core_reg()
struct arm_reg *areg = r->arch_info;
arm7_9_common.c:2050arm7_9_write_core_reg()
struct arm_reg *areg = r->arch_info;
arm7_9_common.c:2543arm7_9_dcc_completion()
arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
arm_dpm.c:555arm_dpm_write_dirty_registers()
r = cache->reg_list[i].arch_info;
arm_dpm.c:803arm_dpm_full_context()
r = cache->reg_list[i].arch_info;
armv4_5.c:577armv4_5_get_core_reg()
struct arm_reg *reg_arch_info = reg->arch_info;
armv4_5.c:597armv4_5_set_core_reg()
struct arm_reg *reg_arch_info = reg->arch_info;
armv4_5.c:692arm_build_reg_cache()
reg_list[i].arch_info = &reg_arch_info[i];
armv4_5.c:738arm_build_reg_cache()
reg_list[i].arch_info = &reg_arch_info[i];
armv4_5.c:775arm_free_reg_cache()
free(cache->reg_list[0].arch_info);
armv7m.c:219armv7m_get_core_reg()
struct arm_reg *armv7m_reg = reg->arch_info;
armv7m.c:233armv7m_set_core_reg()
struct arm_reg *armv7m_reg = reg->arch_info;
armv7m.c:352armv7m_read_core_reg()
struct arm_reg *armv7m_core_reg = r->arch_info;
armv7m.c:424armv7m_write_core_reg()
struct arm_reg *armv7m_core_reg = r->arch_info;
armv7m.c:795armv7m_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
armv7m.c:846armv7m_free_reg_cache()
free(cache->reg_list[0].arch_info);
armv8.c:1680armv8_get_core_reg()
struct arm_reg *armv8_reg = reg->arch_info;
armv8.c:1692armv8_set_core_reg()
struct arm_reg *armv8_reg = reg->arch_info;
armv8.c:1727armv8_get_core_reg32()
struct arm_reg *armv8_reg = reg->arch_info;
armv8.c:1753armv8_set_core_reg32()
struct arm_reg *armv8_reg = reg->arch_info;
armv8.c:1818armv8_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
armv8.c:1860armv8_build_reg_cache()
reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];
armv8.c:1911armv8_free_cache()
free(cache->reg_list[0].arch_info);
armv8_dpm.c:797armv8_dpm_read_current_registers()
arm_reg = r->arch_info;
armv8_dpm.c:940armv8_dpm_write_dirty_registers()
r = cache->reg_list[i].arch_info;
armv8_dpm.c:1056armv8_dpm_full_context()
r = cache->reg_list[i].arch_info;
avr32_ap7k.c:130avr32_get_core_reg()
struct avr32_core_reg *avr32_reg = reg->arch_info;
avr32_ap7k.c:143avr32_set_core_reg()
struct avr32_core_reg *avr32_reg = reg->arch_info;
avr32_ap7k.c:191avr32_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
cortex_m.c:2525cortex_m_dwt_get_reg()
struct dwt_reg_state *state = reg->arch_info;
cortex_m.c:2538cortex_m_dwt_set_reg()
struct dwt_reg_state *state = reg->arch_info;
cortex_m.c:2601cortex_m_dwt_addreg()
r->arch_info = state;
cortex_m.c:2692cortex_m_dwt_free()
free(cache->reg_list[i].arch_info);
dsp563xx.c:400dsp563xx_get_core_reg()
struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
dsp563xx.c:416dsp563xx_set_core_reg()
struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
dsp563xx.c:469dsp563xx_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
dsp563xx.c:606dsp563xx_reg_ssh_read()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
dsp563xx.c:666dsp563xx_reg_ssh_write()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
dsp563xx.c:708dsp563xx_reg_ssl_read()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info;
dsp563xx.c:741dsp563xx_read_register()
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
dsp563xx.c:791dsp563xx_write_register()
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
dsp563xx.c:873dsp563xx_invalidate_x_context()
arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
dsp563xx.c:963dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info;
dsp563xx.c:995dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info;
dsp563xx.c:1003dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
dsp563xx.c:1011dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
dsp563xx.c:1019dsp563xx_debug_init()
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
embeddedice.c:200embeddedice_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
embeddedice.c:306embeddedice_free_reg_cache()
free(reg_cache->reg_list[0].arch_info);
embeddedice.c:345embeddedice_read_reg_w_check()
struct embeddedice_reg *ice_reg = reg->arch_info;
embeddedice.c:503embeddedice_write_reg()
struct embeddedice_reg *ice_reg = reg->arch_info;
esirisc.c:288esirisc_save_context()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:305esirisc_restore_context()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1299esirisc_read_reg()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1322esirisc_write_reg()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1344esirisc_read_csr()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1367esirisc_write_csr()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1389esirisc_get_reg()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1403esirisc_set_reg()
struct esirisc_reg *reg_info = reg->arch_info;
esirisc.c:1460esirisc_build_reg_cache()
reg->arch_info = reg_info;
esirisc.c:1481esirisc_build_reg_cache()
reg->arch_info = reg_info;
esirisc.c:1498esirisc_free_reg_cache()
free(reg->arch_info);
esirisc.c:1506esirisc_free_reg_cache()
free(reg->arch_info);
etb.c:138etb_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
etb.c:205etb_read_reg_w_check()
struct etb_reg *etb_reg = reg->arch_info;
etb.c:286etb_write_reg()
struct etb_reg *etb_reg = reg->arch_info;
etm.c:229etm_reg_lookup()
struct etm_reg *reg = cache->reg_list[i].arch_info;
etm.c:267etm_reg_add()
reg->arch_info = ereg;
etm.c:489etm_read_reg_w_check()
struct etm_reg *etm_reg = reg->arch_info;
etm.c:577etm_write_reg()
struct etm_reg *etm_reg = reg->arch_info;
lakemont.c:331lakemont_get_core_reg()
struct lakemont_core_reg *lakemont_reg = reg->arch_info;
lakemont.c:342lakemont_set_core_reg()
struct lakemont_core_reg *lakemont_reg = reg->arch_info;
lakemont.c:400lakemont_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
lakemont.c:514halt_prep()
x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
lakemont.c:515halt_prep()
if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
lakemont.c:518halt_prep()
x86_32->pm_regs[I(EFLAGS)],
lakemont.c:519halt_prep()
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
lakemont.c:520halt_prep()
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
lakemont.c:525halt_prep()
x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
lakemont.c:526halt_prep()
if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
lakemont.c:528halt_prep()
LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
lakemont.c:531halt_prep()
x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;
lakemont.c:532halt_prep()
if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
lakemont.c:534halt_prep()
LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
lakemont.c:541halt_prep()
x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
lakemont.c:542halt_prep()
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
lakemont.c:544halt_prep()
LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:548halt_prep()
x86_32->pm_regs[I(CR0)] =
lakemont.c:549halt_prep()
x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
lakemont.c:550halt_prep()
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
lakemont.c:552halt_prep()
LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:640read_hw_reg()
arch_info = x86_32->cache->reg_list[reg].arch_info;
lakemont.c:674write_hw_reg()
arch_info = x86_32->cache->reg_list[reg].arch_info;
lakemont.c:710is_paging_enabled()
if (x86_32->pm_regs[I(CR0)] & CR0_PG)
lakemont.c:725disable_paging()
x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;
lakemont.c:726disable_paging()
int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
lakemont.c:737enable_paging()
x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);
lakemont.c:738enable_paging()
int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
mips32.c:228mips32_get_core_reg()
struct mips32_core_reg *mips32_reg = reg->arch_info;
mips32.c:242mips32_set_core_reg()
struct mips32_core_reg *mips32_reg = reg->arch_info;
mips32.c:509mips32_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
mips64.c:228mips64_get_core_reg()
struct mips64_core_reg *mips64_reg = reg->arch_info;
mips64.c:242mips64_set_core_reg()
struct mips64_core_reg *mips64_reg = reg->arch_info;
mips64.c:406mips64_build_reg_cache()
r->arch_info = &arch_info[i];
or1k.c:453or1k_get_core_reg()
struct or1k_core_reg *or1k_reg = reg->arch_info;
or1k.c:466or1k_set_core_reg()
struct or1k_core_reg *or1k_reg = reg->arch_info;
or1k.c:536or1k_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
riscv-013.c:880access_register_command()
riscv_reg_info_t *reg_info = target->reg_cache->reg_list[number].arch_info;
riscv.c:477riscv_free_registers()
free(target->reg_cache->reg_list[0].arch_info);
riscv.c:480riscv_free_registers()
free(target->reg_cache->reg_list[i].arch_info);
riscv.c:3699register_get()
riscv_reg_info_t *reg_info = reg->arch_info;
riscv.c:3729register_set()
riscv_reg_info_t *reg_info = reg->arch_info;
riscv.c:3981riscv_init_registers()
r->arch_info = shared_reg_info;
riscv.c:4383riscv_init_registers()
r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
riscv.c:4384riscv_init_registers()
if (!r->arch_info)
riscv.c:4386riscv_init_registers()
((riscv_reg_info_t *) r->arch_info)->target = target;
riscv.c:4387riscv_init_registers()
((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
stm8.c:543stm8_get_core_reg()
struct stm8_core_reg *stm8_reg = reg->arch_info;
stm8.c:557stm8_set_core_reg()
struct stm8_core_reg *stm8_reg = reg->arch_info;
stm8.c:1219stm8_build_reg_cache()
reg_list[i].arch_info = &arch_info[i];
stm8.c:1266stm8_free_reg_cache()
free(cache->reg_list[0].arch_info);
xscale.c:2389xscale_get_reg()
struct xscale_reg *arch_info = reg->arch_info;
xscale.c:2425xscale_set_reg()
struct xscale_reg *arch_info = reg->arch_info;
xscale.c:2462xscale_write_dcsr_sw()
struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
xscale.c:2885xscale_build_reg_cache()
(*cache_p)->reg_list[i].arch_info = &arch_info[i];
xscale.c:2903xscale_free_reg_cache()
free(cache->reg_list[0].arch_info);
xtensa.c:434xtensa_core_reg_get()
struct xtensa *xtensa = (struct xtensa *)reg->arch_info;
xtensa.c:452xtensa_core_reg_set()
struct xtensa *xtensa = (struct xtensa *)reg->arch_info;
xtensa.c:2976xtensa_build_reg_cache()
reg_list[didx].arch_info = xtensa;
xtensa.c:3020xtensa_build_reg_cache()
xtensa->empty_regs[i].arch_info = xtensa;

Data Use

Functions writing reg::arch_info
Functions reading reg::arch_info
all items filtered out
reg::arch_info
all items filtered out