OpenOCD
lakemont_core_reg is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDlakemont_core_reg

lakemont_core_reg struct

Syntax

struct lakemont_core_reg {     uint32_t num;     struct target *target;     struct x86_32_common *x86_32_common;     uint64_t op;     uint8_t pm_idx; };

Fields

num

No summary provided. Read more...

target

No summary provided. Read more...

x86_32_common

No summary provided. Read more...

op

No summary provided. Read more...

pm_idx

No summary provided. Read more...

References

LocationReferrerScopeText
lakemont.h:66
struct lakemont_core_reg {
lakemont.c:331lakemont_get_core_reg()
struct lakemont_core_reg *lakemont_reg = reg->arch_info;
lakemont.c:342lakemont_set_core_reg()
struct lakemont_core_reg *lakemont_reg = reg->arch_info;
lakemont.c:369lakemont_build_reg_cache()
struct lakemont_core_reg *arch_info = malloc(sizeof(struct lakemont_core_reg) * num_regs);
lakemont.c:376lakemont_build_reg_cache()
free(arch_info);
lakemont.c:514halt_prep()
x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
lakemont.c:515halt_prep()
if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
lakemont.c:518halt_prep()
x86_32->pm_regs[I(EFLAGS)],
lakemont.c:519halt_prep()
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
lakemont.c:520halt_prep()
x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
lakemont.c:525halt_prep()
x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
lakemont.c:526halt_prep()
if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
lakemont.c:528halt_prep()
LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
lakemont.c:531halt_prep()
x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;
lakemont.c:532halt_prep()
if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
lakemont.c:534halt_prep()
LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
lakemont.c:541halt_prep()
x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
lakemont.c:542halt_prep()
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
lakemont.c:544halt_prep()
LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:548halt_prep()
x86_32->pm_regs[I(CR0)] =
lakemont.c:549halt_prep()
x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
lakemont.c:550halt_prep()
if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
lakemont.c:552halt_prep()
LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
lakemont.c:639read_hw_reg()
struct lakemont_core_reg *arch_info;
lakemont.c:673write_hw_reg()
struct lakemont_core_reg *arch_info;
lakemont.c:710is_paging_enabled()
if (x86_32->pm_regs[I(CR0)] & CR0_PG)
lakemont.c:725disable_paging()
x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;
lakemont.c:726disable_paging()
int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
lakemont.c:737enable_paging()
x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);
lakemont.c:738enable_paging()
int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);

Type Use

Variables of lakemont_core_reg type
lakemont_get_core_reg()::lakemont_reg
lakemont_set_core_reg()::lakemont_reg
lakemont_build_reg_cache()::arch_info
read_hw_reg()::arch_info
write_hw_reg()::arch_info
all items filtered out
lakemont_core_reg
Allocators of lakemont_core_reg
Deletors of lakemont_core_reg
all items filtered out
lakemont_core_reg
all items filtered out