OpenOCD
flash_bank::base is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDflash_bank::base

flash_bank::base field

The base address of this bank

Syntax

target_addr_t base;

References

LocationReferrerText
core.h:84
target_addr_t base; /**< The base address of this bank */
FLASHPlugin.c:510plugin_write()
report_flash_progress("flash_write_progress_sync", bank->base + offset + done, bank->base + offset + done + doneNow, bank->name);
FLASHPlugin.c:617plugin_probe()
retval = call_plugin_func(target, loaded_plugin.timeouts.init, plugin_info->FLASHPlugin_Probe, sp, &result, 5, sp, (uint32_t)bank->base, (uint32_t)bank->size, (uint32_t)bank->chip_width, (uint32_t)bank->bus_width);
FLASHPlugin.c:639plugin_probe()
bank->base = bankInfo.BaseAddress;
FLASHPlugin.c:703plugin_erase()
report_flash_progress("flash_erase_progress", bank->base + bank->sectors[first].offset, bank->base + bank->sectors[first + result - 1].offset + bank->sectors[first + result - 1].size, bank->name);
aduc702x.c:37aduc702x_flash_bank_command()
bank->base = 0x80000;
aduc702x.c:96aduc702x_erase()
adr = bank->base + ((first + x) * 512);
aduc702x.c:130aduc702x_write_block()
uint32_t address = bank->base + offset;
aducm302x.c:347aducm302x_write_block()
uint32_t address = bank->base + offset;
aducm302x.c:526aducm302x_flash_bank_command()
bank->base = 0x0;
aducm302x.c:553aducm4x50_flash_bank_command()
bank->base = 0x0;
aducm360.c:64aducm360_flash_bank_command()
bank->base = 0x00000000;
aducm360.c:169aducm360_erase()
padd = bank->base + ((first+i)*FLASH_SECTOR_SIZE);
aducm360.c:190aducm360_write_block_sync()
uint32_t address = bank->base + offset;
aducm360.c:310aducm360_write_block_async()
uint32_t address = bank->base + offset;
ambiqmicro.c:195ambiqmicro_read_part_info()
bank->base = bank->bank_number * 0x40000;
ambiqmicro.c:212ambiqmicro_read_part_info()
bank->base = bank->bank_number * 0x40000;
ambiqmicro.c:525ambiqmicro_write_block()
uint32_t address = bank->base + offset;
at91sam3.c:2188flashd_read_uid()
private->bank->base + (x * 4),
at91sam3.c:3013sam3_flash_bank_command()
switch (bank->base) {
at91sam3.c:3018sam3_flash_bank_command()
((unsigned int)(bank->base)),
at91sam3.c:3160_sam3_probe()
if (bank->base == private->chip->details.bank[x].base_address) {
at91sam4.c:1638flashd_read_uid()
private->bank->base + (x * 4),
at91sam4.c:2506sam4_flash_bank_command()
switch (bank->base) {
at91sam4.c:2510sam4_flash_bank_command()
((unsigned int)(bank->base)),
at91sam4.c:2629sam4_info()
bank->base);
at91sam4.c:2666sam4_probe()
if (bank->base == private->chip->details.bank[x].base_address) {
at91sam4.c:2669sam4_probe()
TARGET_ADDR_FMT ", idx %d", bank->base,
at91sam4.c:2670sam4_probe()
bank->base + bank->size, x);
at91sam4l.c:195sam4l_flash_bank_command()
if (bank->base != SAM4L_FLASH) {
at91sam4l.c:199sam4l_flash_bank_command()
bank->base, SAM4L_FLASH);
at91sam4l.c:580sam4l_write()
(offset / chip->page_size) * chip->page_size + bank->base,
at91sam4l.c:599sam4l_write()
bank->base + offset,
at91sam4l.c:606sam4l_write()
bank->base + offset,
at91sam7.c:587at91sam7_read_part_info()
t_bank->base = base_address + bnk * bank_size;
at91sam7.c:775at91sam7_flash_bank_command()
t_bank->base = base_address + bnk * bank_size;
at91sam7.c:949at91sam7_write()
retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4,
at91samd.c:873samd_write()
address = bank->base + offset;
at91samd.c:944samd_flash_bank_command()
if (bank->base != SAMD_FLASH) {
at91samd.c:948samd_flash_bank_command()
bank->base, SAMD_FLASH);
ath79.c:783ath79_probe()
target_device->name, bank->base);
atsame5.c:676same5_write()
address = bank->base + offset;
atsame5.c:736same5_flash_bank_command()
if (bank->base != SAMD_FLASH) {
atsame5.c:738same5_flash_bank_command()
"0x%08x[same5] )", bank->base, SAMD_FLASH);
atsamv.c:341samv_probe()
bank->base = SAMV_FLASH_BASE;
avrf.c:329avrf_probe()
bank->base = 0x00000000;
bluenrg-x.c:159bluenrgx_erase()
address = bank->base;
bluenrg-x.c:166bluenrgx_erase()
(address - bank->base) >> 2) != ERROR_OK) {
bluenrg-x.c:193bluenrgx_erase()
address = bank->base+i*FLASH_PAGE_SIZE(bluenrgx_info);
bluenrg-x.c:202bluenrgx_erase()
(address - bank->base) >> 2) != ERROR_OK) {
bluenrg-x.c:241bluenrgx_write()
uint32_t address = bank->base + offset;
bluenrg-x.c:398bluenrgx_probe()
bank->base = flash_priv_data_1.flash_base;
bluenrg-x.c:403bluenrgx_probe()
bank->base = (*flash_ctrl[i]).flash_base;
cc26xx.c:347cc26xx_write()
address = bank->base + offset;
cc26xx.c:468cc26xx_probe()
bank->base = CC26XX_FLASH_BASE_ADDR;
cc3220sf.c:441cc3220sf_probe()
bank->base = base;
cfi.c:109cfi_flash_address()
return bank->base + offset * bank->bus_width;
cfi.c:115cfi_flash_address()
return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
cfi.c:868cfi_intel_erase()
TARGET_ADDR_FMT, i, bank->base);
cfi.c:923cfi_spansion_erase()
TARGET_ADDR_FMT, i, bank->base);
cfi.c:1981cfi_intel_write_word()
bank->base, address);
cfi.c:2006cfi_intel_write_words()
bank->base, address, cfi_info->max_buf_write_size);
cfi.c:2036cfi_intel_write_words()
bank->base,
cfi.c:2065cfi_intel_write_words()
", address 0x%" PRIx32 " failed.", bank->base, address);
cfi.c:2096cfi_spansion_write_word()
", address 0x%" PRIx32, bank->base, address);
cfi.c:2121cfi_spansion_write_words()
bank->base, address, cfi_info->max_buf_write_size);
cfi.c:2162cfi_spansion_write_words()
", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
cfi.c:2216cfi_read()
uint32_t address = bank->base + offset;
cfi.c:2284cfi_write()
uint32_t address = bank->base + offset; /* address of first byte to be programmed */
core.c:95flash_driver_write()
bank->base,
core.c:114flash_driver_read()
bank->base,
core.c:124default_flash_read()
return target_read_buffer(bank->target, offset + bank->base, count, buffer);
core.c:136flash_driver_verify()
bank->base, offset);
core.c:152default_flash_verify()
retval = target_checksum_memory(bank->target, offset + bank->base, count, &target_crc);
core.c:157default_flash_verify()
offset + bank->base, count, ~image_crc, ~target_crc);
core.c:320get_flash_bank_by_addr()
if ((addr >= c->base) && (addr <= c->base + (c->size - 1))) {
core.c:358default_flash_mem_blank_check()
bank->base + bank->sectors[i].offset + j,
core.c:396default_flash_blank_check()
block_array[i].address = bank->base + bank->sectors[i].offset;
core.c:473flash_iterate_address_range_inner()
if (addr != c->base) {
core.c:482flash_iterate_address_range_inner()
if (last_addr > c->base + c->size - 1) {
core.c:502flash_iterate_address_range_inner()
target_addr_t sector_addr = c->base + f->offset;
core.c:595flash_iterate_address_range()
if (addr + length - 1 > c->base + c->size - 1) {
core.c:597flash_iterate_address_range()
cur_length = c->base + c->size - addr;
core.c:656flash_write_align_start()
if (addr < bank->base || addr >= bank->base + bank->size
core.c:661flash_write_align_start()
uint32_t offset = addr - bank->base;
core.c:669flash_write_align_start()
return bank->base + aligned;
core.c:680flash_write_align_end()
if (addr < bank->base || addr >= bank->base + bank->size
core.c:685flash_write_align_end()
uint32_t offset = addr - bank->base;
core.c:692flash_write_align_end()
return bank->base + aligned;
core.c:705flash_write_check_gap()
|| addr1 < bank->base || addr1 >= bank->base + bank->size
core.c:706flash_write_check_gap()
|| addr2 < bank->base || addr2 >= bank->base + bank->size)
core.c:711flash_write_check_gap()
uint32_t offset1 = addr1 - bank->base;
core.c:720flash_write_check_gap()
uint32_t offset2 = addr2 - bank->base;
core.c:810flash_write_unlock_verify()
while ((run_address + run_size - 1 < c->base + c->size - 1) &&
core.c:814flash_write_unlock_verify()
if (sections[section_last + 1]->base_address >= (c->base + c->size)) {
core.c:852flash_write_unlock_verify()
if (run_address + run_size - 1 > c->base + c->size - 1) {
core.c:858flash_write_unlock_verify()
run_size = c->base + c->size - run_address;
core.c:894flash_write_unlock_verify()
uint32_t offset_start = run_address - c->base;
core.c:980flash_write_unlock_verify()
retval = flash_driver_write(c, buffer, run_address - c->base, run_size);
core.c:987flash_write_unlock_verify()
retval = flash_driver_verify(c, buffer, run_address - c->base, run_size);
dsp5680xx_flash.c:53dsp5680xx_flash_bank_command()
bank->base = HFM_FLASH_BASE_ADDR;
dsp5680xx_flash.c:152dsp5680xx_flash_write()
return dsp5680xx_f_wr(bank->target, buffer, bank->base + offset / 2, count, 0);
efm32.c:340efm32x_flash_bank_command()
int bank_index = efm32x_get_bank_index(bank->base);
efm32.c:343efm32x_flash_bank_command()
(uint32_t) bank->base);
efm32.c:518efm32x_erase()
ret = efm32x_erase_page(bank, bank->base + bank->sectors[i].offset);
efm32.c:528efm32x_erase()
if (bank->base == EFM32_MSC_LOCK_BITS) {
efm32.c:664efm32x_get_page_lock()
switch (bank->base) {
efm32.c:686efm32x_set_page_lock()
if (bank->base != EFM32_FLASH_BASE) {
efm32.c:1041efm32x_write()
if (bank->base == EFM32_MSC_LOCK_BITS && offset < LOCKWORDS_SZ) {
efm32.c:1045efm32x_write()
return efm32x_priv_write(bank, buffer, bank->base + offset, count);
efm32.c:1054efm32x_probe()
int bank_index = efm32x_get_bank_index(bank->base);
efm32.c:1074efm32x_probe()
if (bank->base == EFM32_FLASH_BASE) {
efm32.c:1105efm32x_auto_probe()
int bank_index = efm32x_get_bank_index(bank->base);
em357.c:364em357_erase()
bank->base + bank->sectors[i].offset);
em357.c:451em357_write_block()
uint32_t address = bank->base + offset;
em357.c:577em357_write()
uint32_t address = bank->base + offset;
em357.c:716em357_probe()
bank->base = base_address;
eneispif.c:344eneispif_probe()
bank->base, eneispif_info->ctrl_base);
fespi.c:751fespi_probe()
target_device->name, bank->base);
fespi.c:756fespi_probe()
bank->base);
fm3.c:345fm3_write_block()
uint32_t address = bank->base + offset;
fm3.c:651fm3_probe()
bank->base = 0x00000000;
fm4.c:152fm4_flash_erase()
uint32_t addr = bank->base + bank->sectors[sector].offset;
fm4.c:274fm4_flash_write()
uint32_t addr = bank->base + offset;
fm4.c:350mb9bf_probe()
uint32_t flash_addr = bank->base;
fm4.c:382mb9bf_probe()
bank->sectors[i].offset = flash_addr - bank->base;
fm4.c:411s6e2cc_probe()
uint32_t flash_addr = bank->base;
fm4.c:444s6e2cc_probe()
bank->sectors[i].offset = flash_addr - bank->base;
fm4.c:454s6e2cc_probe()
bank->sectors[i].offset = flash_addr - bank->base;
fm4.c:469s6e2dh_probe()
uint32_t flash_addr = bank->base;
fm4.c:481s6e2dh_probe()
bank->sectors[i].offset = flash_addr - bank->base;
fm4.c:671fm4_flash_bank_command()
fm4_bank->macro_nr = (bank->base == 0x00000000) ? 0 : 1;
gdb_server.c:1915compare_bank()
if (b1->base == b2->base)
gdb_server.c:1917compare_bank()
else if (b1->base > b2->base)
gdb_server.c:2010gdb_memory_map()
target_addr_t extended_base = extend_address_for_gdb(target, p->base);
kinetis.c:1829kinetis_write_sections()
bank->base + offset, align_begin, align_end);
kinetis.c:1836kinetis_write_sections()
bank->base + offset, size);
kinetis.c:1851kinetis_write_sections()
bank->base + offset);
kinetis.c:1857kinetis_write_sections()
bank->base + offset);
kinetis.c:1899kinetis_write_inner()
LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
kinetis.c:1945kinetis_write_inner()
LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
kinetis.c:1953kinetis_write_inner()
bank->base + offset);
kinetis.c:1959kinetis_write_inner()
bank->base + offset);
kinetis.c:2068kinetis_write()
result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
kinetis.c:2927kinetis_probe()
bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
kinetis.c:2948kinetis_probe()
bank->base = k_chip->nvm_base + bank->size * nvm_ord;
kinetis.c:3065kinetis_info()
bank->name, bank->base);
kinetis_ke.c:696kinetis_ke_write_words()
uint32_t address = bank->base + offset;
kinetis_ke.c:961kinetis_ke_erase()
FCCOBLO[0] = (bank->base + bank->sectors[i].offset) >> 16;
kinetis_ke.c:964kinetis_ke_erase()
FCCOBHI[1] = (bank->base + bank->sectors[i].offset) >> 8;
kinetis_ke.c:965kinetis_ke_erase()
FCCOBLO[1] = (bank->base + bank->sectors[i].offset);
kinetis_ke.c:1076kinetis_ke_probe()
bank->base = 0x00000000;
kinetis_ke.c:1146kinetis_ke_info()
bank->driver->name, bank->name, bank->base);
kinetis_ke.c:1180kinetis_ke_blank_check()
FCCOBLO[0] = (bank->base + bank->sectors[i].offset) >> 16;
kinetis_ke.c:1183kinetis_ke_blank_check()
FCCOBHI[1] = (bank->base + bank->sectors[i].offset) >> 8;
kinetis_ke.c:1184kinetis_ke_blank_check()
FCCOBLO[1] = (bank->base + bank->sectors[i].offset);
lpc2000.c:1181lpc2000_write()
thisrun_bytes, bank->base + offset + bytes_written);
lpc2000.c:1184lpc2000_write()
param_table[0] = bank->base + offset + bytes_written;
lpc288x.c:137lpc288x_read_part_info()
offset = bank->base;
lpc2900.c:260lpc2900_read_security_status()
target_read_memory(target, bank->base + 0xC00, 4, 0x230/4,
lpc2900.c:351lpc2900_address2sector()
uint32_t address = bank->base + offset;
lpc2900.c:395lpc2900_write_index_page()
target_write_u32(target, bank->base, 0);
lpc2900.c:406lpc2900_write_index_page()
bank->base + pagenum * FLASH_PAGE_SIZE,
lpc2900.c:488lpc2900_handle_signature_command()
status = lpc2900_run_bist128(bank, bank->base, bank->base + (bank->size - 1), signature);
lpc2900.c:534lpc2900_handle_read_custom_command()
target_read_memory(target, bank->base+ISS_CUSTOMER_START1, 4,
lpc2900.c:537lpc2900_handle_read_custom_command()
target_read_memory(target, bank->base+ISS_CUSTOMER_START2, 4,
lpc2900.c:1107lpc2900_write()
if (((bank->base + offset) <
lpc2900.c:1109lpc2900_write()
((bank->base + (offset + count - 1)) >= bank->sectors[sector].offset)) {
lpc2900.c:1206lpc2900_write()
if ((bank->sectors[sector].offset - bank->base) <
lpc2900.c:1211lpc2900_write()
bank->base - offset)
lpc2900.c:1309lpc2900_write()
bank->base + (offset - (offset % FLASH_PAGE_SIZE)),
lpc2900.c:1394lpc2900_probe()
bank->base = 0x20000000;
max32xxx.c:358max32xxx_write_block()
uint32_t address = bank->base + offset;
mdr.c:211mdr_write_block()
uint32_t address = bank->base + offset;
mdr.c:455mdr_write()
target_checksum_memory(bank->target, bank->base, 64, &tmp);
msp432.c:593msp432_flash_bank_command()
bank->base = FLASH_BASE;
msp432.c:605msp432_erase()
bool is_main = bank->base == FLASH_BASE;
msp432.c:606msp432_erase()
bool is_info = bank->base == P4_FLASH_INFO_BASE;
msp432.c:649msp432_erase()
buf_set_u32(algo_params.address, 0, 32, bank->base +
msp432.c:684msp432_write()
bool is_info = bank->base == P4_FLASH_INFO_BASE;
msp432.c:738msp432_write()
buf_set_u32(algo_params.address, 0, 32, bank->base + offset);
msp432.c:820msp432_probe()
bool is_main = bank->base == FLASH_BASE;
msp432.c:821msp432_probe()
bool is_info = bank->base == P4_FLASH_INFO_BASE;
msp432.c:954msp432_probe()
info->base = P4_FLASH_INFO_BASE;
msp432.c:968msp432_auto_probe()
bool is_main = bank->base == FLASH_BASE;
msp432.c:969msp432_auto_probe()
bool is_info = bank->base == P4_FLASH_INFO_BASE;
msp432.c:1038msp432_flash_free_driver_priv()
bool is_main = bank->base == FLASH_BASE;
msp432p4.c:129msp432p4_flash_bank_command()
msp432p4_info->register_base = bank->base;
msp432p4.c:545msp432p4_probe()
bank->base = base_address;
niietcm4.c:1273niietcm4_write_block()
uint32_t address = bank->base + offset;
niietcm4.c:1576niietcm4_probe_k1921vk01t()
TARGET_ADDR_FMT " base address", bank->base);
nrf5.c:849nrf5_probe_chip()
switch (bank->base) {
nrf5.c:1002nrf5_setup_bank()
if (bank->base == chip->map->flash_base) {
nrf5.c:1019nrf5_setup_bank()
} else if (bank->base == chip->map->uicr_base) {
nrf5.c:1032nrf5_setup_bank()
LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base);
nrf5.c:1072nrf5_erase_page()
if (bank->base == chip->map->uicr_base) {
nrf5.c:1097nrf5_erase_page()
res = target_write_u32(chip->target, bank->base + sector->offset, 0xffffffff);
nrf5.c:1271nrf5_write()
res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
nrf5.c:1379nrf5_flash_bank_command()
switch (bank->base) {
nrf5.c:1387nrf5_flash_bank_command()
LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base);
nrf5.c:1401nrf5_flash_bank_command()
switch (bank->base) {
numicro.c:699numicro_writeblock()
uint32_t address = bank->base + offset;
numicro.c:879numicro_erase()
LOG_DEBUG("erasing sector %u at address " TARGET_ADDR_FMT, i, bank->base + bank->sectors[i].offset);
numicro.c:882numicro_erase()
bank->base + bank->sectors[i].offset);
numicro.c:971numicro_write()
bank->base + offset + i);
numicro.c:1056numicro_get_flash_size()
if (bank->base == cpu->bank[i].base) {
numicro.c:1059numicro_get_flash_size()
PRIx32, bank->base, *flash_size);
ocl.c:231ocl_probe()
bank->base = dcc_buffer[0];
pic32mm.c:143pic32mm_is_boot_bank()
return Virt2Phys(bank->base) == PIC32MM_PHYS_BOOT_FLASH;
pic32mm.c:369pic32mm_invalidate_flash_line_buffer()
int res = target_read_memory(bank->target, bank->base, 4, 1, tmp);
pic32mm.c:374pic32mm_invalidate_flash_line_buffer()
res = target_read_memory(bank->target, bank->base + pic32mm_info->layout.page_size_in_words * PIC32MM_FLASH_WORD_SIZE_IN_BYTES, 4, 1, tmp);
pic32mm.c:395pic32mm_erase()
&& (Virt2Phys(bank->base) == PIC32MM_PHYS_PGM_FLASH)) {
pic32mm.c:408pic32mm_erase()
target_write_u32(target, PIC32MM_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
pic32mm.c:575pic32mm_write_using_loader()
uint32_t address = bank->base + offset;
pic32mm.c:761pic32mm_write()
int retval = pic32mm_write_dword(bank, bank->base + row_offset, pair.u32[0], pair.u32[1]);
pic32mm.c:958pic32mm_handle_pgm_word_command()
if (address < bank->base || address >= (bank->base + bank->size)) {
pic32mm.c:970pic32mm_handle_pgm_word_command()
unsigned sector = (address - bank->base) / (pic32mm_info->layout.page_size_in_words * PIC32MM_FLASH_WORD_SIZE_IN_BYTES);
pic32mm.c:1069pic32mm_verify()
int retval = target_read_memory(bank->target, bank->base + aligned_offset, 4, (count + offset - aligned_offset + 3) / 4, tmp);
pic32mm.c:1083pic32mm_verify()
uint32_t address = (uint32_t)(bank->base + offset + i);
pic32mx.c:284pic32mx_protect_check()
else if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
pic32mx.c:324pic32mx_erase()
&& (virt2phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
pic32mx.c:337pic32mx_erase()
target_write_u32(target, PIC32MX_NVMADDR, virt2phys(bank->base + bank->sectors[i].offset));
pic32mx.c:439pic32mx_write_block()
uint32_t address = bank->base + offset;
pic32mx.c:600pic32mx_write()
uint32_t address = bank->base + offset;
pic32mx.c:611pic32mx_write()
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
pic32mx.c:723pic32mx_probe()
if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
pic32mx.c:842pic32mx_handle_pgm_word_command()
if (address < bank->base || address >= (bank->base + bank->size)) {
psoc4.c:809psoc4_probe()
bank->base = 0x00000000;
psoc5lp.c:774psoc5lp_nvl_probe()
bank->base = NVL_META_BASE;
psoc5lp.c:925psoc5lp_eeprom_probe()
uint32_t flash_addr = bank->base;
psoc5lp.c:957psoc5lp_eeprom_probe()
bank->sectors[i].offset = flash_addr - bank->base;
psoc5lp.c:1077psoc5lp_erase_check()
block_array[i].address = bank->base + bank->sectors[i].offset;
psoc5lp.c:1375psoc5lp_probe()
uint32_t flash_addr = bank->base;
psoc5lp.c:1410psoc5lp_probe()
bank->sectors[i].offset = flash_addr - bank->base;
psoc5lp.c:1419psoc5lp_probe()
bank->sectors[i].offset = flash_addr - bank->base;
psoc6.c:517is_sflash_bank()
if (bank->base == safe_sflash_regions[i].addr)
psoc6.c:531is_wflash_bank()
return (bank->base == MEM_BASE_WFLASH);
psoc6.c:541is_mflash_bank()
return (bank->base == MEM_BASE_MFLASH);
psoc6.c:581psoc6_probe()
if (safe_sflash_regions[i].addr == bank->base) {
psoc6.c:730psoc6_erase()
hr = psoc6_erase_sector(bank, wa, bank->base + first * psoc6_info->row_sz);
psoc6.c:737psoc6_erase()
hr = psoc6_erase_row(bank, wa, bank->base + first * psoc6_info->row_sz);
psoc6.c:835psoc6_program()
uint32_t aligned_addr = bank->base + offset - row_offset;
qn908x.c:359qn908x_flash_bank_command()
if (bank->base != QN908X_FLASH_BASE) {
qn908x.c:362qn908x_flash_bank_command()
bank->base, QN908X_FLASH_BASE);
qn908x.c:404qn908x_read_page_lock()
int retval = target_read_memory(bank->target, bank->base + prot_offset, 4,
qn908x.c:766qn908x_write()
retval = target_write_buffer(bank->target, bank->base,
qn908x.c:772qn908x_write()
retval = target_write_u32(bank->target, bank->base + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_POS, checksum);
qn908x.c:777qn908x_write()
bank->base + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_END,
qn908x.c:781qn908x_write()
retval = target_write_buffer(bank->target, bank->base + offset,
renesas_rpchf.c:449rpchf_spansion_write_words()
bank->base, address, cfi_info->max_buf_write_size);
renesas_rpchf.c:479rpchf_spansion_write_words()
", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
renesas_rpchf.c:496rpchf_write()
uint32_t address = bank->base + offset; /* address of first byte to be programmed */
rp2040.c:481rp2040_flash_probe()
bank->size, bank->base, bank->num_sectors);
rs14100.c:319rs14100_probe()
bank->base = base_address;
rsl10.c:169rsl10_protect_check()
if (bank->base == RSL10_FLASH_ADDRESS_MAIN) {
rsl10.c:175rsl10_protect_check()
switch (bank->base) {
rsl10.c:202rsl10_protect()
if (bank->base == RSL10_FLASH_ADDRESS_MAIN) {
rsl10.c:224rsl10_protect()
switch (bank->base) {
rsl10.c:285rsl10_probe()
switch (bank->base) {
rsl10.c:562rsl10_write()
return rsl10_ll_flash_write(chip, bank->base + offset, buffer, count);
rsl10.c:576rsl10_erase()
retval = rsl10_ll_flash_erase(chip, bank->base + i * 0x800);
rsl10.c:624rsl10_flash_bank_command()
LOG_INFO("Creating flash @ " TARGET_ADDR_FMT, bank->base);
rsl10.c:626rsl10_flash_bank_command()
switch (bank->base) {
rsl10.c:634rsl10_flash_bank_command()
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
rsl10.c:647rsl10_flash_bank_command()
switch (bank->base) {
sh_qspi.c:777sh_qspi_probe()
target_device->name, bank->base);
sim3x.c:336sim3x_write_block()
uint32_t address = bank->base + offset;
sim3x.c:796sim3x_probe()
bank->base = FLASH_BASE_ADDRESS;
stellaris.c:457stellaris_flash_bank_command()
bank->base = 0x0;
stellaris.c:1026stellaris_write_block()
uint32_t address = bank->base + offset;
stm32f1x.c:392stm32x_erase()
bank->base + bank->sectors[i].offset);
stm32f1x.c:724stm32x_write()
retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
stm32f1x.c:992stm32x_probe()
if (bank->base != 0x08080000) {
stm32f1x.c:1027stm32x_probe()
bank->base = base_address;
stm32f2x.c:202stm32x_is_otp()
return bank->base == STM32F2_OTP_BANK_BASE ||
stm32f2x.c:203stm32x_is_otp()
bank->base == STM32F7_OTP_BANK_BASE;
stm32f2x.c:208stm32x_otp_is_f7()
return bank->base == STM32F7_OTP_BANK_BASE;
stm32f2x.c:643stm32x_erase()
report_flash_progress("flash_erase_progress", bank->base + bank->sectors[i].offset, bank->base + bank->sectors[i].offset + bank->sectors[i].size, bank->name);
stm32f2x.c:702stm32x_write_block()
uint32_t address = bank->base + offset;
stm32f2x.c:805stm32x_write()
uint32_t address = bank->base + offset;
stm32f2x.c:1184stm32x_probe()
bank->base = base_address;
stm32g0x.c:604stm32gx_write()
retval = stm32x_write_block(bank, buffer, bank->base + offset, dwords_remaining);
stm32g0x.c:615stm32gx_write()
retval = target_write_u64(target, bank->base + offset, value);
stm32g0x.c:782stm32x_probe()
bank->base = base_address;
stm32g4x.c:663stm32l4_write_block()
uint32_t address = bank->base + offset;
stm32g4x.c:880stm32l4_probe()
bank->base = 0x08000000;
stm32h7x.c:567stm32x_write_block()
uint32_t address = bank->base + offset;
stm32h7x.c:666stm32x_write()
uint32_t address = bank->base + offset;
stm32h7x.c:784stm32x_probe()
if (bank->base == FLASH_BANK0_ADDRESS)
stm32h7x.c:786stm32x_probe()
else if (bank->base == FLASH_BANK1_ADDRESS)
stm32h7x.c:839stm32x_probe()
if (bank->base != bank1_base && bank->base != bank2_base) {
stm32h7x.c:842stm32x_probe()
bank->base, bank1_base, bank2_base);
stm32h7x.c:847stm32x_probe()
if (bank->base == bank2_base) {
stm32h7x.c:850stm32x_probe()
} else if (bank->base != bank1_base) {
stm32h7x.c:853stm32x_probe()
bank->base, bank1_base);
stm32h7x.c:859stm32x_probe()
bank->bank_number, flash_size_in_kb, bank->base);
stm32l4x.c:698stm32l4_flash_bank_command()
if (bank->base == 0)
stm32l4x.c:699stm32l4_flash_bank_command()
bank->base = STM32_FLASH_BANK_BASE;
stm32l4x.c:773stm32l4_is_otp()
return bank->base == stm32l4_info->part_info->otp_base;
stm32l4x.c:1443stm32l4_write_block()
uint32_t address = bank->base + offset;
stm32l4x.c:1566stm32l4_write_block_without_loader()
uint32_t address = bank->base + offset;
stm32l4x.c:1656stm32l4_write()
bank->base + head->offset + head->size,
stm32l4x.c:1657stm32l4_write()
bank->base + (head + 1)->offset - 1);
stm32l4x.c:1880stm32l4_probe()
LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
stm32l4x.c:1894stm32l4_probe()
} else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
stm32l5x.c:531stm32l4_write_block()
uint32_t address = bank->base + offset;
stm32l5x.c:833stm32l4_probe()
bank->base = base_address;
stm32lx.c:420stm32lx_write_half_pages()
uint32_t address = bank->base + offset;
stm32lx.c:615stm32lx_write()
uint32_t address = bank->base + offset;
stm32lx.c:809stm32lx_probe()
if (bank->base == second_bank_base || !bank->base) {
stm32lx.c:814stm32lx_probe()
} else if (bank->base == base_address) {
stm32lx.c:821stm32lx_probe()
bank->base, base_address, second_bank_base);
stm32lx.c:843stm32lx_probe()
bank->base = base_address;
stm32lx.c:1120stm32lx_erase_sector()
uint32_t addr = bank->base + bank->sectors[sector].offset + (page
stmqspi.c:1347qspi_verify()
offset + bank->base, count, ~crc32, result);
stmqspi.c:2163stmqspi_probe()
PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
stmqspi.c:2168stmqspi_probe()
PRIx32 ", QSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
stmsmi.c:428stmsmi_write()
retval = smi_write_buffer(bank, buffer, bank->base + offset,
stmsmi.c:446stmsmi_write()
retval = smi_write_buffer(bank, buffer, bank->base + offset,
stmsmi.c:461stmsmi_write()
retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
stmsmi.c:533stmsmi_probe()
switch (bank->base - target_device->smi_base) {
stmsmi.c:547stmsmi_probe()
LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
stmsmi.c:554stmsmi_probe()
target_device->name, bank->base);
str7x.c:436str7x_write_block()
uint32_t address = bank->base + offset;
str7x.c:551str7x_write()
uint32_t address = bank->base + offset;
str9x.c:89str9x_build_block_list()
bank1start = bank->base;
str9x.c:94str9x_build_block_list()
bank1start = bank->base;
str9x.c:243str9x_erase()
adr = bank->base + bank->sectors[i].offset;
str9x.c:310str9x_protect()
adr = bank->base + bank->sectors[i].offset;
str9x.c:338str9x_write_block()
uint32_t address = bank->base + offset;
str9x.c:449str9x_write()
uint32_t address = bank->base + offset;
swm050.c:47swm050_erase()
uint32_t curr_addr = bank->base + (SWM050_FLASH_PAGE_SIZE * curr_page);
swm050.c:79swm050_write()
retval = target_write_memory(target, bank->base + offset, 4, count/4, buffer);
target.c:6459handle_report_flash_progress()
command_print(cmd, "flash_bank_summary:0x%x|0x%x|%s", (uint32_t)bank->base, (uint32_t)bank->size, bank->name);
tcl.c:107handle_flash_info_command()
p->base,
tcl.c:170handle_flash_probe_command()
p->base);
tcl.c:198handle_flash_erase_check_command()
p->base);
tcl.c:562handle_flash_fill_command()
if (address + count * wordsize > bank->base + bank->size) {
tcl.c:622handle_flash_fill_command()
retval = flash_driver_write(bank, buffer, aligned_start - bank->base, aligned_size);
tcl.c:626handle_flash_fill_command()
retval = flash_driver_read(bank, buffer, address - bank->base, size_bytes);
tcl.c:708handle_flash_md_command()
uint32_t offset = address - bank->base;
tcl.c:782handle_flash_write_bank_command()
target_addr_t start_addr = bank->base + offset;
tcl.c:830handle_flash_write_bank_command()
retval = flash_driver_write(bank, buffer, aligned_start - bank->base, aligned_size);
tcl.c:1289handle_flash_bank_command()
COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[1], c->base);
tcl.c:1300handle_flash_bank_command()
"; usage: %s", driver_name, c->base, driver->usage);
tcl.c:1323handle_flash_banks_command()
p->name, p->driver->name, p->base, p->size,
tcl.c:1345handle_flash_list()
p->name, p->driver->name, p->base, p->size, p->bus_width, p->chip_width,
tms470.c:154tms470_read_part_info()
if (bank->base >= 0x00040000) {
tms470.c:158tms470_read_part_info()
bank->base);
tms470.c:162tms470_read_part_info()
bank->base = 0x00000000;
tms470.c:174tms470_read_part_info()
if (bank->base < 0x00008000) {
tms470.c:176tms470_read_part_info()
bank->base = 0x00000000;
tms470.c:184tms470_read_part_info()
} else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) {
tms470.c:186tms470_read_part_info()
bank->base = 0x00040000;
tms470.c:196tms470_read_part_info()
part_name, bank->base);
tms470.c:204tms470_read_part_info()
if (bank->base < 0x00020000) {
tms470.c:206tms470_read_part_info()
bank->base = 0x00000000;
tms470.c:214tms470_read_part_info()
} else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) {
tms470.c:216tms470_read_part_info()
bank->base = 0x00020000;
tms470.c:224tms470_read_part_info()
} else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) {
tms470.c:226tms470_read_part_info()
bank->base = 0x00040000;
tms470.c:236tms470_read_part_info()
part_name, bank->base);
tms470.c:674tms470_erase_sector()
uint32_t flash_addr = bank->base + bank->sectors[sector].offset;
tms470.c:891tms470_write()
count, bank->base + offset);
tms470.c:919tms470_write()
uint32_t addr = bank->base + offset + i;
tms470.c:1032tms470_erase_check()
uint32_t i, addr = bank->base + bank->sectors[sector].offset;
virtual.c:172virtual_info()
bank->driver->name, master_bank->name, master_bank->base);
w600.c:326w600_probe()
bank->base = W600_FLASH_BASE;
xmc1xxx.c:124xmc1xxx_erase()
buf_set_u32(reg_params[1].value, 0, 32, bank->base +
xmc1xxx.c:126xmc1xxx_erase()
buf_set_u32(reg_params[2].value, 0, 32, bank->base +
xmc1xxx.c:195xmc1xxx_erase_check()
uint32_t start = bank->base + bank->sectors[sector].offset;
xmc1xxx.c:305xmc1xxx_write()
uint32_t addr = bank->base + offset;
xmc1xxx.c:444xmc1xxx_probe()
uint32_t flash_addr = bank->base;
xmc1xxx.c:486xmc1xxx_probe()
bank->sectors[i].offset = flash_addr - bank->base;
xmc4xxx.c:406xmc4xxx_get_sector_start_addr()
*ret_addr = bank->base + bank->sectors[sector].offset;
xmc4xxx.c:494xmc4xxx_erase_sector()
erase_cmd_seq[5].address += bank->base;
xmc4xxx.c:632xmc4xxx_write_page()
write_cmd_seq[3].address = bank->base + offset;
xmc4xxx.c:770xmc4xxx_write()
bank->base + offset, end_pad);

Data Use

Functions writing flash_bank::base
Functions reading flash_bank::base
all items filtered out
flash_bank::base
all items filtered out
Type of flash_bank::base
flash_bank::base
all items filtered out