OpenOCD
flash_bank::target is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDflash_bank::target

flash_bank::target field

Target to which this bank belongs.

Syntax

struct target *target;

References

LocationReferrerText
core.h:78
struct target *target; /**< Target to which this bank belongs. */
FLASHPlugin.c:488plugin_write()
struct target *target = bank->target;
FLASHPlugin.c:602plugin_probe()
struct target *target = bank->target;
FLASHPlugin.c:683plugin_erase()
struct target *target = bank->target;
FLASHPlugin.c:715plugin_protect()
struct target *target = bank->target;
FLASHPlugin.c:747plugin_protect_check()
struct target *target = bank->target;
aduc702x.c:72aduc702x_erase()
struct target *target = bank->target;
aduc702x.c:126aduc702x_write_block()
struct target *target = bank->target;
aduc702x.c:269aduc702x_write_single()
struct target *target = bank->target;
aducm302x.c:133aducm302x_probe()
struct target *target = bank->target;
aducm302x.c:219aducm302x_mass_erase()
struct target *target = bank->target;
aducm302x.c:237aducm302x_erase()
struct target *target = bank->target;
aducm302x.c:277aducm302x_protect()
struct target *target = bank->target;
aducm302x.c:316aducm302x_protect_check()
struct target *target = bank->target;
aducm302x.c:343aducm302x_write_block()
struct target *target = bank->target;
aducm302x.c:436aducm302x_write()
struct target *target = bank->target;
aducm302x.c:446aducm302x_write()
if (bank->target->state != TARGET_HALTED) {
aducm360.c:161aducm360_erase()
struct target *target = bank->target;
aducm360.c:186aducm360_write_block_sync()
struct target *target = bank->target;
aducm360.c:306aducm360_write_block_async()
struct target *target = bank->target;
aducm360.c:445aducm360_write_modified()
struct target *target = bank->target;
ambiqmicro.c:172ambiqmicro_read_part_info()
struct target *target = bank->target;
ambiqmicro.c:337ambiqmicro_mass_erase()
target = bank->target;
ambiqmicro.c:404ambiqmicro_erase()
struct target *target = bank->target;
ambiqmicro.c:407ambiqmicro_erase()
if (bank->target->state != TARGET_HALTED) {
ambiqmicro.c:512ambiqmicro_protect()
if (bank->target->state != TARGET_HALTED) {
ambiqmicro.c:524ambiqmicro_write_block()
struct target *target = bank->target;
ambiqmicro.c:674ambiqmicro_otp_program()
target = bank->target;
at91sam3.c:2112efc_start_command()
r = target_write_u32(private->bank->target,
at91sam3.c:2958sam3_protect_check()
if (bank->target->state != TARGET_HALTED) {
at91sam3.c:2991sam3_flash_bank_command()
if (chip->target == bank->target)
at91sam3.c:3003sam3_flash_bank_command()
chip->target = bank->target;
at91sam3.c:3007sam3_flash_bank_command()
chip->target = bank->target;
at91sam3.c:3135_sam3_probe()
if (bank->target->state != TARGET_HALTED) {
at91sam3.c:3217sam3_erase()
if (bank->target->state != TARGET_HALTED) {
at91sam3.c:3248sam3_protect()
if (bank->target->state != TARGET_HALTED) {
at91sam3.c:3308sam3_page_write()
r = target_write_u32(private->bank->target, private->controller_address, fmr);
at91sam3.c:3366sam3_write()
if (bank->target->state != TARGET_HALTED) {
at91sam4.c:1562efc_start_command()
r = target_write_u32(private->bank->target,
at91sam4.c:2451sam4_protect_check()
if (bank->target->state != TARGET_HALTED) {
at91sam4.c:2484sam4_flash_bank_command()
if (chip->target == bank->target)
at91sam4.c:2496sam4_flash_bank_command()
chip->target = bank->target;
at91sam4.c:2500sam4_flash_bank_command()
chip->target = bank->target;
at91sam4.c:2641sam4_probe()
if (bank->target->state != TARGET_HALTED) {
at91sam4.c:2731sam4_erase()
if (bank->target->state != TARGET_HALTED) {
at91sam4.c:2780sam4_protect()
if (bank->target->state != TARGET_HALTED) {
at91sam4.c:2837sam4_set_wait()
r = target_write_u32(private->bank->target, private->controller_address, fmr);
at91sam4.c:2910sam4_write()
if (bank->target->state != TARGET_HALTED) {
at91sam4l.c:210sam4l_flash_bank_command()
chip->target = bank->target;
at91sam4l.c:239sam4l_check_page_erased()
res = sam4l_flash_command(bank->target, SAM4L_FCMD_QPR, pn);
at91sam4l.c:246sam4l_check_page_erased()
res = target_read_u32(bank->target, SAM4L_FLASHCALW + SAM4L_FSR, &st);
at91sam4l.c:267sam4l_probe()
res = target_read_u32(bank->target, SAM4L_CHIPID + SAM4L_CIDR, &id);
at91sam4l.c:273sam4l_probe()
res = target_read_u32(bank->target, SAM4L_CHIPID + SAM4L_EXID, &exid);
at91sam4l.c:301sam4l_probe()
res = target_read_u32(bank->target, SAM4L_FLASHCALW + SAM4L_FPR, &param);
at91sam4l.c:352sam4l_protect_check()
if (bank->target->state != TARGET_HALTED) {
at91sam4l.c:363sam4l_protect_check()
res = target_read_u32(bank->target, SAM4L_FLASHCALW + SAM4L_FSR, &st);
at91sam4l.c:379sam4l_protect()
if (bank->target->state != TARGET_HALTED) {
at91sam4l.c:403sam4l_protect()
res = sam4l_flash_command(bank->target,
at91sam4l.c:420sam4l_erase()
if (bank->target->state != TARGET_HALTED) {
at91sam4l.c:442sam4l_erase()
ret = sam4l_flash_command(bank->target, SAM4L_FCMD_EA, -1);
at91sam4l.c:458sam4l_erase()
ret = sam4l_flash_command(bank->target, SAM4L_FCMD_EP, pn);
at91sam4l.c:530sam4l_write_page_partial()
res = target_read_memory(bank->target, address, 4,
at91sam4l.c:541sam4l_write_page_partial()
res = sam4l_write_page(chip, bank->target, address, pg);
at91sam4l.c:556sam4l_write()
if (bank->target->state != TARGET_HALTED) {
at91sam4l.c:598sam4l_write()
res = sam4l_write_page(chip, bank->target,
at91sam7.c:180at91sam7_read_clock_info()
struct target *target = bank->target;
at91sam7.c:251at91sam7_set_flash_mode()
struct target *target = bank->target;
at91sam7.c:292at91sam7_wait_status_busy()
while ((!((status = at91sam7_get_flash_status(bank->target,
at91sam7.c:318at91sam7_flash_command()
struct target *target = bank->target;
at91sam7.c:344at91sam7_read_part_info()
struct target *target = bank->target;
at91sam7.c:364at91sam7_read_part_info()
if (t_bank->target != target)
at91sam7.c:389at91sam7_read_part_info()
if (t_bank->target != target)
at91sam7.c:568at91sam7_read_part_info()
fb->target = target;
at91sam7.c:639at91sam7_erase_check()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:660at91sam7_protect_check()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:665at91sam7_protect_check()
status = at91sam7_get_flash_status(bank->target, bank->bank_number);
at91sam7.c:678at91sam7_protect_check()
status = at91sam7_get_flash_status(bank->target, 0);
at91sam7.c:696at91sam7_flash_bank_command()
struct target *target = t_bank->target;
at91sam7.c:756at91sam7_flash_bank_command()
fb->target = target;
at91sam7.c:813at91sam7_erase()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:865at91sam7_protect()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:900at91sam7_write()
struct target *target = bank->target;
at91sam7.c:907at91sam7_write()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:969at91sam7_probe()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:1049at91sam7_handle_gpnvm_command()
if (bank->target->state != TARGET_HALTED) {
at91sam7.c:1085at91sam7_handle_gpnvm_command()
status = at91sam7_get_flash_status(bank->target, 0);
at91samd.c:403samd_protect_check()
res = target_read_u16(bank->target,
at91samd.c:447samd_probe()
res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
at91samd.c:461samd_probe()
res = samd_get_flash_page_info(bank->target, &chip->page_size,
at91samd.c:756samd_protect()
if (bank->target->state != TARGET_HALTED) {
at91samd.c:764samd_protect()
res = target_write_u32(bank->target,
at91samd.c:771samd_protect()
res = samd_issue_nvmctrl_command(bank->target,
at91samd.c:784samd_protect()
res = samd_modify_user_row(bank->target,
at91samd.c:804samd_erase()
if (bank->target->state != TARGET_HALTED) {
at91samd.c:817samd_erase()
res = samd_erase_row(bank->target, bank->sectors[s].offset);
at91samd.c:841samd_write()
if (bank->target->state != TARGET_HALTED) {
at91samd.c:852samd_write()
res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
at91samd.c:862samd_write()
res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
at91samd.c:899samd_write()
res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
at91samd.c:906samd_write()
res = target_write_memory(bank->target, address, 4, nw, buffer);
at91samd.c:918samd_write()
res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
at91samd.c:923samd_write()
res = samd_check_error(bank->target);
at91samd.c:959samd_flash_bank_command()
chip->target = bank->target;
ath79.c:236ath79_spi_bitbang_chunk()
struct target *target = bank->target;
ath79.c:492ath79_erase()
struct target *target = bank->target;
ath79.c:636ath79_write()
struct target *target = bank->target;
ath79.c:705ath79_read()
struct target *target = bank->target;
ath79.c:726read_flash_id()
struct target *target = bank->target;
ath79.c:756ath79_probe()
struct target *target = bank->target;
atsame5.c:232same5_protect_check()
res = target_read_u32(bank->target,
atsame5.c:276same5_probe()
res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
atsame5.c:290same5_probe()
res = samd_get_flash_page_info(bank->target, &chip->page_size,
atsame5.c:575same5_protect()
if (bank->target->state != TARGET_HALTED) {
atsame5.c:583same5_protect()
res = target_write_u32(bank->target,
atsame5.c:590same5_protect()
res = same5_issue_nvmctrl_command(bank->target,
atsame5.c:606same5_protect()
res = same5_modify_user_row_masked(bank->target,
atsame5.c:625same5_erase()
if (bank->target->state != TARGET_HALTED) {
atsame5.c:636same5_erase()
res = same5_erase_block(bank->target, bank->sectors[s].offset);
atsame5.c:658same5_write()
res = same5_pre_write_check(bank->target);
atsame5.c:665same5_write()
res = same5_issue_nvmctrl_command(bank->target, SAME5_NVM_CMD_PBC);
atsame5.c:702same5_write()
res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
atsame5.c:709same5_write()
res = target_write_memory(bank->target, address, 4, nw, buffer);
atsame5.c:716same5_write()
res = same5_issue_nvmctrl_command(bank->target, SAME5_NVM_CMD_WP);
atsame5.c:749same5_flash_bank_command()
chip->target = bank->target;
atsamv.c:278samv_protect_check()
r = samv_efc_perform_command(bank->target, SAMV_EFC_FCMD_GLB, 0, NULL);
atsamv.c:280samv_protect_check()
samv_efc_get_result(bank->target, &v[0]);
atsamv.c:281samv_protect_check()
samv_efc_get_result(bank->target, &v[1]);
atsamv.c:282samv_protect_check()
samv_efc_get_result(bank->target, &v[2]);
atsamv.c:283samv_protect_check()
r = samv_efc_get_result(bank->target, &v[3]);
atsamv.c:304samv_get_device_id()
return target_read_u32(bank->target, SAMV_CHIPID_CIDR, device_id);
atsamv.c:371samv_erase()
if (bank->target->state != TARGET_HALTED) {
atsamv.c:382samv_erase()
return samv_efc_perform_command(bank->target, SAMV_EFC_FCMD_EA, 0, NULL);
atsamv.c:388samv_erase()
r = samv_erase_pages(bank->target, (i * page_count), page_count, &status);
atsamv.c:407samv_protect()
if (bank->target->state != TARGET_HALTED) {
atsamv.c:414samv_protect()
r = samv_flash_lock(bank->target, first, last);
atsamv.c:416samv_protect()
r = samv_flash_unlock(bank->target, first, last);
atsamv.c:463samv_write()
if (bank->target->state != TARGET_HALTED) {
atsamv.c:500samv_write()
r = samv_page_read(bank->target, page_cur, pagebuffer);
atsamv.c:507samv_write()
r = samv_page_write(bank->target, page_cur, pagebuffer);
atsamv.c:518samv_write()
r = samv_page_read(bank->target, page_cur, pagebuffer);
atsamv.c:526samv_write()
r = samv_page_write(bank->target, page_cur, pagebuffer);
atsamv.c:544samv_write()
r = samv_page_write(bank->target, page_cur, buffer);
atsamv.c:556samv_write()
r = samv_page_read(bank->target, page_cur, pagebuffer);
atsamv.c:560samv_write()
r = samv_page_write(bank->target, page_cur, pagebuffer);
atsamv.c:586samv_handle_gpnvm_command()
struct target *target = bank->target;
avrf.c:214avrf_erase()
struct target *target = bank->target;
avrf.c:238avrf_write()
struct target *target = bank->target;
avrf.c:243avrf_write()
if (bank->target->state != TARGET_HALTED) {
avrf.c:294avrf_probe()
struct target *target = bank->target;
avrf.c:300avrf_probe()
if (bank->target->state != TARGET_HALTED) {
avrf.c:362avrf_info()
struct target *target = bank->target;
avrf.c:367avrf_info()
if (bank->target->state != TARGET_HALTED) {
avrf.c:405avrf_mass_erase()
struct target *target = bank->target;
bluenrg-x.c:125bluenrgx_read_flash_reg()
return target_read_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value);
bluenrg-x.c:130bluenrgx_write_flash_reg()
return target_write_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value);
bluenrg-x.c:140bluenrgx_erase()
struct target *target = bank->target;
bluenrg-x.c:147bluenrgx_erase()
if (bank->target->state != TARGET_HALTED) {
bluenrg-x.c:236bluenrgx_write()
struct target *target = bank->target;
bluenrg-x.c:265bluenrgx_write()
if (bank->target->state != TARGET_HALTED) {
bluenrg-x.c:385bluenrgx_probe()
int retval = target_read_u32(bank->target, BLUENRGLP_JTAG_REG, &idcode);
bluenrg-x.c:391bluenrgx_probe()
retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode);
bluenrg-x.c:412bluenrgx_probe()
retval = target_read_u32(bank->target, DIE_ID_REG(bluenrgx_info), &die_id);
cc26xx.c:98cc26xx_wait_algo_done()
struct target *target = bank->target;
cc26xx.c:131cc26xx_init()
struct target *target = bank->target;
cc26xx.c:190cc26xx_quit()
struct target *target = bank->target;
cc26xx.c:210cc26xx_mass_erase()
struct target *target = bank->target;
cc26xx.c:271cc26xx_erase()
struct target *target = bank->target;
cc26xx.c:320cc26xx_write()
struct target *target = bank->target;
cc26xx.c:403cc26xx_probe()
struct target *target = bank->target;
cc3220sf.c:32cc3220sf_mass_erase()
struct target *target = bank->target;
cc3220sf.c:106cc3220sf_erase()
struct target *target = bank->target;
cc3220sf.c:174cc3220sf_write()
struct target *target = bank->target;
cfi.c:126cfi_target_write_memory()
return target_write_memory(bank->target, addr, bank->bus_width,
cfi.c:138cfi_target_read_memory()
return target_read_memory(bank->target, addr, bank->bus_width,
cfi.c:822cfi_flash_bank_cmd()
bank->target->endianness == TARGET_LITTLE_ENDIAN ?
cfi.c:825cfi_flash_bank_cmd()
cfi_info->endianness = bank->target->endianness;
cfi.c:936cfi_erase()
if (bank->target->state != TARGET_HALTED) {
cfi.c:1078cfi_protect()
if (bank->target->state != TARGET_HALTED) {
cfi.c:1098cfi_command_val()
struct target *target = bank->target;
cfi.c:1119cfi_intel_write_block()
struct target *target = bank->target;
cfi.c:1370cfi_spansion_write_block_mips()
struct target *target = bank->target;
cfi.c:1582cfi_spansion_write_block()
struct target *target = bank->target;
cfi.c:2225cfi_read()
if (bank->target->state != TARGET_HALTED) {
cfi.c:2294cfi_write()
if (bank->target->state != TARGET_HALTED) {
cfi.c:2535cfi_probe()
struct target *target = bank->target;
cfi.c:2543cfi_probe()
if (bank->target->state != TARGET_HALTED) {
cfi.c:2934cfi_protect_check()
if (bank->target->state != TARGET_HALTED) {
core.c:124default_flash_read()
return target_read_buffer(bank->target, offset + bank->base, count, buffer);
core.c:152default_flash_verify()
retval = target_checksum_memory(bank->target, offset + bank->base, count, &target_crc);
core.c:309get_flash_bank_by_addr()
if (c->target != target)
core.c:335default_flash_mem_blank_check()
struct target *target = bank->target;
core.c:340default_flash_mem_blank_check()
if (bank->target->state != TARGET_HALTED) {
core.c:382default_flash_blank_check()
struct target *target = bank->target;
core.c:385default_flash_blank_check()
if (bank->target->state != TARGET_HALTED) {
dsp5680xx_flash.c:76dsp5680xx_flash_protect_check()
retval = dsp5680xx_f_protect_check(bank->target, &protected);
dsp5680xx_flash.c:118dsp5680xx_flash_protect()
retval = dsp5680xx_f_lock(bank->target);
dsp5680xx_flash.c:120dsp5680xx_flash_protect()
retval = dsp5680xx_f_unlock(bank->target);
dsp5680xx_flash.c:152dsp5680xx_flash_write()
return dsp5680xx_f_wr(bank->target, buffer, bank->base + offset / 2, count, 0);
dsp5680xx_flash.c:177dsp5680xx_flash_erase()
return dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last);
dsp5680xx_flash.c:197dsp5680xx_flash_erase_check()
retval = dsp5680xx_f_erase_check(bank->target, &erased, i);
efm32.c:205efm32x_get_flash_size()
return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
efm32.c:210efm32x_get_ram_size()
return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
efm32.c:215efm32x_get_part_num()
return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
efm32.c:220efm32x_get_part_family()
return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
efm32.c:225efm32x_get_prod_rev()
return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
efm32.c:234efm32x_read_reg_u32()
return target_read_u32(bank->target, base + offset, value);
efm32.c:243efm32x_write_reg_u32()
return target_write_u32(bank->target, base + offset, value);
efm32.c:302efm32x_read_info()
ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
efm32.c:350efm32x_flash_bank_command()
&& bank_iter->target == bank->target
efm32.c:502efm32x_erase()
struct target *target = bank->target;
efm32.c:540efm32x_read_lock_data()
struct target *target = bank->target;
efm32.c:630efm32x_write_lock_data()
ret = target_read_buffer(bank->target, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes, extra_data);
efm32.c:707efm32x_protect()
struct target *target = bank->target;
efm32.c:735efm32x_write_block()
struct target *target = bank->target;
efm32.c:966efm32x_priv_write()
struct target *target = bank->target;
efm32.c:1115efm32x_protect_check()
struct target *target = bank->target;
efm32.c:1167efm32x_handle_debuglock_command()
target = bank->target;
em357.c:103em357_get_flash_status()
struct target *target = bank->target;
em357.c:109em357_wait_status_busy()
struct target *target = bank->target;
em357.c:152em357_read_options()
struct target *target = bank->target;
em357.c:182em357_erase_options()
struct target *target = bank->target;
em357.c:228em357_write_options()
struct target *target = bank->target;
em357.c:302em357_protect_check()
struct target *target = bank->target;
em357.c:338em357_erase()
struct target *target = bank->target;
em357.c:340em357_erase()
if (bank->target->state != TARGET_HALTED) {
em357.c:387em357_protect()
struct target *target = bank->target;
em357.c:447em357_write_block()
struct target *target = bank->target;
em357.c:574em357_write()
struct target *target = bank->target;
em357.c:581em357_write()
if (bank->target->state != TARGET_HALTED) {
em357.c:663em357_probe()
struct target *target = bank->target;
em357.c:756em357_handle_lock_command()
target = bank->target;
em357.c:793em357_handle_unlock_command()
target = bank->target;
em357.c:819em357_mass_erase()
struct target *target = bank->target;
eneispif.c:76eneispif_read_reg()
struct target *target = bank->target;
eneispif.c:92eneispif_write_reg()
struct target *target = bank->target;
eneispif.c:162eneispif_erase()
struct target *target = bank->target;
eneispif.c:213eneispif_write()
struct target *target = bank->target;
eneispif.c:291eneispif_read_flash_id()
struct target *target = bank->target;
esirisc_flash.c:127esirisc_flash_unlock()
struct target *target = bank->target;
esirisc_flash.c:139esirisc_flash_disable_protect()
struct target *target = bank->target;
esirisc_flash.c:158esirisc_flash_enable_protect()
struct target *target = bank->target;
esirisc_flash.c:177esirisc_flash_check_status()
struct target *target = bank->target;
esirisc_flash.c:192esirisc_flash_clear_status()
struct target *target = bank->target;
esirisc_flash.c:202esirisc_flash_wait()
struct target *target = bank->target;
esirisc_flash.c:222esirisc_flash_control()
struct target *target = bank->target;
esirisc_flash.c:246esirisc_flash_erase()
struct target *target = bank->target;
esirisc_flash.c:274esirisc_flash_mass_erase()
struct target *target = bank->target;
esirisc_flash.c:300esirisc_flash_ref_erase()
struct target *target = bank->target;
esirisc_flash.c:321esirisc_flash_fill_pb()
struct target *target = bank->target;
esirisc_flash.c:352esirisc_flash_write()
struct target *target = bank->target;
esirisc_flash.c:411esirisc_flash_init()
struct target *target = bank->target;
esirisc_flash.c:449esirisc_flash_probe()
struct target *target = bank->target;
fespi.c:162fespi_read_reg()
struct target *target = bank->target;
fespi.c:176fespi_write_reg()
struct target *target = bank->target;
fespi.c:359fespi_erase()
struct target *target = bank->target;
fespi.c:484fespi_write()
struct target *target = bank->target;
fespi.c:673fespi_read_flash_id()
struct target *target = bank->target;
fespi.c:725fespi_probe()
struct target *target = bank->target;
fm3.c:197fm3_erase()
struct target *target = bank->target;
fm3.c:341fm3_write_block()
struct target *target = bank->target;
fm3.c:627fm3_probe()
if (bank->target->state != TARGET_HALTED) {
fm3.c:804fm3_chip_erase()
struct target *target = bank->target;
fm4.c:106fm4_flash_erase()
struct target *target = bank->target;
fm4.c:204fm4_flash_write()
struct target *target = bank->target;
fm4.c:408s6e2cc_probe()
struct target *target = bank->target;
fm4.c:500fm4_probe()
if (bank->target->state != TARGET_HALTED) {
fm4.c:547fm4_get_info_command()
if (bank->target->state != TARGET_HALTED) {
gdb_server.c:1051gdb_new_connection()
if (p->target != target)
gdb_server.c:1990gdb_memory_map()
if (p->target != target)
jtagspi.c:70jtagspi_flash_bank_command()
if (!bank->target->tap) {
jtagspi.c:74jtagspi_flash_bank_command()
info->tap = bank->target->tap;
kinetis.c:891kinetis_get_chip()
|| bank_iter->target != target)
kinetis.c:920kinetis_flash_bank_command()
struct target *target = bank->target;
kinetis.c:1038kinetis_create_missing_banks()
bank->target = k_chip->target;
kinetis.c:1305kinetis_write_block()
struct target *target = bank->target;
kinetis.c:1426kinetis_protect_check()
result = target_read_u32(bank->target, FTFX_FPROT3, &fprot);
kinetis.c:1436kinetis_protect_check()
result = target_read_u8(bank->target, FTFX_FDPROT, &fdprot);
kinetis.c:1513kinetis_fill_fcf()
target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
kinetis.c:1705kinetis_erase()
result = kinetis_ftfx_prepare(bank->target);
kinetis.c:1719kinetis_erase()
result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
kinetis.c:1824kinetis_write_sections()
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
kinetis.c:1831kinetis_write_sections()
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
kinetis.c:1844kinetis_write_sections()
result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTWRITE,
kinetis.c:1892kinetis_write_inner()
result = kinetis_make_ram_ready(bank->target);
kinetis.c:1947kinetis_write_inner()
result = kinetis_ftfx_command(bank->target, FTFX_CMD_LWORDPROG, k_bank->prog_base + offset,
kinetis.c:1998kinetis_write()
result = kinetis_ftfx_prepare(bank->target);
kinetis.c:2068kinetis_write()
result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
kinetis.c:3082kinetis_blank_check()
result = kinetis_ftfx_prepare(bank->target);
kinetis.c:3100kinetis_blank_check()
result = kinetis_ftfx_command(bank->target, FTFX_CMD_BLOCKSTAT, k_bank->prog_base,
kinetis.c:3104kinetis_blank_check()
kinetis_ftfx_clear_error(bank->target);
kinetis.c:3113kinetis_blank_check()
result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTSTAT,
kinetis.c:3121kinetis_blank_check()
kinetis_ftfx_clear_error(bank->target);
kinetis_ke.c:210kinetis_ke_prepare_flash()
struct target *target = bank->target;
kinetis_ke.c:692kinetis_ke_write_words()
struct target *target = bank->target;
kinetis_ke.c:777kinetis_ke_protect()
if (bank->target->state != TARGET_HALTED) {
kinetis_ke.c:789kinetis_ke_protect_check()
if (bank->target->state != TARGET_HALTED) {
kinetis_ke.c:802kinetis_ke_protect_check()
result = target_read_u8(bank->target, kinfo->ftmrx_fprot_addr, &fprot);
kinetis_ke.c:885kinetis_ke_ftmrx_command()
struct target *target = bank->target;
kinetis_ke.c:946kinetis_ke_erase()
if (bank->target->state != TARGET_HALTED) {
kinetis_ke.c:993kinetis_ke_write()
if (bank->target->state != TARGET_HALTED) {
kinetis_ke.c:1006kinetis_ke_write()
result = kinetis_ke_stop_watchdog(bank->target);
kinetis_ke.c:1042kinetis_ke_probe()
struct target *target = bank->target;
kinetis_ke.c:1157kinetis_ke_blank_check()
if (bank->target->state != TARGET_HALTED) {
lpc2000.c:677lpc2000_iap_working_area_init()
struct target *target = bank->target;
lpc2000.c:725lpc2000_iap_call()
struct target *target = bank->target;
lpc2000.c:901lpc2000_iap_blank_check()
struct target *target = bank->target;
lpc2000.c:974lpc2000_erase()
if (bank->target->state != TARGET_HALTED) {
lpc2000.c:1042lpc2000_erase()
struct target *target = bank->target;
lpc2000.c:1050lpc2000_write()
struct target *target = bank->target;
lpc2000.c:1052lpc2000_write()
if (bank->target->state != TARGET_HALTED) {
lpc2000.c:1167lpc2000_write()
retval = target_write_buffer(bank->target, download_area->address, thisrun_bytes, buffer + bytes_written);
lpc2000.c:1176lpc2000_write()
target_write_buffer(bank->target, download_area->address, thisrun_bytes, last_buffer);
lpc2000.c:1223get_lpc2000_part_id()
if (bank->target->state != TARGET_HALTED) {
lpc2000.c:1241get_lpc2000_part_id()
struct target *target = bank->target;
lpc2000.c:1258lpc2000_auto_probe_flash()
if (bank->target->state != TARGET_HALTED) {
lpc2000.c:1536lpc2000_erase_check()
if (bank->target->state != TARGET_HALTED) {
lpc2000.c:1564lpc2000_handle_part_id_command()
if (bank->target->state != TARGET_HALTED) {
lpc288x.c:96lpc288x_wait_status_busy()
struct target *target = bank->target;
lpc288x.c:114lpc288x_read_part_info()
struct target *target = bank->target;
lpc288x.c:193lpc288x_set_flash_clk()
target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN);
lpc288x.c:194lpc288x_set_flash_clk()
target_write_u32(bank->target, F_CLK_TIME, clk_time);
lpc288x.c:217lpc288x_system_ready()
if (bank->target->state != TARGET_HALTED) {
lpc288x.c:228lpc288x_erase()
struct target *target = bank->target;
lpc288x.c:261lpc288x_write()
struct target *target = bank->target;
lpc288x.c:359lpc288x_probe()
if (bank->target->state != TARGET_HALTED) {
lpc288x.c:375lpc288x_protect()
struct target *target = bank->target;
lpc2900.c:185lpc2900_wait_status()
struct target *target = bank->target;
lpc2900.c:214lpc2900_setup()
target_write_u32(bank->target, FCTR, FCTR_FS_WEB | FCTR_FS_CS);
lpc2900.c:217lpc2900_setup()
target_write_u32(bank->target, FCRA, fcra);
lpc2900.c:234lpc2900_is_ready()
if (bank->target->state != TARGET_HALTED) {
lpc2900.c:253lpc2900_read_security_status()
struct target *target = bank->target;
lpc2900.c:317lpc2900_run_bist128()
struct target *target = bank->target;
lpc2900.c:382lpc2900_write_index_page()
struct target *target = bank->target;
lpc2900.c:482lpc2900_handle_signature_command()
if (bank->target->state != TARGET_HALTED) {
lpc2900.c:521lpc2900_handle_read_custom_command()
struct target *target = bank->target;
lpc2900.c:619lpc2900_handle_write_custom_command()
struct target *target = bank->target;
lpc2900.c:941lpc2900_erase()
struct target *target = bank->target;
lpc2900.c:1051lpc2900_write()
struct target *target = bank->target;
lpc2900.c:1363lpc2900_probe()
struct target *target = bank->target;
lpcspifi.c:125lpcspifi_set_hw_mode()
struct target *target = bank->target;
lpcspifi.c:227lpcspifi_set_sw_mode()
struct target *target = bank->target;
lpcspifi.c:281read_status_reg()
struct target *target = bank->target;
lpcspifi.c:338lpcspifi_write_enable()
struct target *target = bank->target;
lpcspifi.c:372lpcspifi_bulk_erase()
struct target *target = bank->target;
lpcspifi.c:409lpcspifi_erase()
struct target *target = bank->target;
lpcspifi.c:573lpcspifi_write()
struct target *target = bank->target;
lpcspifi.c:760lpcspifi_read_flash_id()
struct target *target = bank->target;
max32xxx.c:123max32xxx_flash_op_pre()
struct target *target = bank->target;
max32xxx.c:181max32xxx_flash_op_post()
struct target *target = bank->target;
max32xxx.c:198max32xxx_protect_check()
struct target *target = bank->target;
max32xxx.c:229max32xxx_erase()
struct target *target = bank->target;
max32xxx.c:233max32xxx_erase()
if (bank->target->state != TARGET_HALTED) {
max32xxx.c:313max32xxx_protect()
struct target *target = bank->target;
max32xxx.c:316max32xxx_protect()
if (bank->target->state != TARGET_HALTED) {
max32xxx.c:354max32xxx_write_block()
struct target *target = bank->target;
max32xxx.c:431max32xxx_write()
struct target *target = bank->target;
max32xxx.c:439max32xxx_write()
if (bank->target->state != TARGET_HALTED) {
max32xxx.c:635max32xxx_probe()
struct target *target = bank->target;
max32xxx.c:686max32xxx_mass_erase()
target = bank->target;
mdr.c:80mdr_mass_erase()
struct target *target = bank->target;
mdr.c:119mdr_erase()
struct target *target = bank->target;
mdr.c:125mdr_erase()
if (bank->target->state != TARGET_HALTED) {
mdr.c:207mdr_write_block()
struct target *target = bank->target;
mdr.c:298mdr_write()
struct target *target = bank->target;
mdr.c:302mdr_write()
if (bank->target->state != TARGET_HALTED) {
mdr.c:455mdr_write()
target_checksum_memory(bank->target, bank->base, 64, &tmp);
mdr.c:464mdr_read()
struct target *target = bank->target;
mdr.c:471mdr_read()
if (bank->target->state != TARGET_HALTED) {
mrvlqspi.c:79mrvlqspi_set_din_cnt()
struct target *target = bank->target;
mrvlqspi.c:86mrvlqspi_set_addr()
struct target *target = bank->target;
mrvlqspi.c:93mrvlqspi_set_instr()
struct target *target = bank->target;
mrvlqspi.c:100mrvlqspi_set_hdr_cnt()
struct target *target = bank->target;
mrvlqspi.c:109mrvlqspi_set_conf()
struct target *target = bank->target;
mrvlqspi.c:127mrvlqspi_set_ss_state()
struct target *target = bank->target;
mrvlqspi.c:166mrvlqspi_start_transfer()
struct target *target = bank->target;
mrvlqspi.c:196mrvlqspi_stop_transfer()
struct target *target = bank->target;
mrvlqspi.c:255mrvlqspi_fifo_flush()
struct target *target = bank->target;
mrvlqspi.c:291mrvlqspi_read_byte()
struct target *target = bank->target;
mrvlqspi.c:522mrvlqspi_flash_erase()
struct target *target = bank->target;
mrvlqspi.c:581mrvlqspi_flash_write()
struct target *target = bank->target;
mrvlqspi.c:756mrvlqspi_flash_read()
struct target *target = bank->target;
mrvlqspi.c:820mrvlqspi_probe()
struct target *target = bank->target;
msp432.c:281msp432_init()
struct target *target = bank->target;
msp432.c:403msp432_quit()
struct target *target = bank->target;
msp432.c:434msp432_mass_erase()
struct target *target = bank->target;
msp432.c:601msp432_erase()
struct target *target = bank->target;
msp432.c:676msp432_write()
struct target *target = bank->target;
msp432.c:810msp432_probe()
struct target *target = bank->target;
msp432.c:951msp432_probe()
info->target = bank->target;
msp432p4.c:179msp432p4_run_algo()
struct target *target = bank->target;
msp432p4.c:231msp432p4_init()
struct target *target = bank->target;
msp432p4.c:262msp432p4_mass_erase()
struct target *target = bank->target;
msp432p4.c:293msp432p4_sector_erase()
struct target *target = bank->target;
msp432p4.c:399msp432p4_erase()
struct target *target = bank->target;
msp432p4.c:434msp432p4_write()
struct target *target = bank->target;
msp432p4.c:445msp432p4_write()
if (bank->target->state != TARGET_HALTED) {
msp432p4.c:519msp432p4_probe()
struct target *target = bank->target;
niietcm4.c:144niietcm4_opstatus_check()
struct target *target = bank->target;
niietcm4.c:181niietcm4_uopstatus_check()
struct target *target = bank->target;
niietcm4.c:221niietcm4_dump_uflash_page()
struct target *target = bank->target;
niietcm4.c:257niietcm4_load_uflash_page()
struct target *target = bank->target;
niietcm4.c:293niietcm4_uflash_page_erase()
struct target *target = bank->target;
niietcm4.c:386niietcm4_handle_uflash_read_byte_command()
struct target *target = bank->target;
niietcm4.c:433niietcm4_handle_uflash_write_byte_command()
struct target *target = bank->target;
niietcm4.c:489niietcm4_handle_uflash_full_erase_command()
struct target *target = bank->target;
niietcm4.c:527niietcm4_handle_uflash_erase_command()
struct target *target = bank->target;
niietcm4.c:571niietcm4_handle_uflash_protect_check_command()
struct target *target = bank->target;
niietcm4.c:661niietcm4_handle_uflash_protect_command()
struct target *target = bank->target;
niietcm4.c:713niietcm4_handle_bflash_info_remap_command()
struct target *target = bank->target;
niietcm4.c:763niietcm4_handle_extmem_cfg_command()
struct target *target = bank->target;
niietcm4.c:840niietcm4_handle_extmem_boot_command()
struct target *target = bank->target;
niietcm4.c:891niietcm4_handle_service_mode_erase_command()
struct target *target = bank->target;
niietcm4.c:1069niietcm4_protect_check()
struct target *target = bank->target;
niietcm4.c:1137niietcm4_mass_erase()
struct target *target = bank->target;
niietcm4.c:1159niietcm4_erase()
struct target *target = bank->target;
niietcm4.c:1163niietcm4_erase()
if (bank->target->state != TARGET_HALTED) {
niietcm4.c:1206niietcm4_protect()
struct target *target = bank->target;
niietcm4.c:1268niietcm4_write_block()
struct target *target = bank->target;
niietcm4.c:1362niietcm4_write()
struct target *target = bank->target;
niietcm4.c:1366niietcm4_write()
if (bank->target->state != TARGET_HALTED) {
niietcm4.c:1466niietcm4_probe_k1921vk01t()
struct target *target = bank->target;
niietcm4.c:1667niietcm4_probe()
struct target *target = bank->target;
npcx.c:79npcx_init()
struct target *target = bank->target;
npcx.c:136npcx_quit()
struct target *target = bank->target;
npcx.c:154npcx_wait_algo_done()
struct target *target = bank->target;
npcx.c:181npcx_get_flash_id()
struct target *target = bank->target;
npcx.c:340npcx_chip_erase()
struct target *target = bank->target;
npcx.c:389npcx_erase()
struct target *target = bank->target;
npcx.c:448npcx_write()
struct target *target = bank->target;
npcx.c:523npcx_info()
target_name(bank->target),
nrf5.c:624nrf5_protect()
if (bank->target->state != TARGET_HALTED) {
nrf5.c:1228nrf5_write()
if (bank->target->state != TARGET_HALTED) {
nrf5.c:1288nrf5_erase()
if (bank->target->state != TARGET_HALTED) {
nrf5.c:1358nrf5_get_chip()
if (bank_iter->target != target)
nrf5.c:1391nrf5_flash_bank_command()
chip = nrf5_get_chip(bank->target);
nrf5.c:1398nrf5_flash_bank_command()
chip->target = bank->target;
numicro.c:695numicro_writeblock()
struct target *target = bank->target;
numicro.c:811numicro_protect_check()
struct target *target = bank->target;
numicro.c:858numicro_erase()
struct target *target = bank->target;
numicro.c:929numicro_write()
struct target *target = bank->target;
numicro.c:1071numicro_probe()
struct target *target = bank->target;
ocl.c:31ocl_flash_bank_command()
arm7_9 = target_to_arm7_9(bank->target);
ocl.c:54ocl_erase()
if (bank->target->state != TARGET_RUNNING) {
ocl.c:110ocl_write()
if (bank->target->state != TARGET_RUNNING) {
pic32mm.c:221pic32mm_get_flash_status()
struct target *target = bank->target;
pic32mm.c:246pic32mm_nvm_exec()
struct target *target = bank->target;
pic32mm.c:272pic32mm_protect_check()
struct target *target = bank->target;
pic32mm.c:292pic32mm_unprotect_sectors()
retval = target_read_u32(bank->target, PIC32MM_NVMBWP, &reg);
pic32mm.c:321pic32mm_unprotect_sectors()
target_write_u32(bank->target, PIC32MM_NVMKEY, NVMKEY1);
pic32mm.c:322pic32mm_unprotect_sectors()
target_write_u32(bank->target, PIC32MM_NVMKEY, NVMKEY2);
pic32mm.c:324pic32mm_unprotect_sectors()
retval = target_write_u32(bank->target, PIC32MM_NVMBWP, reg);
pic32mm.c:331pic32mm_unprotect_sectors()
retval = target_read_u32(bank->target, PIC32MM_NVMPWP, &reg);
pic32mm.c:355pic32mm_unprotect_sectors()
target_write_u32(bank->target, PIC32MM_NVMKEY, NVMKEY1);
pic32mm.c:356pic32mm_unprotect_sectors()
target_write_u32(bank->target, PIC32MM_NVMKEY, NVMKEY2);
pic32mm.c:358pic32mm_unprotect_sectors()
retval = target_write_u32(bank->target, PIC32MM_NVMPWP, reg);
pic32mm.c:369pic32mm_invalidate_flash_line_buffer()
int res = target_read_memory(bank->target, bank->base, 4, 1, tmp);
pic32mm.c:374pic32mm_invalidate_flash_line_buffer()
res = target_read_memory(bank->target, bank->base + pic32mm_info->layout.page_size_in_words * PIC32MM_FLASH_WORD_SIZE_IN_BYTES, 4, 1, tmp);
pic32mm.c:382pic32mm_erase()
struct target *target = bank->target;
pic32mm.c:385pic32mm_erase()
if (bank->target->state != TARGET_HALTED) {
pic32mm.c:425pic32mm_protect()
struct target *target = bank->target;
pic32mm.c:571pic32mm_write_using_loader()
struct target *target = bank->target;
pic32mm.c:684pic32mm_write_dword()
struct target *target = bank->target;
pic32mm.c:702pic32mm_write()
if (bank->target->state != TARGET_HALTED) {
pic32mm.c:812pic32mm_recompute_sector_protection()
struct target *target = bank->target;
pic32mm.c:840pic32mm_probe()
struct target *target = bank->target;
pic32mm.c:891pic32mm_info()
struct target *target = bank->target;
pic32mm.c:987pic32mm_handle_pgm_word_command()
res = target_read_memory(bank->target, address, 4, 2, (uint8_t *)&read_value);
pic32mm.c:1014pic32mm_handle_unlock_command()
target = bank->target;
pic32mm.c:1069pic32mm_verify()
int retval = target_read_memory(bank->target, bank->base + aligned_offset, 4, (count + offset - aligned_offset + 3) / 4, tmp);
pic32mx.c:211pic32mx_get_flash_status()
struct target *target = bank->target;
pic32mx.c:236pic32mx_nvm_exec()
struct target *target = bank->target;
pic32mx.c:258pic32mx_protect_check()
struct target *target = bank->target;
pic32mx.c:315pic32mx_erase()
struct target *target = bank->target;
pic32mx.c:318pic32mx_erase()
if (bank->target->state != TARGET_HALTED) {
pic32mx.c:353pic32mx_protect()
struct target *target = bank->target;
pic32mx.c:435pic32mx_write_block()
struct target *target = bank->target;
pic32mx.c:588pic32mx_write_word()
struct target *target = bank->target;
pic32mx.c:605pic32mx_write()
if (bank->target->state != TARGET_HALTED) {
pic32mx.c:681pic32mx_probe()
struct target *target = bank->target;
pic32mx.c:794pic32mx_info()
struct target *target = bank->target;
pic32mx.c:877pic32mx_handle_unlock_command()
target = bank->target;
psoc4.c:219psoc4_sysreq()
struct target *target = bank->target;
psoc4.c:363psoc4_get_silicon_id()
struct target *target = bank->target;
psoc4.c:435psoc4_flash_prepare()
struct target *target = bank->target;
psoc4.c:483psoc4_protect_check()
struct target *target = bank->target;
psoc4.c:539psoc4_protect()
struct target *target = bank->target;
psoc4.c:633psoc4_write()
struct target *target = bank->target;
psoc4.c:717psoc4_probe()
struct target *target = bank->target;
psoc4.c:833get_psoc4_info()
struct target *target = bank->target;
psoc5lp.c:632psoc5lp_nvl_read()
retval = psoc5lp_spc_enable_clock(bank->target);
psoc5lp.c:637psoc5lp_nvl_read()
retval = psoc5lp_spc_read_byte(bank->target,
psoc5lp.c:667psoc5lp_nvl_write()
struct target *target = bank->target;
psoc5lp.c:765psoc5lp_nvl_probe()
if (bank->target->state != TARGET_HALTED) {
psoc5lp.c:770psoc5lp_nvl_probe()
retval = psoc5lp_find_device(bank->target, &psoc_nvl_bank->device);
psoc5lp.c:842psoc5lp_eeprom_erase()
retval = psoc5lp_spc_erase_sector(bank->target,
psoc5lp.c:854psoc5lp_eeprom_write()
struct target *target = bank->target;
psoc5lp.c:932psoc5lp_eeprom_probe()
if (bank->target->state != TARGET_HALTED) {
psoc5lp.c:937psoc5lp_eeprom_probe()
retval = psoc5lp_find_device(bank->target, &psoc_eeprom_bank->device);
psoc5lp.c:941psoc5lp_eeprom_probe()
retval = target_read_u32(bank->target, PM_ACT_CFG12, &val);
psoc5lp.c:946psoc5lp_eeprom_probe()
retval = target_write_u32(bank->target, PM_ACT_CFG12, val);
psoc5lp.c:1046psoc5lp_erase()
retval = psoc5lp_spc_erase_sector(bank->target,
psoc5lp.c:1059psoc5lp_erase_check()
struct target *target = bank->target;
psoc5lp.c:1123psoc5lp_write()
struct target *target = bank->target;
psoc5lp.c:1314psoc5lp_protect_check()
if (bank->target->state != TARGET_HALTED) {
psoc5lp.c:1320psoc5lp_protect_check()
retval = psoc5lp_spc_read_hidden_row(bank->target, i,
psoc5lp.c:1373psoc5lp_probe()
struct target *target = bank->target;
psoc5lp.c:1460psoc5lp_handle_mass_erase_command()
retval = psoc5lp_spc_erase_all(bank->target);
psoc6.c:418psoc6_protect_check()
int hr = get_silicon_id(bank->target, &psoc6_info->silicon_id, &psoc6_info->protection);
psoc6.c:493psoc6_get_info()
int hr = get_silicon_id(bank->target, &psoc6_info->silicon_id, &psoc6_info->protection);
psoc6.c:554psoc6_probe()
struct target *target = bank->target;
psoc6.c:642psoc6_erase_sector()
struct target *target = bank->target;
psoc6.c:671psoc6_erase_row()
struct target *target = bank->target;
psoc6.c:703psoc6_erase()
struct target *target = bank->target;
psoc6.c:765psoc6_program_row()
struct target *target = bank->target;
psoc6.c:822psoc6_program()
struct target *target = bank->target;
qn908x.c:393qn908x_read_page_lock()
if (bank->target->state != TARGET_HALTED) {
qn908x.c:404qn908x_read_page_lock()
int retval = target_read_memory(bank->target, bank->base + prot_offset, 4,
qn908x.c:535qn908x_erase()
retval = qn908x_setup_erase(bank->target);
qn908x.c:559qn908x_erase()
retval = target_write_u32(bank->target, QN908X_FMC_ERASE_CTRL,
qn908x.c:564qn908x_erase()
retval = qn908x_wait_for_idle(bank->target, QN908X_DEFAULT_TIMEOUT_MS);
qn908x.c:568qn908x_erase()
retval = qn908x_status_check(bank->target);
qn908x.c:581qn908x_protect()
if (bank->target->state != TARGET_HALTED) {
qn908x.c:661qn908x_protect()
retval = qn908x_load_lock_stat(bank->target);
qn908x.c:677qn908x_write()
if (bank->target->state != TARGET_HALTED) {
qn908x.c:738qn908x_write()
retval = qn908x_wait_for_idle(bank->target, QN908X_DEFAULT_TIMEOUT_MS);
qn908x.c:749qn908x_write()
retval = target_write_u32(bank->target, QN908X_FMC_SMART_CTRL, smart_ctrl);
qn908x.c:766qn908x_write()
retval = target_write_buffer(bank->target, bank->base,
qn908x.c:772qn908x_write()
retval = target_write_u32(bank->target, bank->base + QN908X_FLASH_IRQ_VECTOR_CHECKSUM_POS, checksum);
qn908x.c:776qn908x_write()
retval = target_write_buffer(bank->target,
qn908x.c:781qn908x_write()
retval = target_write_buffer(bank->target, bank->base + offset,
qn908x.c:794qn908x_write()
retval = qn908x_wait_for_idle(bank->target, QN908X_DEFAULT_TIMEOUT_MS);
qn908x.c:799qn908x_write()
retval = qn908x_status_check(bank->target);
qn908x.c:811is_flash_protected()
retval = target_read_u32(bank->target, QN908X_FMC_LOCK_STAT_8, &lock_stat);
qn908x.c:837qn908x_probe()
retval = target_read_memory(bank->target, QN908X_INFO_PAGE_CRC_START,
qn908x.c:851qn908x_probe()
retval = target_read_u32(bank->target, QN908X_INFO_PAGE_CRC32, &read_crc);
qn908x.c:878qn908x_probe()
uint32_t flash_size_fld = target_buffer_get_u32(bank->target,
qn908x.c:906qn908x_probe()
retval = qn908x_init_flash(bank->target);
qn908x.c:951qn908x_get_info()
retval = target_read_u32(bank->target, QN908X_SYSCON_CHIP_ID, &chip_id);
qn908x.c:956qn908x_get_info()
retval = target_read_u32(bank->target, QN908X_INFO_PAGE_BOOTLOADER_VER,
qn908x.c:963qn908x_get_info()
retval = target_read_memory(bank->target, QN908X_INFO_PAGE_BLUETOOTH_ADDR,
renesas_rpchf.c:384rpchf_target_write_memory()
struct target *target = bank->target;
renesas_rpchf.c:399rpchf_target_read_memory()
struct target *target = bank->target;
renesas_rpchf.c:469rpchf_spansion_write_words()
retval = rpc_hf_xfer(bank->target, address, 0, NULL, RPC_HF_SIZE_64BIT, true, word, wordcount * 2);
renesas_rpchf.c:503rpchf_write()
if (bank->target->state != TARGET_HALTED) {
renesas_rpchf.c:614rpchf_read()
struct target *target = bank->target;
renesas_rpchf.c:619rpchf_read()
if (bank->target->state != TARGET_HALTED) {
rp2040.c:155rp2040_finalize_stack_free()
struct target *target = bank->target;
rp2040.c:187rp2040_stack_grab_and_prep()
struct target *target = bank->target;
rp2040.c:219rp2040_flash_write()
struct target *target = bank->target;
rp2040.c:281rp2040_flash_erase()
struct target *target = bank->target;
rp2040.c:382rp2040_flash_probe()
struct target *target = bank->target;
rs14100.c:87rs14100_init()
struct target *target = bank->target;
rs14100.c:183rs14100_erase()
struct target *target = bank->target;
rs14100.c:418rs14100_write()
struct target *target = bank->target;
rsl10.c:142rsl10_get_probed_chip_if_halted()
if (bank->target->state != TARGET_HALTED) {
rsl10.c:165rsl10_protect_check()
int retval = target_read_u32(bank->target, RSL10_FLASH_REG_IF_STATUS, &status);
rsl10.c:204rsl10_protect()
retval = target_read_u32(bank->target, RSL10_FLASH_REG_MAIN_CTRL, &status);
rsl10.c:215rsl10_protect()
retval = target_write_u32(bank->target, RSL10_FLASH_REG_MAIN_CTRL, status);
rsl10.c:219rsl10_protect()
retval = target_write_u32(bank->target, RSL10_FLASH_REG_MAIN_WRITE_UNLOCK, RSL10_FLASH_KEY_MAIN);
rsl10.c:239rsl10_protect()
retval = target_read_u32(bank->target, RSL10_FLASH_REG_NVR_CTRL, &status);
rsl10.c:248rsl10_protect()
retval = target_write_u32(bank->target, RSL10_FLASH_REG_NVR_CTRL, status);
rsl10.c:252rsl10_protect()
retval = target_write_u32(bank->target, RSL10_FLASH_REG_NVR_WRITE_UNLOCK, RSL10_FLASH_KEY_NVR);
rsl10.c:263rsl10_check_device()
int retval = target_read_u32(bank->target, RSL10_REG_ID, &configid);
rsl10.c:607rsl10_get_chip()
if (bank_iter->target != target)
rsl10.c:638rsl10_flash_bank_command()
chip = rsl10_get_chip(bank->target);
rsl10.c:644rsl10_flash_bank_command()
chip->target = bank->target;
sh_qspi.c:101sh_qspi_init()
struct target *target = bank->target;
sh_qspi.c:193sh_qspi_cs_activate()
struct target *target = bank->target;
sh_qspi.c:248sh_qspi_cs_deactivate()
struct target *target = bank->target;
sh_qspi.c:267sh_qspi_wait_for_bit()
struct target *target = bank->target;
sh_qspi.c:297sh_qspi_xfer_common()
struct target *target = bank->target;
sh_qspi.c:444sh_qspi_erase()
struct target *target = bank->target;
sh_qspi.c:488sh_qspi_write()
struct target *target = bank->target;
sh_qspi.c:592sh_qspi_read()
struct target *target = bank->target;
sh_qspi.c:663read_flash_id()
struct target *target = bank->target;
sh_qspi.c:698sh_qspi_upload_helper()
struct target *target = bank->target;
sh_qspi.c:751sh_qspi_probe()
struct target *target = bank->target;
sim3x.c:159sim3x_init()
target = bank->target;
sim3x.c:220sim3x_erase_page()
target = bank->target;
sim3x.c:279sim3x_flash_erase()
if (bank->target->state != TARGET_HALTED) {
sim3x.c:302sim3x_flash_erase()
target = bank->target;
sim3x.c:332sim3x_write_block()
struct target *target = bank->target;
sim3x.c:472sim3x_flash_write()
target = bank->target;
sim3x.c:527sim3x_flash_lock_check()
ret = target_read_u32(bank->target, LOCK_WORD_ADDRESS, &lock_word);
sim3x.c:545sim3x_flash_protect_check()
if (bank->target->state != TARGET_HALTED) {
sim3x.c:570sim3x_flash_protect()
target = bank->target;
sim3x.c:639sim3x_read_deviceid()
ret = target_read_u32(bank->target, DEVICEID0_DEVICEID2, &device_id);
sim3x.c:648sim3x_read_deviceid()
ret = target_read_u32(bank->target, DEVICEID0_DEVICEID1, &device_id);
sim3x.c:667sim3x_read_deviceid()
ret = target_read_u32(bank->target, DEVICEID0_DEVICEID0, &device_id);
sim3x.c:739sim3x_read_info()
ret = target_read_u32(bank->target, CPUID, &cpuid);
stellaris.c:522stellaris_set_flash_timing()
struct target *target = bank->target;
stellaris.c:570stellaris_read_clock_info()
struct target *target = bank->target;
stellaris.c:653stellaris_read_part_info()
struct target *target = bank->target;
stellaris.c:783stellaris_protect_check()
struct target *target = bank->target;
stellaris.c:833stellaris_erase()
struct target *target = bank->target;
stellaris.c:835stellaris_erase()
if (bank->target->state != TARGET_HALTED) {
stellaris.c:888stellaris_protect()
struct target *target = bank->target;
stellaris.c:1022stellaris_write_block()
struct target *target = bank->target;
stellaris.c:1105stellaris_write()
struct target *target = bank->target;
stellaris.c:1113stellaris_write()
if (bank->target->state != TARGET_HALTED) {
stellaris.c:1256stellaris_mass_erase()
target = bank->target;
stellaris.c:1358stellaris_handle_recover_command()
arm = target_to_arm(bank->target);
stm32f1x.c:158stm32x_get_flash_status()
struct target *target = bank->target;
stm32f1x.c:164stm32x_wait_status_busy()
struct target *target = bank->target;
stm32f1x.c:221stm32x_read_options()
struct target *target = bank->target;
stm32f1x.c:245stm32x_erase_options()
struct target *target = bank->target;
stm32f1x.c:292stm32x_write_options()
struct target *target = bank->target;
stm32f1x.c:346stm32x_protect_check()
struct target *target = bank->target;
stm32f1x.c:369stm32x_erase()
struct target *target = bank->target;
stm32f1x.c:371stm32x_erase()
if (bank->target->state != TARGET_HALTED) {
stm32f1x.c:417stm32x_protect()
struct target *target = bank->target;
stm32f1x.c:449stm32x_write_block_async()
struct target *target = bank->target;
stm32f1x.c:546stm32x_write_block_riscv()
struct target *target = bank->target;
stm32f1x.c:653stm32x_write_block()
struct target *target = bank->target;
stm32f1x.c:695stm32x_write()
struct target *target = bank->target;
stm32f1x.c:697stm32x_write()
if (bank->target->state != TARGET_HALTED) {
stm32f1x.c:784stm32x_get_device_id()
struct target *target = bank->target;
stm32f1x.c:796stm32x_get_flash_size()
struct target *target = bank->target;
stm32f1x.c:1338stm32x_handle_lock_command()
target = bank->target;
stm32f1x.c:1379stm32x_handle_unlock_command()
target = bank->target;
stm32f1x.c:1423stm32x_handle_options_read_command()
target = bank->target;
stm32f1x.c:1490stm32x_handle_options_write_command()
target = bank->target;
stm32f1x.c:1585stm32x_handle_options_load_command()
struct target *target = bank->target;
stm32f1x.c:1616stm32x_mass_erase()
struct target *target = bank->target;
stm32f2x.c:269stm32x_get_flash_status()
struct target *target = bank->target;
stm32f2x.c:275stm32x_wait_status_busy()
struct target *target = bank->target;
stm32f2x.c:384stm32x_read_options()
struct target *target = bank->target;
stm32f2x.c:444stm32x_write_options()
struct target *target = bank->target;
stm32f2x.c:512stm32x_otp_read_protect()
struct target *target = bank->target;
stm32f2x.c:533stm32x_otp_protect()
struct target *target = bank->target;
stm32f2x.c:596stm32x_erase()
struct target *target = bank->target;
stm32f2x.c:605stm32x_erase()
if (bank->target->state != TARGET_HALTED) {
stm32f2x.c:657stm32x_protect()
struct target *target = bank->target;
stm32f2x.c:698stm32x_write_block()
struct target *target = bank->target;
stm32f2x.c:802stm32x_write()
struct target *target = bank->target;
stm32f2x.c:809stm32x_write()
if (bank->target->state != TARGET_HALTED) {
stm32f2x.c:966stm32x_get_device_id()
struct target *target = bank->target;
stm32f2x.c:984stm32x_probe()
struct target *target = bank->target;
stm32f2x.c:1438stm32x_handle_lock_command()
target = bank->target;
stm32f2x.c:1477stm32x_handle_unlock_command()
target = bank->target;
stm32f2x.c:1512stm32x_mass_erase()
struct target *target = bank->target;
stm32g0x.c:192stm32x_get_flash_status()
struct target *target = bank->target;
stm32g0x.c:198stm32x_wait_status_busy()
struct target *target = bank->target;
stm32g0x.c:241stm32x_read_options()
struct target *target = bank->target;
stm32g0x.c:284stm32x_write_options()
struct target *target = bank->target;
stm32g0x.c:344stm32x_protect_check()
struct target *target = bank->target;
stm32g0x.c:387stm32gx_erase()
struct target *target = bank->target;
stm32g0x.c:426stm32x_erase()
if (bank->target->state != TARGET_HALTED) {
stm32g0x.c:443stm32x_protect()
struct target *target = bank->target;
stm32g0x.c:468stm32x_write_block()
struct target *target = bank->target;
stm32g0x.c:562stm32gx_write()
struct target *target = bank->target;
stm32g0x.c:644stm32x_write()
if (bank->target->state != TARGET_HALTED) {
stm32g0x.c:661stm32x_get_device_id()
struct target *target = bank->target;
stm32g0x.c:688stm32x_get_flash_size()
struct target *target = bank->target;
stm32g0x.c:878stm32x_handle_lock_command()
target = bank->target;
stm32g0x.c:910stm32x_handle_unlock_command()
target = bank->target;
stm32g0x.c:944stm32x_handle_options_read_command()
target = bank->target;
stm32g0x.c:997stm32x_handle_options_write_command()
target = bank->target;
stm32g0x.c:1109stm32x_handle_options_load_command()
struct target *target = bank->target;
stm32g0x.c:1142stm32gx_mass_erase()
struct target *target = bank->target;
stm32g0x.c:1172stm32x_mass_erase()
struct target *target = bank->target;
stm32g4x.c:369stm32l4_read_flash_reg()
return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
stm32g4x.c:374stm32l4_write_flash_reg()
return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
stm32g4x.c:570stm32l4_erase()
if (bank->target->state != TARGET_HALTED) {
stm32g4x.c:620stm32l4_protect()
struct target *target = bank->target;
stm32g4x.c:658stm32l4_write_block()
struct target *target = bank->target;
stm32g4x.c:755stm32l4_write()
if (bank->target->state != TARGET_HALTED) {
stm32g4x.c:796stm32l4_read_idcode()
int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
stm32g4x.c:805stm32l4_probe()
struct target *target = bank->target;
stm32g4x.c:942stm32l4_mass_erase()
struct target *target = bank->target;
stm32g4x.c:1104stm32l4_handle_lock_command()
target = bank->target;
stm32g4x.c:1132stm32l4_handle_unlock_command()
target = bank->target;
stm32h7x.c:239stm32x_read_flash_reg()
int retval = target_read_u32(bank->target, reg_addr, value);
stm32h7x.c:250stm32x_write_flash_reg()
int retval = target_write_u32(bank->target, reg_addr, value);
stm32h7x.c:472stm32x_erase()
if (bank->target->state != TARGET_HALTED)
stm32h7x.c:522stm32x_protect()
struct target *target = bank->target;
stm32h7x.c:557stm32x_write_block()
struct target *target = bank->target;
stm32h7x.c:664stm32x_write()
struct target *target = bank->target;
stm32h7x.c:669stm32x_write()
if (bank->target->state != TARGET_HALTED) {
stm32h7x.c:743stm32x_read_id_code()
int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
stm32h7x.c:751stm32x_probe()
struct target *target = bank->target;
stm32h7x.c:961stm32x_set_rdp()
struct target *target = bank->target;
stm32h7x.c:1046stm32x_mass_erase()
struct target *target = bank->target;
stm32l4x.c:845stm32l4_read_flash_reg()
return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
stm32l4x.c:857stm32l4_write_flash_reg()
return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
stm32l4x.c:1245stm32l4_erase()
if (bank->target->state != TARGET_HALTED) {
stm32l4x.c:1403stm32l4_protect()
struct target *target = bank->target;
stm32l4x.c:1439stm32l4_write_block()
struct target *target = bank->target;
stm32l4x.c:1565stm32l4_write_block_without_loader()
struct target *target = bank->target;
stm32l4x.c:1616stm32l4_write()
if (bank->target->state != TARGET_HALTED) {
stm32l4x.c:1719stm32l4_read_idcode()
struct target *target = bank->target;
stm32l4x.c:1790stm32l4_probe()
struct target *target = bank->target;
stm32l4x.c:2206stm32l4_mass_erase()
struct target *target = bank->target;
stm32l4x.c:2441stm32l4_handle_lock_command()
target = bank->target;
stm32l4x.c:2476stm32l4_handle_unlock_command()
target = bank->target;
stm32l5x.c:231stm32l4_get_flash_status()
struct target *target = bank->target;
stm32l5x.c:238stm32l4_wait_status_busy()
struct target *target = bank->target;
stm32l5x.c:278stm32l4_unlock_reg()
struct target *target = bank->target;
stm32l5x.c:314stm32l4_unlock_option_reg()
struct target *target = bank->target;
stm32l5x.c:347stm32l4_read_option()
struct target *target = bank->target;
stm32l5x.c:353stm32l4_write_option()
struct target *target = bank->target;
stm32l5x.c:429stm32l4_erase()
struct target *target = bank->target;
stm32l5x.c:435stm32l4_erase()
if (bank->target->state != TARGET_HALTED) {
stm32l5x.c:489stm32l4_protect()
struct target *target = bank->target;
stm32l5x.c:527stm32l4_write_block()
struct target *target = bank->target;
stm32l5x.c:647stm32l4_write()
struct target *target = bank->target;
stm32l5x.c:650stm32l4_write()
if (bank->target->state != TARGET_HALTED) {
stm32l5x.c:691stm32l4_probe()
struct target *target = bank->target;
stm32l5x.c:862get_stm32l4_info()
struct target *target = bank->target;
stm32l5x.c:923stm32l4_mass_erase()
struct target *target = bank->target;
stm32l5x.c:1052stm32l4_handle_option_load_command()
struct target *target = bank->target;
stm32l5x.c:1081stm32l4_handle_lock_command()
target = bank->target;
stm32l5x.c:1109stm32l4_handle_unlock_command()
target = bank->target;
stm32lx.c:360stm32lx_protect_check()
struct target *target = bank->target;
stm32lx.c:393stm32lx_erase()
if (bank->target->state != TARGET_HALTED) {
stm32lx.c:413stm32lx_write_half_pages()
struct target *target = bank->target;
stm32lx.c:609stm32lx_write()
struct target *target = bank->target;
stm32lx.c:619stm32lx_write()
if (bank->target->state != TARGET_HALTED) {
stm32lx.c:732stm32lx_probe()
struct target *target = bank->target;
stm32lx.c:742stm32lx_probe()
int retval = stm32lx_read_id_code(bank->target, &device_id);
stm32lx.c:956stm32lx_unlock_program_memory()
struct target *target = bank->target;
stm32lx.c:1022stm32lx_enable_write_half_page()
struct target *target = bank->target;
stm32lx.c:1059stm32lx_lock_program_memory()
struct target *target = bank->target;
stm32lx.c:1093stm32lx_erase_sector()
struct target *target = bank->target;
stm32lx.c:1140stm32lx_get_flash_status()
struct target *target = bank->target;
stm32lx.c:1153stm32lx_unlock_options_bytes()
struct target *target = bank->target;
stm32lx.c:1196stm32lx_wait_until_bsy_clear_timeout()
struct target *target = bank->target;
stm32lx.c:1239stm32lx_obl_launch()
struct target *target = bank->target;
stm32lx.c:1260stm32lx_lock()
struct target *target = bank->target;
stm32lx.c:1282stm32lx_unlock()
struct target *target = bank->target;
stm32lx.c:1308stm32lx_mass_erase()
struct target *target = bank->target;
stmqspi.c:179octospi_cmd()
struct target *target = bank->target;
stmqspi.c:236poll_busy()
struct target *target = bank->target;
stmqspi.c:263stmqspi_abort()
struct target *target = bank->target;
stmqspi.c:279set_mm_mode()
struct target *target = bank->target;
stmqspi.c:325read_status_reg()
struct target *target = bank->target;
stmqspi.c:421qspi_write_enable()
struct target *target = bank->target;
stmqspi.c:506stmqspi_handle_mass_erase_command()
target = bank->target;
stmqspi.c:627stmqspi_handle_set()
target = bank->target;
stmqspi.c:796stmqspi_handle_cmd()
target = bank->target;
stmqspi.c:926qspi_erase_sector()
struct target *target = bank->target;
stmqspi.c:997stmqspi_erase()
struct target *target = bank->target;
stmqspi.c:1065stmqspi_blank_check()
struct target *target = bank->target;
stmqspi.c:1246qspi_verify()
struct target *target = bank->target;
stmqspi.c:1369qspi_read_write_block()
struct target *target = bank->target;
stmqspi.c:1572stmqspi_read()
struct target *target = bank->target;
stmqspi.c:1610stmqspi_write()
struct target *target = bank->target;
stmqspi.c:1671stmqspi_verify()
struct target *target = bank->target;
stmqspi.c:1720find_sfdp_dummy()
struct target *target = bank->target;
stmqspi.c:1812read_sfdp_block()
struct target *target = bank->target;
stmqspi.c:1938read_flash_id()
struct target *target = bank->target;
stmqspi.c:2069stmqspi_probe()
struct target *target = bank->target;
stmsmi.c:172read_status_reg()
struct target *target = bank->target;
stmsmi.c:225smi_write_enable()
struct target *target = bank->target;
stmsmi.c:272smi_erase_sector()
struct target *target = bank->target;
stmsmi.c:307stmsmi_erase()
struct target *target = bank->target;
stmsmi.c:362smi_write_buffer()
struct target *target = bank->target;
stmsmi.c:387stmsmi_write()
struct target *target = bank->target;
stmsmi.c:473read_flash_id()
struct target *target = bank->target;
stmsmi.c:512stmsmi_probe()
struct target *target = bank->target;
str7x.c:233str7x_waitbusy()
struct target *target = bank->target;
str7x.c:254str7x_result()
struct target *target = bank->target;
str7x.c:296str7x_protect_check()
struct target *target = bank->target;
str7x.c:300str7x_protect_check()
if (bank->target->state != TARGET_HALTED) {
str7x.c:324str7x_erase()
struct target *target = bank->target;
str7x.c:330str7x_erase()
if (bank->target->state != TARGET_HALTED) {
str7x.c:375str7x_protect()
struct target *target = bank->target;
str7x.c:379str7x_protect()
if (bank->target->state != TARGET_HALTED) {
str7x.c:432str7x_write_block()
struct target *target = bank->target;
str7x.c:548str7x_write()
struct target *target = bank->target;
str7x.c:557str7x_write()
if (bank->target->state != TARGET_HALTED) {
str7x.c:722str7x_handle_disable_jtag_command()
target = bank->target;
str9x.c:154str9x_protect_check()
struct target *target = bank->target;
str9x.c:160str9x_protect_check()
if (bank->target->state != TARGET_HALTED) {
str9x.c:215str9x_erase()
struct target *target = bank->target;
str9x.c:221str9x_erase()
if (bank->target->state != TARGET_HALTED) {
str9x.c:298str9x_protect()
struct target *target = bank->target;
str9x.c:302str9x_protect()
if (bank->target->state != TARGET_HALTED) {
str9x.c:334str9x_write_block()
struct target *target = bank->target;
str9x.c:446str9x_write()
struct target *target = bank->target;
str9x.c:456str9x_write()
if (bank->target->state != TARGET_HALTED) {
str9x.c:609str9x_handle_flash_config_command()
target = bank->target;
str9x.c:611str9x_handle_flash_config_command()
if (bank->target->state != TARGET_HALTED) {
str9xpec.c:280str9xpec_flash_bank_command()
arm = bank->target->arch_info;
swm050.c:33swm050_erase()
struct target *target = bank->target;
swm050.c:65swm050_write()
struct target *target = bank->target;
swm050.c:98swm050_mass_erase()
struct target *target = bank->target;
tcl.c:1287handle_flash_bank_command()
c->target = target;
tcl.c:1346handle_flash_list()
target_name(p->target));
tms470.c:112tms470_read_part_info()
struct target *target = bank->target;
tms470.c:456tms470_unlock_flash()
struct target *target = bank->target;
tms470.c:491tms470_flash_initialize_internal_state_machine()
struct target *target = bank->target;
tms470.c:623tms470_flash_status()
struct target *target = bank->target;
tms470.c:673tms470_erase_sector()
struct target *target = bank->target;
tms470.c:794tms470_erase()
if (bank->target->state != TARGET_HALTED) {
tms470.c:832tms470_protect()
struct target *target = bank->target;
tms470.c:878tms470_write()
struct target *target = bank->target;
tms470.c:969tms470_probe()
if (bank->target->state != TARGET_HALTED) {
tms470.c:990tms470_erase_check()
struct target *target = bank->target;
tms470.c:1065tms470_protect_check()
struct target *target = bank->target;
tms470.c:1121get_tms470_info()
tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
w600.c:126w600_start_do()
struct target *target = bank->target;
w600.c:201w600_erase()
if (bank->target->state != TARGET_HALTED) {
w600.c:223w600_write()
struct target *target = bank->target;
w600.c:226w600_write()
if (bank->target->state != TARGET_HALTED) {
w600.c:263w600_get_flash_id()
struct target *target = bank->target;
xcf.c:89product_name()
switch (bank->target->tap->idcode & ID_MEANINGFUL_MASK) {
xcf.c:130read_status()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:157isc_enter()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:186isc_leave()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:226isc_read_register()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_DRSHIFT);
xcf.c:231isc_read_register()
jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IDLE);
xcf.c:265isc_set_register()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_DRSHIFT);
xcf.c:270isc_set_register()
jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IDLE);
xcf.c:291isc_program_register()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_DRSHIFT);
xcf.c:296isc_program_register()
jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IRSHIFT);
xcf.c:301isc_program_register()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:360isc_data_read_out()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:365isc_data_read_out()
jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IDLE);
xcf.c:547fpga_configure()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:594xcf_probe()
if (!bank->target->tap) {
xcf.c:600xcf_probe()
if (!bank->target->tap->has_idcode)
xcf.c:604xcf_probe()
id = bank->target->tap->idcode;
xcf.c:632xcf_probe()
LOG_INFO("device id = 0x%" PRIX32, bank->target->tap->idcode);
xcf.c:678xcf_erase_check()
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
xcf.c:684xcf_erase_check()
jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IDLE);
xmc1xxx.c:83xmc1xxx_erase()
struct target *target = bank->target;
xmc1xxx.c:95xmc1xxx_erase()
if (bank->target->state != TARGET_HALTED) {
xmc1xxx.c:157xmc1xxx_erase_check()
struct target *target = bank->target;
xmc1xxx.c:168xmc1xxx_erase_check()
if (bank->target->state != TARGET_HALTED) {
xmc1xxx.c:243xmc1xxx_write()
struct target *target = bank->target;
xmc1xxx.c:384xmc1xxx_protect_check()
if (bank->target->state != TARGET_HALTED) {
xmc1xxx.c:389xmc1xxx_protect_check()
retval = target_read_u32(bank->target, NVMCONF, &nvmconf);
xmc1xxx.c:409xmc1xxx_get_info_command()
if (bank->target->state != TARGET_HALTED) {
xmc1xxx.c:416xmc1xxx_get_info_command()
retval = target_read_u32(bank->target, FLASH_CS0 + i * 4, &chipid[i]);
xmc1xxx.c:423xmc1xxx_get_info_command()
retval = target_read_u32(bank->target, SCU_BASE + 0x000, &chipid[7]);
xmc1xxx.c:451xmc1xxx_probe()
if (bank->target->state != TARGET_HALTED) {
xmc1xxx.c:456xmc1xxx_probe()
retval = target_read_u32(bank->target, SCU_IDCHIP, &idchip);
xmc1xxx.c:469xmc1xxx_probe()
retval = target_read_u32(bank->target, PAU_FLSIZE, &flsize);
xmc4xxx.c:257xmc4xxx_write_command_sequence()
res = target_write_u32(bank->target, seq[i].address,
xmc4xxx.c:330xmc4xxx_probe()
if (bank->target->state != TARGET_HALTED) {
xmc4xxx.c:336xmc4xxx_probe()
res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
xmc4xxx.c:351xmc4xxx_probe()
res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
xmc4xxx.c:417xmc4xxx_clear_flash_status()
res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
xmc4xxx.c:431xmc4xxx_get_flash_status()
res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
xmc4xxx.c:506xmc4xxx_erase_sector()
res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
xmc4xxx.c:536xmc4xxx_erase()
if (bank->target->state != TARGET_HALTED) {
xmc4xxx.c:582xmc4xxx_enter_page_mode()
res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
xmc4xxx.c:653xmc4xxx_write_page()
uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
xmc4xxx.c:654xmc4xxx_write_page()
uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
xmc4xxx.c:659xmc4xxx_write_page()
res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
xmc4xxx.c:663xmc4xxx_write_page()
res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
xmc4xxx.c:718xmc4xxx_write()
if (bank->target->state != TARGET_HALTED) {
xmc4xxx.c:800xmc4xxx_get_info_command()
if (bank->target->state != TARGET_HALTED) {
xmc4xxx.c:806xmc4xxx_get_info_command()
int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
xmc4xxx.c:1087xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
xmc4xxx.c:1088xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
xmc4xxx.c:1093xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
xmc4xxx.c:1094xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
xmc4xxx.c:1095xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
xmc4xxx.c:1096xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
xmc4xxx.c:1101xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
xmc4xxx.c:1102xmc4xxx_flash_protect()
target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
xmc4xxx.c:1163xmc4xxx_protect_check()
ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
xmc4xxx.c:1169xmc4xxx_protect_check()
ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
xmc4xxx.c:1175xmc4xxx_protect_check()
ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);

Data Use

Functions writing flash_bank::target
Functions reading flash_bank::target
all items filtered out
flash_bank::target
all items filtered out
Type of flash_bank::target
flash_bank::target
all items filtered out