OpenOCD
target_read_u32() is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDtarget_read_u32()

target_read_u32() function

Syntax

int target_read_u32(struct target *target,     target_addr_t address,     uint32_t *value);
Implemented in target.c:2560

Arguments

target

address

value

References

LocationReferrerText
target.c:2560
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value)
target.h:768
int target_read_u32(struct target *target, target_addr_t address, uint32_t *value);
FreeRTOS.c:155freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:172freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:186freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:237freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:282freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:299freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:314freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:370freertos_update_threads()
retval = target_read_u32(rtos->target,
FreeRTOS.c:408freertos_get_thread_reg_list()
retval = target_read_u32(rtos->target,
FreeRTOS.c:429freertos_get_thread_reg_list()
retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr);
FreeRTOS.c:446freertos_get_thread_reg_list()
retval = target_read_u32(rtos->target,
aducm302x.c:164aducm302x_probe()
target_read_u32(target, TIME_PARAM0, &time_param0);
aducm302x.c:193aducm302x_check_cmdfail()
target_read_u32(target, STAT, &flash_stat);
aducm302x.c:299aducm302x_protect()
target_read_u32(target, WRPROT, &wrprot);
aducm302x.c:328aducm302x_protect_check()
target_read_u32(target, WRPROT, &wrprot);
aducm302x.c:458aducm302x_write()
target_read_u32(target, ECC_CFG, &ecc_cfg);
aducm360.c:100aducm360_mass_erase()
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
aducm360.c:129aducm360_page_erase()
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
aducm360.c:454aducm360_write_modified()
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
aducm360.c:462aducm360_write_modified()
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEESTA, &value);
aducm360.c:507aducm360_set_write_enable()
target_read_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEECON0, &value);
aducm360.c:529aducm360_check_flash_completion()
target_read_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEESTA, &v);
ambiqmicro.c:179ambiqmicro_read_part_info()
retval = target_read_u32(target, 0x40020000, &part_num);
ambiqmicro.c:268check_flash_status()
rc = target_read_u32(target, address, &retflash);
arm7_9_common.c:234arm7_9_set_breakpoint()
retval = target_read_u32(target, breakpoint->address, &verify);
arm7_9_common.c:1745arm7_9_resume()
target_read_u32(target, current_pc, &current_opcode);
arm7_9_common.c:1937arm7_9_step()
target_read_u32(target, current_pc, &current_opcode);
arm_semihosting.c:297arm_semihosting()
*retval = target_read_u32(target, pc64, &insn);
arm_semihosting.c:312arm_semihosting()
*retval = target_read_u32(target, pc, &insn);
arm_simulator.c:240arm_simulate_step_core()
retval = target_read_u32(target, current_pc, &opcode);
arm_simulator.c:471arm_simulate_step_core()
retval = target_read_u32(target, load_address, &load_value);
arm_simulator.c:530arm_simulate_step_core()
target_read_u32(target, rn, &load_values[i]);
arm_tpiu_swo.c:586wrap_read_u32()
return target_read_u32(target, address, value);
armv7m_trace.c:34armv7m_trace_itm_config()
retval = target_read_u32(target, ITM_TCR, &itm_tcr);
armv7m_trace.c:46armv7m_trace_itm_config()
retval = target_read_u32(target, ITM_TCR, &itm_tcr);
at91sam3.c:2001efc_get_status()
r = target_read_u32(private->chip->target,
at91sam3.c:2022efc_get_result()
r = target_read_u32(private->chip->target,
at91sam3.c:2187flashd_read_uid()
r = target_read_u32(private->chip->target,
at91sam3.c:2868sam3_read_this_reg()
r = target_read_u32(chip->target, reg->address, goes_here);
at91sam3.c:3297sam3_page_write()
r = target_read_u32(private->chip->target, private->controller_address, &fmr);
at91sam4.c:1451efc_get_status()
r = target_read_u32(private->chip->target,
at91sam4.c:1472efc_get_result()
r = target_read_u32(private->chip->target,
at91sam4.c:1637flashd_read_uid()
r = target_read_u32(private->chip->target,
at91sam4.c:2375sam4_read_this_reg()
r = target_read_u32(chip->target, reg->address, goes_here);
at91sam4.c:2824sam4_set_wait()
r = target_read_u32(private->chip->target, private->controller_address, &fmr);
at91sam4l.c:133sam4l_flash_wait_until_ready()
res = target_read_u32(target, SAM4L_FLASHCALW + SAM4L_FSR, &st);
at91sam4l.c:144sam4l_flash_check_error()
res = target_read_u32(target, SAM4L_FLASHCALW + SAM4L_FSR, &st);
at91sam4l.c:168sam4l_flash_command()
res = target_read_u32(target, SAM4L_FLASHCALW + SAM4L_FCMD, &fcmd);
at91sam4l.c:246sam4l_check_page_erased()
res = target_read_u32(bank->target, SAM4L_FLASHCALW + SAM4L_FSR, &st);
at91sam4l.c:267sam4l_probe()
res = target_read_u32(bank->target, SAM4L_CHIPID + SAM4L_CIDR, &id);
at91sam4l.c:273sam4l_probe()
res = target_read_u32(bank->target, SAM4L_CHIPID + SAM4L_EXID, &exid);
at91sam4l.c:301sam4l_probe()
res = target_read_u32(bank->target, SAM4L_FLASHCALW + SAM4L_FPR, &param);
at91sam4l.c:363sam4l_protect_check()
res = target_read_u32(bank->target, SAM4L_FLASHCALW + SAM4L_FSR, &st);
at91sam7.c:171at91sam7_get_flash_status()
target_read_u32(target, mc_fsr[bank_number], &fsr);
at91sam7.c:185at91sam7_read_clock_info()
target_read_u32(target, CKGR_MOR, &mor);
at91sam7.c:187at91sam7_read_clock_info()
target_read_u32(target, CKGR_MCFR, &mcfr);
at91sam7.c:189at91sam7_read_clock_info()
target_read_u32(target, PMC_MCKR, &mckr);
at91sam7.c:191at91sam7_read_clock_info()
target_read_u32(target, CKGR_PLLR, &pllr);
at91sam7.c:218at91sam7_read_clock_info()
target_read_u32(target, CKGR_PLLR, &pllr);
at91sam7.c:380at91sam7_read_part_info()
target_read_u32(target, DBGU_CIDR, &cidr);
at91sam9.c:229at91sam9_nand_ready()
target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);
at91sam9.c:376at91sam9_read_page()
target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
at91sam9.c:385at91sam9_read_page()
target_read_u32(target,
at91sam9.c:454at91sam9_write_page()
target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
at91sam9.c:455at91sam9_write_page()
target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
at91samd.c:421samd_get_flash_page_info()
res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
at91samd.c:447samd_probe()
res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
at91samd.c:622samd_get_reservedmask()
res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
at91samd.c:712samd_modify_user_row_masked()
res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
at91samd.c:852samd_write()
res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
atsame5.c:232same5_protect_check()
res = target_read_u32(bank->target,
atsame5.c:250samd_get_flash_page_info()
res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
atsame5.c:276same5_probe()
res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
atsame5.c:457same5_pre_write_check()
res = target_read_u32(target, SAMD_NVMCTRL + SAME5_NVMCTRL_CTRLA, &nvm_ctrla);
atsame5.c:848same5_handle_bootloader_command()
int res2 = target_read_u32(target, SAMD_USER_ROW, &val);
atsamv.c:71samv_efc_get_status()
int r = target_read_u32(target, SAMV_CONTROLLER_ADDR + OFFSET_EFC_FSR, v);
atsamv.c:78samv_efc_get_result()
int r = target_read_u32(target, SAMV_CONTROLLER_ADDR + OFFSET_EFC_FRR, &rv);
atsamv.c:304samv_get_device_id()
return target_read_u32(bank->target, SAMV_CHIPID_CIDR, device_id);
bluenrg-x.c:125bluenrgx_read_flash_reg()
return target_read_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value);
bluenrg-x.c:359bluenrgx_write()
retval = target_read_u32(target, source->address+4, &rp);
bluenrg-x.c:385bluenrgx_probe()
int retval = target_read_u32(bank->target, BLUENRGLP_JTAG_REG, &idcode);
bluenrg-x.c:391bluenrgx_probe()
retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode);
bluenrg-x.c:412bluenrgx_probe()
retval = target_read_u32(bank->target, DIE_ID_REG(bluenrgx_info), &die_id);
cc26xx.c:110cc26xx_wait_algo_done()
retval = target_read_u32(target, status_addr, &status);
cc26xx.c:413cc26xx_probe()
retval = target_read_u32(target, FCFG1_ICEPICK_ID, &value);
cc26xx.c:418cc26xx_probe()
retval = target_read_u32(target, FCFG1_USER_ID, &value);
cc26xx.c:457cc26xx_probe()
retval = target_read_u32(target, CC26XX_FLASH_SIZE_INFO, &value);
cc3220sf.c:59cc3220sf_mass_erase()
retval = target_read_u32(target, FMC_REGISTER_ADDR, &value);
cc3220sf.c:146cc3220sf_erase()
retval = target_read_u32(target, FMC_REGISTER_ADDR, &value);
chibios.c:239chibios_update_stacking()
retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr);
chibios.c:304chibios_update_threads()
retval = target_read_u32(rtos->target,
chibios.c:319chibios_update_threads()
retval = target_read_u32(rtos->target,
chibios.c:374chibios_update_threads()
retval = target_read_u32(rtos->target,
chibios.c:389chibios_update_threads()
retval = target_read_u32(rtos->target,
chibios.c:441chibios_update_threads()
retval = target_read_u32(rtos->target,
chibios.c:477chibios_get_thread_reg_list()
retval = target_read_u32(rtos->target,
chromium-ec.c:148chromium_ec_get_current_task_ptr()
return target_read_u32(rtos->target,
chromium-ec.c:158chromium_ec_get_num_tasks()
ret = target_read_u32(rtos->target,
chromium-ec.c:219chromium_ec_update_threads()
ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_START_CALLED].address,
chromium-ec.c:247chromium_ec_update_threads()
ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_TASKS_ENABLED].address,
chromium-ec.c:255chromium_ec_update_threads()
ret = target_read_u32(rtos->target, rtos->symbols[CHROMIUM_EC_VAL_TASKS_READY].address,
chromium-ec.c:273chromium_ec_update_threads()
ret = target_read_u32(rtos->target,
chromium-ec.c:298chromium_ec_update_threads()
ret = target_read_u32(rtos->target,
chromium-ec.c:353chromium_ec_get_thread_reg_list()
ret = target_read_u32(rtos->target,
cortex_m.c:595cortex_m_enable_fpb()
retval = target_read_u32(target, FP_CTRL, &fpctrl);
cortex_m.c:2366cortex_m_hit_watchpoint()
int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
cortex_m.c:2453cortex_m_profiling()
retval = target_read_u32(target, DWT_PCSR, &reg_value);
cortex_m.c:2491cortex_m_profiling()
target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
cortex_m.c:2528cortex_m_dwt_get_reg()
int retval = target_read_u32(state->target, state->addr, &tmp);
cortex_m.c:2613cortex_m_dwt_setup()
target_read_u32(target, DWT_CTRL, &dwtcr);
cortex_m.c:2620cortex_m_dwt_setup()
target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
cortex_m.c:2708cortex_m_has_tz()
int retval = target_read_u32(target, DAUTHSTATUS, &dauthstatus);
cortex_m.c:2776cortex_m_examine()
retval = target_read_u32(target, CPUID, &cpuid);
cortex_m.c:2824cortex_m_examine()
target_read_u32(target, MVFR0, &mvfr0);
cortex_m.c:2833cortex_m_examine()
target_read_u32(target, MVFR0, &mvfr0);
cortex_m.c:2834cortex_m_examine()
target_read_u32(target, MVFR1, &mvfr1);
cortex_m.c:2876cortex_m_examine()
retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
cortex_m.c:2916cortex_m_examine()
target_read_u32(target, FP_CTRL, &fpcr);
davinci.c:79davinci_init()
target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
davinci.c:109davinci_nand_ready()
target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
davinci.c:182davinci_read_block_data()
target_read_u32(target, nfdata, &tmp);
davinci.c:408davinci_write_page_ecc1()
target_read_u32(target, ecc1_addr, &ecc1);
davinci.c:410davinci_write_page_ecc1()
target_read_u32(target, fcr_addr, &fcr);
davinci.c:425davinci_write_page_ecc1()
target_read_u32(target, ecc1_addr, &ecc1);
davinci.c:499davinci_write_page_ecc4()
target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
davinci.c:501davinci_write_page_ecc4()
target_read_u32(target, fcr_addr, &fcr);
davinci.c:519davinci_write_page_ecc4()
target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
davinci.c:560davinci_write_page_ecc4infix()
target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
davinci.c:562davinci_write_page_ecc4infix()
target_read_u32(target, fcr_addr, &fcr);
davinci.c:581davinci_write_page_ecc4infix()
target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
efm32.c:234efm32x_read_reg_u32()
return target_read_u32(bank->target, base + offset, value);
efm32.c:553efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
efm32.c:564efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
efm32.c:572efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
efm32.c:580efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
efm32.c:588efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
efm32.c:596efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
efm32.c:604efm32x_read_lock_data()
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
em357.c:104em357_get_flash_status()
return target_read_u32(target, EM357_FLASH_SR, status);
em357.c:157em357_read_options()
int retval = target_read_u32(target, EM357_FLASH_OBR, &optiondata);
em357.c:168em357_read_options()
retval = target_read_u32(target, EM357_FLASH_WRPR, &optiondata);
em357.c:316em357_protect_check()
int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
em357.c:414em357_protect()
int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
eneispif.c:79eneispif_read_reg()
int result = target_read_u32(target, eneispif_info->ctrl_base + address, value);
esirisc_flash.c:142esirisc_flash_disable_protect()
target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
esirisc_flash.c:161esirisc_flash_enable_protect()
target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
esirisc_flash.c:180esirisc_flash_check_status()
target_read_u32(target, esirisc_info->cfg + STATUS, &status);
esirisc_flash.c:208esirisc_flash_wait()
target_read_u32(target, esirisc_info->cfg + STATUS, &status);
esp32s2.c:121esp32s2_set_peri_reg_mask()
int res = target_read_u32(target, addr, &reg_val);
esp32s2.c:346esp32s2_disable_wdts()
res = target_read_u32(target, ESP32_S2_SWD_CONF_REG, &swd_conf_reg);
esp32s3.c:260esp32s3_disable_wdts()
res = target_read_u32(target, ESP32_S3_SWD_CONF_REG, &swd_conf_reg);
esp_algorithm.c:25esp_algorithm_read_stub_logs()
int retval = target_read_u32(target, stub->log_buff_addr, &len);
fespi.c:165fespi_read_reg()
int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
fm3.c:274fm3_erase()
retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
fm3.c:332fm3_erase()
retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */
fm3.c:882fm3_chip_erase()
retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
fm3.c:928fm3_chip_erase()
retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */
fm4.c:80fm4_enter_flash_cpu_programming_mode()
retval = target_read_u32(target, FASZR, &u32_value);
fm4.c:96fm4_enter_flash_cpu_rom_mode()
retval = target_read_u32(target, FASZR, &u32_value);
fm4.c:415s6e2cc_probe()
retval = target_read_u32(target, DFCTRLR, &u32_value);
hla_target.c:238adapter_debug_entry()
retval = target_read_u32(target, DCB_DCRDR, &target->SAVED_DCRDR);
kinetis.c:1145kinetis_disable_wdog32()
retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
kinetis.c:1158kinetis_disable_wdog32()
retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
kinetis.c:1426kinetis_protect_check()
result = target_read_u32(bank->target, FTFX_FPROT3, &fprot);
kinetis.c:1581kinetis_read_pmstat()
result = target_read_u32(target, SMC32_PMSTAT, &stat32);
kinetis.c:2116kinetis_probe_chip_s32k()
result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
kinetis.c:2215kinetis_probe_chip_s32k()
result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
kinetis.c:2291kinetis_probe_chip()
result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
kinetis.c:2293kinetis_probe_chip()
result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
kinetis.c:2297kinetis_probe_chip()
result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
kinetis.c:2421kinetis_probe_chip()
result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
kinetis.c:2715kinetis_probe_chip()
result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
kinetis.c:2719kinetis_probe_chip()
result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
kinetis.c:3178kinetis_nvm_partition()
result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
kinetis_ke.c:1045kinetis_ke_probe()
result = target_read_u32(target, SIM_SRSID, &kinfo->sim_srsid);
lpc2000.c:757lpc2000_iap_call()
target_read_u32(target, 0x10400100, &iap_entry_point);
lpc288x.c:100lpc288x_wait_status_busy()
target_read_u32(target, F_STAT, &status);
lpc288x.c:125lpc288x_read_part_info()
target_read_u32(target, DBGU_CIDR, &cidr);
lpc2900.c:190lpc2900_wait_status()
target_read_u32(target, INT_STATUS, &int_status);
lpc2900.c:1379lpc2900_probe()
target_read_u32(target, CHIPID, &lpc2900_info->chipid);
lpc2900.c:1388lpc2900_probe()
target_read_u32(target, FEAT0, &feat0);
lpc2900.c:1389lpc2900_probe()
target_read_u32(target, FEAT1, &feat1);
lpc2900.c:1390lpc2900_probe()
target_read_u32(target, FEAT2, &feat2);
lpc2900.c:1391lpc2900_probe()
target_read_u32(target, FEAT3, &feat3);
lpc3180.c:96lpc3180_cycle_time()
target_read_u32(target, 0x40004050, &sysclk_ctrl);
lpc3180.c:104lpc3180_cycle_time()
target_read_u32(target, 0x40004044, &pwr_ctrl);
lpc3180.c:109lpc3180_cycle_time()
target_read_u32(target, 0x40004058, &hclkpll_ctrl);
lpc3180.c:112lpc3180_cycle_time()
target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
lpc3180.c:395lpc3180_read_data()
target_read_u32(target, 0x20020000, &data32);
lpc3180.c:889lpc3180_read_page()
target_read_u32(target, 0x200b8048, &mlc_isr);
lpc3180.c:1178lpc3180_controller_ready()
target_read_u32(target, 0x20020018, &status);
lpc3180.c:1221lpc3180_nand_ready()
target_read_u32(target, 0x20020018, &status);
lpc3180.c:1253lpc3180_tc_ready()
target_read_u32(target, 0x2002001c, &status);
lpc32xx.c:130lpc32xx_cycle_time()
retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
lpc32xx.c:142lpc32xx_cycle_time()
retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
lpc32xx.c:151lpc32xx_cycle_time()
retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
lpc32xx.c:158lpc32xx_cycle_time()
retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
lpc32xx.c:559lpc32xx_read_data()
retval = target_read_u32(target, 0x20020000, &data32);
lpc32xx.c:963lpc32xx_dma_ready()
retval = target_read_u32(target, 0x31000014, &tc_stat);
lpc32xx.c:969lpc32xx_dma_ready()
retval = target_read_u32(target, 0x31000018, &err_stat);
lpc32xx.c:1381lpc32xx_read_page_mlc()
retval = target_read_u32(target, 0x200b8048, &mlc_isr);
lpc32xx.c:1637lpc32xx_controller_ready()
retval = target_read_u32(target, 0x20020018, &status);
lpc32xx.c:1691lpc32xx_nand_ready()
retval = target_read_u32(target, 0x20020018, &status);
lpc32xx.c:1720lpc32xx_tc_ready()
retval = target_read_u32(target, 0x2002001c, &status);
lpcspifi.c:86ssp_read_reg()
return target_read_u32(target, ssp_base + offset, value);
max32xxx.c:129max32xxx_flash_op_pre()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:138max32xxx_flash_op_pre()
target_read_u32(target, info->flc_base + FLSH_INT, &info->int_state);
max32xxx.c:142max32xxx_flash_op_pre()
if (target_read_u32(target, info->flc_base + FLSH_BL_CTRL, &bootloader) != ERROR_OK) {
max32xxx.c:155max32xxx_flash_op_pre()
if (target_read_u32(target, info->flc_base + FLSH_BL_CTRL, &bootloader) != ERROR_OK) {
max32xxx.c:172max32xxx_flash_op_pre()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:189max32xxx_flash_op_post()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:214max32xxx_protect_check()
target_read_u32(target, info->flc_base + FLSH_PROT + ((i/32)*4), &temp_reg);
max32xxx.c:267max32xxx_erase()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:278max32xxx_erase()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:288max32xxx_erase()
target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int);
max32xxx.c:334max32xxx_protect()
target_read_u32(target, info->flc_base + FLSH_PROT + (page/32), &temp_reg);
max32xxx.c:340max32xxx_protect()
target_read_u32(target, info->flc_base + FLSH_PROT + (page/32), &temp_reg);
max32xxx.c:466max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:492max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:506max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:522max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:540max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:557max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:571max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:587max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:609max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:619max32xxx_write()
target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int);
max32xxx.c:655max32xxx_probe()
target_read_u32(target, ARM_PID_REG, &arm_id[0]);
max32xxx.c:656max32xxx_probe()
target_read_u32(target, ARM_PID_REG+4, &arm_id[1]);
max32xxx.c:662max32xxx_probe()
target_read_u32(target, MAX326XX_ID_REG, &max326xx_id);
max32xxx.c:716max32xxx_mass_erase()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:727max32xxx_mass_erase()
target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn);
max32xxx.c:736max32xxx_mass_erase()
target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int);
mdr.c:86mdr_mass_erase()
retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
mdr.c:130mdr_erase()
retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
mdr.c:147mdr_erase()
retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
mdr.c:332mdr_write()
retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
mdr.c:351mdr_write()
retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
mdr.c:488mdr_read()
retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
mdr.c:507mdr_read()
retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
mdr.c:528mdr_read()
retval = target_read_u32(target, FLASH_DO, &buf);
mips32.c:737mips32_configure_ibs()
retval = target_read_u32(target, ejtag_info->ejtag_ibs_addr, &bpinfo);
mips32.c:764mips32_configure_dbs()
retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &bpinfo);
mips32.c:795mips32_configure_break_unit()
retval = target_read_u32(target, EJTAG_DCR, &dcr);
mips32.c:846mips32_enable_interrupts()
retval = target_read_u32(target, EJTAG_DCR, &dcr);
mips32.c:1186mips32_read_config_regs()
retval = target_read_u32(target, EJTAG_DCR, &dcr);
mips32.c:2289mips32_handle_ejtag_reg_command()
retval = target_read_u32(target, EJTAG_DCR, &dcr);
mips_m4k.c:53mips_m4k_examine_debug_reason()
retval = target_read_u32(target,
mips_m4k.c:69mips_m4k_examine_debug_reason()
retval = target_read_u32(target,
mips_m4k.c:665mips_m4k_set_breakpoint()
retval = target_read_u32(target, bpaddr, &verify);
mips_mips64.c:294mips_mips64_set_sdbbp()
retval = target_read_u32(target, bp->address, &verify);
mrvlqspi.c:111mrvlqspi_set_conf()
retval = target_read_u32(target,
mrvlqspi.c:129mrvlqspi_set_ss_state()
retval = target_read_u32(target,
mrvlqspi.c:146mrvlqspi_set_ss_state()
retval = target_read_u32(target,
mrvlqspi.c:172mrvlqspi_start_transfer()
retval = target_read_u32(target,
mrvlqspi.c:201mrvlqspi_stop_transfer()
retval = target_read_u32(target,
mrvlqspi.c:216mrvlqspi_stop_transfer()
retval = target_read_u32(target,
mrvlqspi.c:230mrvlqspi_stop_transfer()
retval = target_read_u32(target,
mrvlqspi.c:257mrvlqspi_fifo_flush()
retval = target_read_u32(target,
mrvlqspi.c:271mrvlqspi_fifo_flush()
retval = target_read_u32(target,
mrvlqspi.c:295mrvlqspi_read_byte()
retval = target_read_u32(target,
mrvlqspi.c:305mrvlqspi_read_byte()
retval = target_read_u32(target,
msp432.c:217msp432_wait_return_code()
retval = target_read_u32(target, ALGO_RETURN_CODE_ADDR, &return_code);
msp432.c:259msp432_wait_inactive()
retval = target_read_u32(target, status_addr, &status_code);
msp432.c:833msp432_probe()
retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size);
msp432.c:841msp432_probe()
retval = target_read_u32(target, E4_DID0_REG, &device_id);
msp432.c:847msp432_probe()
retval = target_read_u32(target, E4_DID1_REG, &hardware_rev);
msp432.c:856msp432_probe()
retval = target_read_u32(target, P4_DEVICE_ID_REG, &device_id);
msp432.c:862msp432_probe()
retval = target_read_u32(target, P4_HARDWARE_REV_REG, &hardware_rev);
msp432.c:875msp432_probe()
retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size);
msp432.c:885msp432_probe()
retval = target_read_u32(target, P4_FLASH_INFO_SIZE_REG, &size);
msp432p4.c:236msp432p4_init()
retval = target_read_u32(target, DDDS_DEV_ID, &reg_value);
msp432p4.c:244msp432p4_init()
retval = target_read_u32(target, RETURN_CODE, &reg_value);
msp432p4.c:275msp432p4_mass_erase()
retval = target_read_u32(target, RETURN_CODE, &reg_value);
msp432p4.c:306msp432p4_sector_erase()
retval = target_read_u32(target, RETURN_CODE, &reg_value);
msp432p4.c:502msp432p4_write()
retval = target_read_u32(target, RETURN_CODE, &reg_value);
msp432p4.c:526msp432p4_probe()
retval = target_read_u32(target, CPU_TYPE, &cpu_id);
msp432p4.c:533msp432p4_probe()
retval = target_read_u32(target, FLASH_SIZE_REG, &reg_value);
mx3.c:108imx31_init()
target_read_u32(target, MX3_PCSR, &pcsr_register_content);
mx3.c:130imx31_init()
target_read_u32(target, MX3_CCM_CGR2, &cgr_register_content);
mx3.c:139imx31_init()
target_read_u32(target, MX3_GPR, &gpr_register_content);
mx3.c:509test_iomux_settings()
target_read_u32(target, address, &register_content);
mxc.c:231mxc_init()
target_read_u32(target, sreg, &sreg_content);
niietcm4.c:149niietcm4_opstatus_check()
retval = target_read_u32(target, FCIS, &flash_status);
niietcm4.c:154niietcm4_opstatus_check()
retval = target_read_u32(target, FCIS, &flash_status);
niietcm4.c:186niietcm4_uopstatus_check()
retval = target_read_u32(target, UFCIS, &uflash_status);
niietcm4.c:191niietcm4_uopstatus_check()
retval = target_read_u32(target, UFCIS, &uflash_status);
niietcm4.c:244niietcm4_dump_uflash_page()
retval = target_read_u32(target, UFMD, &dump[i]);
niietcm4.c:415niietcm4_handle_uflash_read_byte_command()
retval = target_read_u32(target, UFMD, &uflash_data);
niietcm4.c:609niietcm4_handle_uflash_protect_check_command()
retval = target_read_u32(target, UFMD, &uflash_data);
niietcm4.c:632niietcm4_handle_uflash_protect_check_command()
retval = target_read_u32(target, UFMD, &uflash_data);
niietcm4.c:902niietcm4_handle_service_mode_erase_command()
retval = target_read_u32(target, SERVICE_MODE_ERASE_ADDR, &status);
niietcm4.c:907niietcm4_handle_service_mode_erase_command()
retval = target_read_u32(target, SERVICE_MODE_ERASE_ADDR, &status);
niietcm4.c:1092niietcm4_protect_check()
retval = target_read_u32(target, UFMD, &uflash_data);
niietcm4.c:1116niietcm4_protect_check()
retval = target_read_u32(target, UFMD, &uflash_data);
niietcm4.c:1473niietcm4_probe_k1921vk01t()
retval = target_read_u32(target, 0x80017000, &service_mode);
niietcm4.c:1498niietcm4_probe_k1921vk01t()
retval = target_read_u32(target, UFMD, &uflash_data[i]);
niietcm4.c:1543niietcm4_probe_k1921vk01t()
retval = target_read_u32(target, 0x80010000 + 0x1000*portnum, &extmem_boot_port_data);
niietcm4.c:1675niietcm4_probe()
retval = target_read_u32(target, CHIPID_ADDR, &chipid);
npcx.c:160npcx_wait_algo_done()
int retval = target_read_u32(target, status_addr, &status);
npcx.c:215npcx_get_flash_id()
target_read_u32(target, NPCX_FLASH_LOADER_BUFFER_ADDR, flash_id);
nrf5.c:366nrf5_nvmc_read_u32()
return target_read_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
nrf5.c:482nrf51_protect_check_clenr0()
res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
nrf5.c:490nrf51_protect_check_clenr0()
res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
nrf5.c:522nrf52_protect_check_bprot()
res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
nrf5.c:565nrf51_protect_clenr0()
res = target_read_u32(chip->target, NRF51_FICR_PPFC,
nrf5.c:577nrf51_protect_clenr0()
res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
nrf5.c:719nrf5_read_ficr_info_part()
int res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part);
nrf5.c:787nrf5_read_ficr_more_info()
res = target_read_u32(target, ficr_base + ficr_offsets->info_variant, &chip->ficr_info.variant);
nrf5.c:791nrf5_read_ficr_more_info()
res = target_read_u32(target, ficr_base + ficr_offsets->info_package, &chip->ficr_info.package);
nrf5.c:795nrf5_read_ficr_more_info()
res = target_read_u32(target, ficr_base + ficr_offsets->info_ram, &chip->ficr_info.ram);
nrf5.c:799nrf5_read_ficr_more_info()
res = target_read_u32(target, ficr_base + ficr_offsets->info_flash, &chip->ficr_info.flash);
nrf5.c:811nrf51_get_ram_size()
res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
nrf5.c:824nrf51_get_ram_size()
res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
nrf5.c:926nrf5_probe_chip()
res = target_read_u32(target, ficr_base + ficr_offsets->configid, &configid);
nrf5.c:965nrf5_probe_chip()
res = target_read_u32(chip->target, ficr_base + ficr_offsets->codepagesize,
nrf5.c:974nrf5_probe_chip()
res = target_read_u32(chip->target, ficr_base + ficr_offsets->codesize,
nrf5.c:1075nrf5_erase_page()
res = target_read_u32(chip->target, NRF51_FICR_PPFC,
nrf5.c:1443nrf5_handle_mass_erase_command()
res = target_read_u32(target, NRF51_FICR_PPFC,
nuc910.c:148nuc910_nand_ready()
target_read_u32(target, NUC910_SMISR, &status);
numicro.c:566numicro_reg_unlock()
retval = target_read_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, &is_protected);
numicro.c:584numicro_reg_unlock()
retval = target_read_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, &is_protected);
numicro.c:612numicro_init_isp()
retval = target_read_u32(target, NUMICRO_SYSCLK_AHBCLK - m_address_bias_offset, &reg_stat);
numicro.c:622numicro_init_isp()
retval = target_read_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, &reg_stat);
numicro.c:663numicro_fmc_cmd()
retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG - m_address_bias_offset, &status);
numicro.c:675numicro_fmc_cmd()
retval = target_read_u32(target, NUMICRO_FLASH_ISPDAT - m_address_bias_offset, rdata);
numicro.c:894numicro_erase()
retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG - m_address_bias_offset, &status);
numicro.c:907numicro_erase()
retval = target_read_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, &status);
numicro.c:988numicro_write()
retval = target_read_u32(target,
numicro.c:1006numicro_write()
retval = target_read_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, &status);
numicro.c:1034numicro_get_cpu_type()
retval = target_read_u32(target, NUMICRO_SYS_BASE - m_address_bias_offset, &part_id);
nuttx.c:128cortexm_hasfpu()
int retval = target_read_u32(target, FPU_CPACR, &cpacr);
nuttx.c:210nuttx_update_threads()
int ret = target_read_u32(rtos->target, rtos->symbols[NX_SYM_NPIDHASH].address, &npidhash);
nuttx.c:218nuttx_update_threads()
ret = target_read_u32(rtos->target, rtos->symbols[NX_SYM_PIDHASH].address, &pidhashaddr);
nuttx.c:260nuttx_update_threads()
ret = target_read_u32(rtos->target, rtos->symbols[NX_SYM_READYTORUN].address, &current_thread);
nuttx.c:396nuttx_getregs_fromstack()
ret = target_read_u32(rtos->target, thread_id + xcpreg_off, &regsaddr);
pic32mm.c:224pic32mm_get_flash_status()
target_read_u32(target, PIC32MM_NVMCON, &status);
pic32mm.c:251pic32mm_nvm_exec()
target_read_u32(target, PIC32MM_NVMCON, &tmp);
pic32mm.c:292pic32mm_unprotect_sectors()
retval = target_read_u32(bank->target, PIC32MM_NVMBWP, &reg);
pic32mm.c:331pic32mm_unprotect_sectors()
retval = target_read_u32(bank->target, PIC32MM_NVMPWP, &reg);
pic32mm.c:818pic32mm_recompute_sector_protection()
if (target_read_u32(target, PIC32MM_NVMBWP, &protection_status) != ERROR_OK)
pic32mm.c:823pic32mm_recompute_sector_protection()
if (target_read_u32(target, PIC32MM_NVMPWP, &protection_status) != ERROR_OK)
pic32mx.c:214pic32mx_get_flash_status()
target_read_u32(target, PIC32MX_NVMCON, &status);
pic32mx.c:280pic32mx_protect_check()
target_read_u32(target, config0_address, &devcfg0);
pic32mx.c:747pic32mx_probe()
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
psoc4.c:335psoc4_sysreq()
retval = target_read_u32(target, psoc4_info->cpuss_sysarg_addr, &sysarg_out_tmp);
psoc4.c:377psoc4_get_silicon_id()
retval = target_read_u32(target, psoc4_info->cpuss_sysreq_addr, &part1);
psoc4.c:706psoc4_test_flash_wounding()
retval = target_read_u32(target, addr, &dummy);
psoc4.c:750psoc4_probe()
retval = target_read_u32(target, psoc4_info->spcif_geometry_addr, &spcif_geometry);
psoc5lp.c:237psoc5lp_get_device_id()
retval = target_read_u32(target, PANTHER_DEVICE_ID, id); /* dummy read */
psoc5lp.c:240psoc5lp_get_device_id()
retval = target_read_u32(target, PANTHER_DEVICE_ID, id);
psoc5lp.c:941psoc5lp_eeprom_probe()
retval = target_read_u32(bank->target, PM_ACT_CFG12, &val);
psoc6.c:237ipc_poll_lock_stat()
hr = target_read_u32(target, MEM_IPC_LOCK_STATUS(ipc_id), &reg_val);
psoc6.c:287ipc_acquire()
hr = target_read_u32(target, MEM_IPC_ACQUIRE(ipc_id), &reg_val);
psoc6.c:353call_sromapi()
hr = target_read_u32(target, working_area, data_out);
psoc6.c:355call_sromapi()
hr = target_read_u32(target, MEM_IPC_DATA(IPC_ID), data_out);
psoc6.c:561psoc6_probe()
target_read_u32(target, PSOC6_SPCIF_GEOMETRY, &geom);
psoc6.c:908handle_reset_halt()
hr = target_read_u32(target, vt_offset_reg, &vt_base);
psoc6.c:918handle_reset_halt()
hr = target_read_u32(target, vt_base + 4, &reset_addr);
qn908x.c:244qn908x_update_reg()
retval = target_read_u32(target, reg, &orig_value);
qn908x.c:282qn908x_load_lock_stat()
retval = target_read_u32(target, QN908X_FMC_STATUS1, &status1);
qn908x.c:290qn908x_load_lock_stat()
if (target_read_u32(target, addr, &lock_stat) == ERROR_OK)
qn908x.c:301qn908x_init_flash()
int retval = target_read_u32(target, QN908X_SYSCON_CLK_CTRL, &clk_ctrl);
qn908x.c:319qn908x_init_flash()
retval = target_read_u32(target, QN908X_SYSCON_XTAL_CTRL, &clk_xtal);
qn908x.c:419qn908x_busy_check()
int retval = target_read_u32(target, QN908X_FMC_STATUS1, &status1);
qn908x.c:434qn908x_status_check()
int retval = target_read_u32(target, QN908X_FMC_INT_STAT, &int_stat);
qn908x.c:811is_flash_protected()
retval = target_read_u32(bank->target, QN908X_FMC_LOCK_STAT_8, &lock_stat);
qn908x.c:851qn908x_probe()
retval = target_read_u32(bank->target, QN908X_INFO_PAGE_CRC32, &read_crc);
qn908x.c:951qn908x_get_info()
retval = target_read_u32(bank->target, QN908X_SYSCON_CHIP_ID, &chip_id);
qn908x.c:956qn908x_get_info()
retval = target_read_u32(bank->target, QN908X_INFO_PAGE_BOOTLOADER_VER,
qn908x.c:1061qn908x_handle_mass_erase_command()
retval = target_read_u32(target, QN908X_FMC_LOCK_STAT_8, &lock_stat_8);
renesas_rpchf.c:172rpc_hf_wait_tend()
ret = target_read_u32(target, reg, &val);
renesas_rpchf.c:192clrsetbits_u32()
ret = target_read_u32(target, reg, &val);
renesas_rpchf.c:260rpc_hf_mode()
return target_read_u32(target, rpc_base + RPC_DRCR, &val);
renesas_rpchf.c:368rpc_hf_xfer()
ret = target_read_u32(target, rpc_base + RPC_SMRDR0, &val32);
riot.c:211riot_update_threads()
retval = target_read_u32(rtos->target,
riot.c:264riot_update_threads()
retval = target_read_u32(rtos->target,
riot.c:335riot_get_thread_reg_list()
retval = target_read_u32(rtos->target,
riot.c:345riot_get_thread_reg_list()
retval = target_read_u32(rtos->target,
rp2040.c:60rp2040_lookup_symbol()
int err = target_read_u32(target, BOOTROM_MAGIC_ADDR, &magic);
rp2040.c:336rp2040_ssel_active()
int err = target_read_u32(target, qspi_ctrl_addr, &val);
rp2040.c:363rp2040_spi_read_flash_id()
err = target_read_u32(target, ssi_dr0, &status);
rsl10.c:165rsl10_protect_check()
int retval = target_read_u32(bank->target, RSL10_FLASH_REG_IF_STATUS, &status);
rsl10.c:204rsl10_protect()
retval = target_read_u32(bank->target, RSL10_FLASH_REG_MAIN_CTRL, &status);
rsl10.c:239rsl10_protect()
retval = target_read_u32(bank->target, RSL10_FLASH_REG_NVR_CTRL, &status);
rsl10.c:263rsl10_check_device()
int retval = target_read_u32(bank->target, RSL10_REG_ID, &configid);
rsl10.c:369rsl10_ll_flash_erase()
retval = target_read_u32(target, RSL10_ROM_CMD_ERASE_SECTOR, &cmd);
rsl10.c:449rsl10_ll_flash_write()
retval = target_read_u32(target, RSL10_ROM_CMD_WRITE_BUFFER, &cmd);
rsl10.c:526rsl10_mass_erase()
retval = target_read_u32(target, RSL10_ROM_CMD_ERASE_ALL, &cmd);
rtkernel.c:119rtkernel_add_task()
retval = target_read_u32(rtos->target, task + rtos->symbols[sym___off_task2name].address, &name);
rtkernel.c:194rtkernel_verify_task()
retval = target_read_u32(rtos->target, task + rtos->symbols[sym___off_task2magic].address, &magic);
rtkernel.c:220rtkernel_update_threads()
int retval = target_read_u32(rtos->target,
rtkernel.c:241rtkernel_update_threads()
retval = target_read_u32(rtos->target, next, &next);
rtkernel.c:286rtkernel_get_thread_reg_list()
int retval = target_read_u32(rtos->target, thread_id + rtos->symbols[sym___off_task2stack].address, &stack_ptr);
rtkernel.c:306rtkernel_get_thread_reg_list()
retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr);
rtkernel.c:327rtkernel_get_thread_reg_list()
retval = target_read_u32(rtos->target, stack_ptr + 0x20, &lr_svc);
s3c2440.c:90s3c2440_read_block_data()
target_read_u32(target, nfdata, &tmp);
sim3x.c:223sim3x_erase_page()
ret = target_read_u32(target, FLASHCTRL0_CONFIG_ALL, &temp);
sim3x.c:306sim3x_flash_erase()
ret = target_read_u32(target, FLASHCTRL0_CONFIG_ALL, &temp);
sim3x.c:527sim3x_flash_lock_check()
ret = target_read_u32(bank->target, LOCK_WORD_ADDRESS, &lock_word);
sim3x.c:639sim3x_read_deviceid()
ret = target_read_u32(bank->target, DEVICEID0_DEVICEID2, &device_id);
sim3x.c:648sim3x_read_deviceid()
ret = target_read_u32(bank->target, DEVICEID0_DEVICEID1, &device_id);
sim3x.c:667sim3x_read_deviceid()
ret = target_read_u32(bank->target, DEVICEID0_DEVICEID0, &device_id);
sim3x.c:739sim3x_read_info()
ret = target_read_u32(bank->target, CPUID, &cpuid);
sim3x.c:991sim3x_lock()
ret = target_read_u32(target, CPUID, &val);
sim3x.c:1011sim3x_lock()
ret = target_read_u32(target, CPUID, &val);
sim3x.c:1029sim3x_lock()
ret = target_read_u32(target, LOCK_WORD_ADDRESS, &val);
stellaris.c:575stellaris_read_clock_info()
target_read_u32(target, SCB_BASE | RCC, &rcc);
stellaris.c:578stellaris_read_clock_info()
target_read_u32(target, SCB_BASE | RCC2, &rcc2);
stellaris.c:581stellaris_read_clock_info()
target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
stellaris.c:658stellaris_read_part_info()
target_read_u32(target, SCB_BASE | DID0, &did0);
stellaris.c:659stellaris_read_part_info()
target_read_u32(target, SCB_BASE | DID1, &did1);
stellaris.c:660stellaris_read_part_info()
target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
stellaris.c:661stellaris_read_part_info()
target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
stellaris.c:748stellaris_read_part_info()
target_read_u32(target, FLASH_FSIZE, &stellaris_info->fsize);
stellaris.c:749stellaris_read_part_info()
target_read_u32(target, FLASH_SSIZE, &stellaris_info->ssize);
stellaris.c:755stellaris_read_part_info()
target_read_u32(target, FLASH_FSIZE, &stellaris_info->fsize);
stellaris.c:756stellaris_read_part_info()
target_read_u32(target, FLASH_SSIZE, &stellaris_info->ssize);
stellaris.c:811stellaris_protect_check()
target_read_u32(target, fmppe_addr, &fmppe);
stellaris.c:868stellaris_erase()
target_read_u32(target, FLASH_FMC, &flash_fmc);
stellaris.c:872stellaris_erase()
target_read_u32(target, FLASH_CRIS, &flash_cris);
stellaris.c:941stellaris_protect()
target_read_u32(target, fmppe_addr, &fmppe);
stellaris.c:964stellaris_protect()
target_read_u32(target, FLASH_FMC, &flash_fmc);
stellaris.c:968stellaris_protect()
target_read_u32(target, FLASH_CRIS, &flash_cris);
stellaris.c:1154stellaris_write()
target_read_u32(target, FLASH_CRIS, &flash_cris);
stellaris.c:1177stellaris_write()
target_read_u32(target, FLASH_FMC, &flash_fmc);
stellaris.c:1201stellaris_write()
target_read_u32(target, FLASH_FMC, &flash_fmc);
stellaris.c:1206stellaris_write()
target_read_u32(target, FLASH_CRIS, &flash_cris);
stellaris.c:1282stellaris_mass_erase()
target_read_u32(target, FLASH_FMC, &flash_fmc);
stellaris.c:1292stellaris_mass_erase()
target_read_u32(target, FLASH_FMC, &flash_fmc);
stm32f1x.c:159stm32x_get_flash_status()
return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
stm32f1x.c:226stm32x_read_options()
retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
stm32f1x.c:235stm32x_read_options()
retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
stm32f1x.c:356stm32x_protect_check()
retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
stm32f1x.c:791stm32x_get_device_id()
return target_read_u32(target, addr.device_id, device_id);
stm32f1x.c:1434stm32x_handle_options_read_command()
retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
stm32f1x.c:1440stm32x_handle_options_read_command()
retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
stm32f2x.c:270stm32x_get_flash_status()
return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
stm32f2x.c:320stm32x_unlock_reg()
int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
stm32f2x.c:336stm32x_unlock_reg()
retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
stm32f2x.c:352stm32x_unlock_option_reg()
int retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
stm32f2x.c:368stm32x_unlock_option_reg()
retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
stm32f2x.c:389stm32x_read_options()
int retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
stm32f2x.c:407stm32x_read_options()
retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
stm32f2x.c:422stm32x_read_options()
retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
stm32f2x.c:969stm32x_get_device_id()
int retval = target_read_u32(target, 0xE0042000, device_id);
stm32f2x.c:1148stm32x_probe()
retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
stm32f2x.c:1165stm32x_probe()
retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
stm32g0x.c:193stm32x_get_flash_status()
return target_read_u32(target, stm32x_get_flash_reg(bank, STM32G0_FLASH_SR), status);
stm32g0x.c:245stm32x_read_options()
retval = target_read_u32(target, STM32_OB_USER_RDP, &(stm32x_info->option_bytes.user_rdp));
stm32g0x.c:249stm32x_read_options()
retval = target_read_u32(target, STM32_OB_WRP1A, &(stm32x_info->option_bytes.wrp1a));
stm32g0x.c:253stm32x_read_options()
retval = target_read_u32(target, STM32_OB_WRP1B, &(stm32x_info->option_bytes.wrp1b));
stm32g0x.c:258stm32x_read_options()
retval = target_read_u32(target, STM32_OB_PCROP1A_STRT, &start);
stm32g0x.c:261stm32x_read_options()
retval = target_read_u32(target, STM32_OB_PCROP1A_END, &end);
stm32g0x.c:266stm32x_read_options()
retval = target_read_u32(target, STM32_OB_PCROP1B_STRT, &start);
stm32g0x.c:269stm32x_read_options()
retval = target_read_u32(target, STM32_OB_PCROP1B_END, &end);
stm32g0x.c:274stm32x_read_options()
retval = target_read_u32(target, STM32_OB_BOOT_SEC, &(stm32x_info->option_bytes.security));
stm32g0x.c:352stm32x_protect_check()
int retval = target_read_u32(target, stm32x_get_flash_reg(bank, STM32G0_FLASH_WRP1AR), &protection);
stm32g0x.c:368stm32x_protect_check()
retval = target_read_u32(target, stm32x_get_flash_reg(bank, STM32G0_FLASH_WRP1BR), &protection);
stm32g0x.c:399stm32gx_erase()
retval = target_read_u32(target, stm32x_get_flash_reg(bank, STM32G0_FLASH_CR), &val);
stm32g0x.c:666stm32x_get_device_id()
int retval = target_read_u32(target, 0xE000ED00, &cpuid);
stm32g0x.c:679stm32x_get_device_id()
retval = target_read_u32(target, device_id_register, device_id);
stm32g0x.c:691stm32x_get_flash_size()
int retval = target_read_u32(target, 0xE000ED00, &cpuid);
stm32g0x.c:953stm32x_handle_options_read_command()
retval = target_read_u32(target, STM32_OB_USER_RDP, &(options.user_rdp));
stm32g0x.c:957stm32x_handle_options_read_command()
retval = target_read_u32(target, STM32_OB_WRP1A, &(options.wrp1a));
stm32g0x.c:961stm32x_handle_options_read_command()
retval = target_read_u32(target, STM32_OB_WRP1B, &(options.wrp1b));
stm32g4x.c:369stm32l4_read_flash_reg()
return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
stm32g4x.c:796stm32l4_read_idcode()
int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
stm32h7x.c:239stm32x_read_flash_reg()
int retval = target_read_u32(bank->target, reg_addr, value);
stm32h7x.c:743stm32x_read_id_code()
int retval = target_read_u32(bank->target, DBGMCU_IDCODE_REGISTER, id);
stm32l4x.c:845stm32l4_read_flash_reg()
return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
stm32l4x.c:1725stm32l4_read_idcode()
retval = target_read_u32(target, dbgmcu_idcode[i], id);
stm32l4x.c:1753stm32l4_read_idcode()
retval = target_read_u32(target, UID64_IDS, &uid64_ids);
stm32l5x.c:232stm32l4_get_flash_status()
return target_read_u32(
stm32l5x.c:284stm32l4_unlock_reg()
int retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), &ctrl);
stm32l5x.c:300stm32l4_unlock_reg()
retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), &ctrl);
stm32l5x.c:317stm32l4_unlock_option_reg()
int retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), &ctrl);
stm32l5x.c:333stm32l4_unlock_option_reg()
retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), &ctrl);
stm32l5x.c:348stm32l4_read_option()
return target_read_u32(target, stm32l4_get_flash_reg(bank, address), value);
stm32l5x.c:356stm32l4_write_option()
int retval = target_read_u32(target, stm32l4_get_flash_reg(bank, address), &optiondata);
stm32l5x.c:703stm32l4_probe()
int retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_DBGMCU_IDCODE), &device_id);
stm32l5x.c:748stm32l4_probe()
retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_OPTR), &options);
stm32l5x.c:866get_stm32l4_info()
int retval = target_read_u32(target, stm32l4_get_flash_reg(bank, STM32_DBGMCU_IDCODE), &dbgmcu_idcode);
stm32lx.c:369stm32lx_protect_check()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
stm32lx.c:723stm32lx_read_id_code()
retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
stm32lx.c:726stm32lx_read_id_code()
retval = target_read_u32(target, DBGMCU_IDCODE, id);
stm32lx.c:967stm32lx_unlock_program_memory()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:987stm32lx_unlock_program_memory()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:1007stm32lx_unlock_program_memory()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:1034stm32lx_enable_write_half_page()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:1045stm32lx_enable_write_half_page()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:1066stm32lx_lock_program_memory()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:1077stm32lx_lock_program_memory()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
stm32lx.c:1143stm32lx_get_flash_status()
return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
stm32lx.c:1164stm32lx_unlock_options_bytes()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
stm32lx.c:1335stm32lx_mass_erase()
retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
stmqspi.c:244poll_busy()
int retval = target_read_u32(target, io_base + SPI_SR, &spi_sr);
stmqspi.c:268stmqspi_abort()
int retval = target_read_u32(target, io_base + SPI_CR, &cr);
stmqspi.c:367read_status_reg()
(void)target_read_u32(target, io_base + SPI_SR, &dummy);
stmqspi.c:722stmqspi_handle_set()
retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
stmqspi.c:1900read_sfdp_block()
retval = target_read_u32(target, io_base + SPI_DR, &word1);
stmqspi.c:1903read_sfdp_block()
retval = target_read_u32(target, io_base + SPI_DR, &word2);
stmqspi.c:1919read_sfdp_block()
retval = target_read_u32(target, io_base + SPI_DR, buffer);
stmqspi.c:2013read_flash_id()
(void)target_read_u32(target, io_base + SPI_SR, &dummy);
stmqspi.c:2105stmqspi_probe()
(void)target_read_u32(target, io_base + QSPI_ABR, &data);
stmqspi.c:2115stmqspi_probe()
retval = target_read_u32(target, io_base + OCTOSPI_MAGIC, &magic_id);
stmqspi.c:2129stmqspi_probe()
retval = target_read_u32(target, io_base + SPI_CR, &stmqspi_info->saved_cr);
stmqspi.c:2131stmqspi_probe()
retval = target_read_u32(target, io_base + SPI_CCR, &stmqspi_info->saved_ccr);
stmqspi.c:2136stmqspi_probe()
retval = target_read_u32(target, io_base + OCTOSPI_DCR1, &dcr1);
stmqspi.c:2139stmqspi_probe()
retval = target_read_u32(target, io_base + OCTOSPI_TCR,
stmqspi.c:2143stmqspi_probe()
retval = target_read_u32(target, io_base + OCTOSPI_IR,
stmqspi.c:2318stmqspi_probe()
retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
stmsmi.c:153poll_tff()
if (SMI_READ_REG(SMI_SR) & SMI_TFF)
stmsmi.c:159poll_tff()
if (SMI_READ_REG(SMI_SR) & SMI_TFF)
stmsmi.c:188read_status_reg()
*status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
stmsmi.c:232smi_write_enable()
SMI_SET_HW_MODE(); /* AB: is this correct ?*/
stmsmi.c:283smi_erase_sector()
SMI_SET_SW_MODE();
stmsmi.c:347stmsmi_erase()
SMI_SET_HW_MODE();
stmsmi.c:375smi_write_buffer()
SMI_SET_HWWB_MODE();
stmsmi.c:465stmsmi_write()
SMI_SET_HW_MODE();
stmsmi.c:489read_flash_id()
SMI_SET_SW_MODE();
stmsmi.c:506read_flash_id()
*id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
stmsmi.c:558stmsmi_probe()
SMI_SET_HW_MODE();
str7x.c:238str7x_waitbusy()
err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
str7x.c:258str7x_result()
retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
str7x.c:306str7x_protect_check()
retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
str7x.c:731str7x_handle_disable_jtag_command()
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
str7x.c:736str7x_handle_disable_jtag_command()
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
str9x.c:182str9x_protect_check()
retval = target_read_u32(target, adr, &status);
target.c:980target_run_flash_async_algorithm()
retval = target_read_u32(target, rp_addr, &rp);
target.c:1080target_run_flash_async_algorithm()
retval = target_read_u32(target, rp_addr, &rp);
target.c:1135target_run_read_async_algorithm()
retval = target_read_u32(target, wp_addr, &wp);
target.c:1234target_run_read_async_algorithm()
retval = target_read_u32(target, wp_addr, &wp);
tms470.c:126tms470_read_part_info()
target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
tms470.c:373tms470_check_flash_unlocked()
target_read_u32(target, 0xFFE89C08, &fmbbusy);
tms470.c:388tms470_try_flash_keys()
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
tms470.c:392tms470_try_flash_keys()
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
tms470.c:401tms470_try_flash_keys()
target_read_u32(target, 0xFFE8A814, &fmbptr);
tms470.c:406tms470_try_flash_keys()
target_read_u32(target, 0xFFE88004, &fmbac2);
tms470.c:410tms470_try_flash_keys()
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
tms470.c:420tms470_try_flash_keys()
target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
tms470.c:435tms470_try_flash_keys()
target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
tms470.c:499tms470_flash_initialize_internal_state_machine()
target_read_u32(target, 0xFFE8BC04, &fmmac2);
tms470.c:508tms470_flash_initialize_internal_state_machine()
target_read_u32(target, 0xFFE8BC00, &fmmac1);
tms470.c:534tms470_flash_initialize_internal_state_machine()
target_read_u32(target, 0xFFE8A080, &fmmaxep);
tms470.c:561tms470_flash_initialize_internal_state_machine()
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
tms470.c:627tms470_flash_status()
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
tms470.c:681tms470_erase_sector()
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
tms470.c:686tms470_erase_sector()
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
tms470.c:698tms470_erase_sector()
target_read_u32(target, 0xFFE88008, &fmbsea);
tms470.c:702tms470_erase_sector()
target_read_u32(target, 0xFFE8800C, &fmbseb);
tms470.c:723tms470_erase_sector()
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
tms470.c:849tms470_protect()
target_read_u32(target, 0xFFE8BC04, &fmmac2);
tms470.c:853tms470_protect()
target_read_u32(target, 0xFFE88008, &fmbsea);
tms470.c:854tms470_protect()
target_read_u32(target, 0xFFE8800C, &fmbseb);
tms470.c:894tms470_write()
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
tms470.c:900tms470_write()
target_read_u32(target, 0xFFE88004, &fmbac2);
tms470.c:904tms470_write()
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
tms470.c:910tms470_write()
target_read_u32(target, 0xFFE88008, &fmbsea);
tms470.c:912tms470_write()
target_read_u32(target, 0xFFE8800C, &fmbseb);
tms470.c:916tms470_write()
target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
tms470.c:937tms470_write()
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
tms470.c:1005tms470_erase_check()
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
tms470.c:1009tms470_erase_check()
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
tms470.c:1013tms470_erase_check()
target_read_u32(target, 0xFFE8BC04, &fmmac2);
tms470.c:1023tms470_erase_check()
target_read_u32(target, 0xFFE88004, &fmbac2);
tms470.c:1079tms470_protect_check()
target_read_u32(target, 0xFFE8BC04, &fmmac2);
tms470.c:1082tms470_protect_check()
target_read_u32(target, 0xFFE88008, &fmbsea);
tms470.c:1083tms470_protect_check()
target_read_u32(target, 0xFFE8800C, &fmbseb);
w600.c:149w600_start_do()
retval = target_read_u32(target, QFLASH_CMD_START, &status);
w600.c:269w600_get_flash_id()
return target_read_u32(target, QFLASH_BUFFER, flash_id);
xmc1xxx.c:389xmc1xxx_protect_check()
retval = target_read_u32(bank->target, NVMCONF, &nvmconf);
xmc1xxx.c:416xmc1xxx_get_info_command()
retval = target_read_u32(bank->target, FLASH_CS0 + i * 4, &chipid[i]);
xmc1xxx.c:423xmc1xxx_get_info_command()
retval = target_read_u32(bank->target, SCU_BASE + 0x000, &chipid[7]);
xmc1xxx.c:456xmc1xxx_probe()
retval = target_read_u32(bank->target, SCU_IDCHIP, &idchip);
xmc1xxx.c:469xmc1xxx_probe()
retval = target_read_u32(bank->target, PAU_FLSIZE, &flsize);
xmc4xxx.c:336xmc4xxx_probe()
res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
xmc4xxx.c:351xmc4xxx_probe()
res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
xmc4xxx.c:431xmc4xxx_get_flash_status()
res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
xmc4xxx.c:506xmc4xxx_erase_sector()
res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
xmc4xxx.c:806xmc4xxx_get_info_command()
int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
xmc4xxx.c:1163xmc4xxx_protect_check()
ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
xmc4xxx.c:1169xmc4xxx_protect_check()
ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
xmc4xxx.c:1175xmc4xxx_protect_check()
ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
xscale.c:731xscale_update_vectors()
retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
xscale.c:745xscale_update_vectors()
retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
xscale.c:1163xscale_resume()
target_read_u32(target, current_pc, &current_opcode);
xscale.c:1297xscale_step_inner()
target_read_u32(target, current_pc, &current_opcode);
zephyr.c:238zephyr_get_arc_state()
retval = target_read_u32(rtos->target, *addr, &real_stack_addr);
zephyr.c:514zephyr_fetch_thread()
retval = target_read_u32(rtos->target, ptr + param->offsets[OFFSET_T_ENTRY],
zephyr.c:519zephyr_fetch_thread()
retval = target_read_u32(rtos->target,
zephyr.c:525zephyr_fetch_thread()
retval = target_read_u32(rtos->target,
zephyr.c:576zephyr_fetch_thread_list()
retval = target_read_u32(rtos->target, zephyr_kptr(rtos, OFFSET_K_THREADS),
zephyr.c:674zephyr_update_threads()
retval = target_read_u32(rtos->target,
zephyr.c:687zephyr_update_threads()
retval = target_read_u32(rtos->target,
zephyr.c:719zephyr_update_threads()
retval = target_read_u32(rtos->target, address, &param->offsets[i]);
zephyr.c:730zephyr_update_threads()
retval = target_read_u32(rtos->target,

Call Tree

Functions calling target_read_u32()
Functions called by target_read_u32()
all items filtered out
target_read_u32()
all items filtered out
Data read by target_read_u32()
target_read_u32()::value_buf
target_read_u32()::retval
all items filtered out
target_read_u32()
Type of target_read_u32()
target_read_u32()
uint8_t
all items filtered out