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target::tap
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target::tap
target::tap field
Syntax
from
target.h:119
struct
jtag_tap
*
tap
;
References
Location
Referrer
Text
target.h:119
struct
jtag_tap
*
tap
;
/* where on the jtag chain is this */
arc.c:1439
arc_target_create()
CHECK_RETVAL
(
arc_init_arch_info
(
target
,
arc
,
target
->
tap
)
)
;
arm11.c:107
arm11_debug_entry()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11.c:295
arm11_leave_debug_state()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11.c:1088
arm11_target_create()
if
(
!
target
->
tap
)
arm11.c:1091
arm11_target_create()
if
(
target
->
tap
->
ir_length
!=
5
)
{
arm11.c:1103
arm11_target_create()
arm11
->
jtag_info
.
tap
=
target
->
tap
;
arm11.c:1149
arm11_examine()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
1
,
&
idcode_field
,
TAP_DRPAUSE
)
;
arm11.c:1162
arm11_examine()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11_dbgtap.c:126
arm11_add_ir()
struct
jtag_tap
*
tap
=
arm11
->
arm
.
target
->
tap
;
arm11_dbgtap.c:139
arm11_add_ir()
arm11_add_ir_scan_vc
(
arm11
->
arm
.
target
->
tap
,
arm11_dbgtap.c:210
arm11_add_debug_scan_n()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
arm11_dbgtap.c:252
arm11_add_debug_inst()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
itr
)
,
itr
,
state
)
;
arm11_dbgtap.c:280
arm11_read_dscr()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
1
,
&
chain1_field
,
TAP_DRPAUSE
)
;
arm11_dbgtap.c:316
arm11_write_dscr()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
1
,
&
chain1_field
,
TAP_DRPAUSE
)
;
arm11_dbgtap.c:476
arm11_run_instr_data_to_core()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11_dbgtap.c:507
arm11_run_instr_data_to_core()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11_dbgtap.c:647
arm11_run_instr_data_to_core_noack()
int
retval
=
arm11_run_instr_data_to_core_noack_inner
(
arm11
->
arm
.
target
->
tap
,
arm11_dbgtap.c:678
arm11_run_instr_data_to_core_noack()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11_dbgtap.c:751
arm11_run_instr_data_from_core()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
arm11_dbgtap.c:886
arm11_sc7_run()
arm11_add_dr_scan_vc
(
arm11
->
arm
.
target
->
tap
,
ARRAY_SIZE
(
chain7_fields
)
,
arm720t.c:420
arm720t_target_create()
return
arm720t_init_arch_info
(
target
,
arm720t
,
target
->
tap
)
;
arm7tdmi.c:677
arm7tdmi_target_create()
arm7tdmi_init_arch_info
(
target
,
arm7_9
,
target
->
tap
)
;
arm920t.c:841
arm920t_target_create()
return
arm920t_init_arch_info
(
target
,
arm920t
,
target
->
tap
)
;
arm926ejs.c:710
arm926ejs_target_create()
target
->
tap
->
ir_capture_mask
=
0x0f
;
arm926ejs.c:712
arm926ejs_target_create()
return
arm926ejs_init_arch_info
(
target
,
arm926ejs
,
target
->
tap
)
;
arm946e.c:86
arm946e_target_create()
arm946e_init_arch_info
(
target
,
arm946e
,
target
->
tap
)
;
arm966e.c:45
arm966e_target_create()
return
arm966e_init_arch_info
(
target
,
arm966e
,
target
->
tap
)
;
arm9tdmi.c:772
arm9tdmi_target_create()
arm9tdmi_init_arch_info
(
target
,
arm7_9
,
target
->
tap
)
;
arm_adi_v5.c:2470
adiv5_jim_configure_ext()
target
->
tap
=
pc
->
dap
->
tap
;
ath79.c:772
ath79_probe()
if
(
target_device
->
tap_idcode
==
target
->
tap
->
idcode
)
ath79.c:776
ath79_probe()
target
->
tap
->
idcode
)
;
avr32_ap7k.c:508
avr32_ap7k_init_target()
ap7k
->
jtag
.
tap
=
target
->
tap
;
avrt.c:75
avr_target_create()
avr
->
jtag_info
.
tap
=
target
->
tap
;
batch.c:101
riscv_batch_run()
jtag_add_dr_scan
(
batch
->
target
->
tap
,
1
,
batch
->
fields
+
i
,
TAP_IDLE
)
;
dsp563xx.c:488
dsp563xx_reg_read_high_io()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
0
,
instr
)
;
dsp563xx.c:493
dsp563xx_reg_read_high_io()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
1
,
instr
)
;
dsp563xx.c:497
dsp563xx_reg_read_high_io()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OGDBR
,
data
)
;
dsp563xx.c:517
dsp563xx_reg_write_high_io()
err
=
dsp563xx_once_execute_dw_ir
(
target
->
tap
,
0
,
0x60F400
,
data
)
;
dsp563xx.c:522
dsp563xx_reg_write_high_io()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
1
,
instr
)
;
dsp563xx.c:538
dsp563xx_reg_read()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
0
,
instr
)
;
dsp563xx.c:542
dsp563xx_reg_read()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
1
,
0x000000
)
;
dsp563xx.c:546
dsp563xx_reg_read()
return
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OGDBR
,
data
)
;
dsp563xx.c:553
dsp563xx_reg_write()
err
=
dsp563xx_once_execute_dw_ir
(
target
->
tap
,
0
,
instr_mask
,
data
)
;
dsp563xx.c:557
dsp563xx_reg_write()
return
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
1
,
0x000000
)
;
dsp563xx.c:890
dsp563xx_target_create()
dsp563xx
->
jtag_info
.
tap
=
target
->
tap
;
dsp563xx.c:915
dsp563xx_examine()
if
(
!
target
->
tap
->
has_idcode
)
{
dsp563xx.c:924
dsp563xx_examine()
chip
=
(
target
->
tap
->
idcode
>
>
12
)
&
0x3ff
;
dsp563xx.c:932
dsp563xx_examine()
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OBCR
,
0
)
;
dsp563xx.c:949
dsp563xx_debug_once_init()
return
dsp563xx_once_read_register
(
target
->
tap
,
1
,
once_regs
,
DSP563XX_NUMONCEREGS
)
;
dsp563xx.c:975
dsp563xx_debug_init()
err
=
dsp563xx_once_execute_dw_ir
(
target
->
tap
,
1
,
arch_info
->
instr_mask
,
sr
)
;
dsp563xx.c:1035
dsp563xx_jtag_debug_request()
return
dsp563xx_once_request_debug
(
target
->
tap
,
target
->
state
==
TARGET_RESET
)
;
dsp563xx.c:1045
dsp563xx_poll()
state
=
dsp563xx_once_target_status
(
target
->
tap
)
;
dsp563xx.c:1053
dsp563xx_poll()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OSCR
,
&
once_status
)
;
dsp563xx.c:1076
dsp563xx_poll()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OBCR
,
0
)
;
dsp563xx.c:1080
dsp563xx_poll()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OMLR0
,
0
)
;
dsp563xx.c:1084
dsp563xx_poll()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OMLR1
,
0
)
;
dsp563xx.c:1147
dsp563xx_resume()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPDBR
,
dsp563xx.c:1151
dsp563xx_resume()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPDBR
|
dsp563xx.c:1158
dsp563xx_resume()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPDBR
,
INSTR_JUMP
)
;
dsp563xx.c:1161
dsp563xx_resume()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_PDBGOTO
|
dsp563xx.c:1212
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OSCR
,
0x000000
)
;
dsp563xx.c:1216
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OSCR
,
DSP563XX_ONCE_OSCR_TME
)
;
dsp563xx.c:1227
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OTC
,
cnt
)
;
dsp563xx.c:1233
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPDBR
,
dsp563xx.c:1237
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPDBR
|
dsp563xx.c:1244
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPDBR
,
INSTR_JUMP
)
;
dsp563xx.c:1247
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_PDBGOTO
|
dsp563xx.c:1255
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OSCR
,
&
once_status
)
;
dsp563xx.c:1260
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPABFR
,
&
dr_in
)
;
dsp563xx.c:1264
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPABDR
,
&
dr_in
)
;
dsp563xx.c:1268
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
1
,
DSP563XX_ONCE_OPABEX
,
&
dr_in
)
;
dsp563xx.c:1274
dsp563xx_step_ex()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OSCR
,
0x000000
)
;
dsp563xx.c:1561
dsp563xx_read_memory_core()
err
=
dsp563xx_once_execute_dw_ir
(
target
->
tap
,
1
,
0x60F400
,
address
)
;
dsp563xx.c:1566
dsp563xx_read_memory_core()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
0
,
move_cmd
)
;
dsp563xx.c:1569
dsp563xx_read_memory_core()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
0
,
0x08D13C
)
;
dsp563xx.c:1572
dsp563xx_read_memory_core()
err
=
dsp563xx_once_reg_read
(
target
->
tap
,
0
,
dsp563xx.c:1743
dsp563xx_write_memory_core()
err
=
dsp563xx_once_execute_dw_ir
(
target
->
tap
,
1
,
0x60F400
,
address
)
;
dsp563xx.c:1754
dsp563xx_write_memory_core()
err
=
dsp563xx_once_execute_dw_ir
(
target
->
tap
,
0
,
0x61F400
,
data
)
;
dsp563xx.c:1757
dsp563xx_write_memory_core()
err
=
dsp563xx_once_execute_sw_ir
(
target
->
tap
,
0
,
move_cmd
)
;
dsp563xx.c:1952
dsp563xx_add_custom_watchpoint()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OMLR0
,
address
)
;
dsp563xx.c:1955
dsp563xx_add_custom_watchpoint()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OMLR1
,
0x0
)
;
dsp563xx.c:1958
dsp563xx_add_custom_watchpoint()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OBCR
,
obcr_value
)
;
dsp563xx.c:1962
dsp563xx_add_custom_watchpoint()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OMBC
,
0
)
;
dsp563xx.c:1967
dsp563xx_add_custom_watchpoint()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OTC
,
0
)
;
dsp563xx.c:1993
dsp563xx_remove_custom_watchpoint()
err
=
dsp563xx_once_reg_write
(
target
->
tap
,
1
,
DSP563XX_ONCE_OBCR
,
0
)
;
dsp5680xx.c:77
dsp5680xx_drscan()
if
(
!
target
->
tap
)
{
dsp5680xx.c:119
dsp5680xx_irscan()
if
(
!
target
->
tap
)
{
dsp5680xx.c:124
dsp5680xx_irscan()
if
(
ir_len
!=
target
->
tap
->
ir_length
)
{
dsp5680xx.c:125
dsp5680xx_irscan()
if
(
target
->
tap
->
enabled
)
{
dsp5680xx.c:1543
dsp5680xx_f_sim_reset()
if
(
strcmp
(
target
->
tap
->
chip
,
"dsp568013"
)
==
0
)
{
esirisc.c:1580
esirisc_target_create()
struct
jtag_tap
*
tap
=
target
->
tap
;
esp32.c:333
esp32_target_create()
.
tap
=
target
->
tap
,
esp32s2.c:452
esp32s2_target_create()
.
tap
=
target
->
tap
,
esp32s3.c:327
esp32s3_target_create()
.
tap
=
target
->
tap
,
fa526.c:336
fa526_target_create()
return
fa526_init_arch_info
(
target
,
arm920t
,
target
->
tap
)
;
feroceon.c:629
feroceon_target_create()
arm926ejs_init_arch_info
(
target
,
arm926ejs
,
target
->
tap
)
;
feroceon.c:647
dragonite_target_create()
arm966e_init_arch_info
(
target
,
arm966e
,
target
->
tap
)
;
fespi.c:739
fespi_probe()
if
(
target_device
->
tap_idcode
==
target
->
tap
->
idcode
)
fespi.c:744
fespi_probe()
target
->
tap
->
idcode
)
;
hla_interface.c:74
hl_interface_init_target()
res
=
hl_if
.
layout
->
api
->
idcode
(
hl_if
.
handle
,
&
t
->
tap
->
idcode
)
;
hla_interface.c:79
hl_interface_init_target()
unsigned
ii
,
limit
=
t
->
tap
->
expected_ids_cnt
;
hla_interface.c:83
hl_interface_init_target()
uint32_t
expected
=
t
->
tap
->
expected_ids
[
ii
]
;
hla_interface.c:86
hl_interface_init_target()
if
(
!
expected
||
!
t
->
tap
->
idcode
||
hla_interface.c:87
hl_interface_init_target()
(
t
->
tap
->
idcode
==
expected
)
)
{
hla_interface.c:94
hl_interface_init_target()
LOG_WARNING
(
"UNEXPECTED idcode: 0x%08"
PRIx32
,
t
->
tap
->
idcode
)
;
hla_interface.c:97
hl_interface_init_target()
t
->
tap
->
expected_ids
[
ii
]
)
;
hla_interface.c:102
hl_interface_init_target()
t
->
tap
->
priv
=
&
hl_if
;
hla_interface.c:103
hl_interface_init_target()
t
->
tap
->
has_idcode
=
true
;
hla_target.c:41
target_to_adapter()
return
target
->
tap
->
priv
;
hla_target.c:208
adapter_target_create()
adapter_init_arch_info
(
target
,
cortex_m
,
target
->
tap
)
;
jtagspi.c:70
jtagspi_flash_bank_command()
if
(
!
bank
->
target
->
tap
)
{
jtagspi.c:74
jtagspi_flash_bank_command()
info
->
tap
=
bank
->
target
->
tap
;
lakemont.c:219
irscan()
if
(
!
t
->
tap
)
{
lakemont.c:224
irscan()
if
(
ir_len
!=
t
->
tap
->
ir_length
)
{
lakemont.c:226
irscan()
if
(
t
->
tap
->
enabled
)
lakemont.c:228
irscan()
__func__
,
t
->
tap
->
ir_length
)
;
lakemont.c:231
irscan()
__func__
,
t
->
tap
->
ir_length
)
;
lakemont.c:252
drscan()
if
(
!
t
->
tap
)
{
ls1_sap.c:24
ls1_sap_target_create()
ls1_sap
->
tap
=
target
->
tap
;
ls1_sap.c:181
ls1_sap_read_memory()
ls1_sap_set_addr_high
(
target
->
tap
,
0
)
;
ls1_sap.c:184
ls1_sap_read_memory()
ls1_sap_memory_cmd
(
target
->
tap
,
address
,
size
,
true
)
;
ls1_sap.c:185
ls1_sap_read_memory()
ls1_sap_memory_read
(
target
->
tap
,
size
,
buffer
)
;
ls1_sap.c:204
ls1_sap_write_memory()
ls1_sap_set_addr_high
(
target
->
tap
,
0
)
;
ls1_sap.c:207
ls1_sap_write_memory()
ls1_sap_memory_cmd
(
target
->
tap
,
address
,
size
,
false
)
;
ls1_sap.c:208
ls1_sap_write_memory()
ls1_sap_memory_write
(
target
->
tap
,
size
,
buffer
)
;
mips_m4k.c:1163
mips_m4k_target_create()
mips_m4k_init_arch_info
(
target
,
mips_m4k
,
target
->
tap
)
;
mips_mips64.c:1102
mips_mips64_target_create()
return
mips64_init_arch_info
(
target
,
mips64
,
target
->
tap
)
;
or1k.c:1091
or1k_init_target()
or1k
->
jtag
.
tap
=
target
->
tap
;
or1k.c:1103
or1k_target_create()
if
(
!
target
->
tap
)
riscv-011.c:290
dtmcontrol_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dtmcontrol
,
TAP_IDLE
)
;
riscv-011.c:295
dtmcontrol_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
&
field
,
TAP_IDLE
)
;
riscv-011.c:298
dtmcontrol_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:317
idcode_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_idcode
,
TAP_IDLE
)
;
riscv-011.c:322
idcode_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
&
field
,
TAP_IDLE
)
;
riscv-011.c:331
idcode_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:382
add_dbus_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
field
,
TAP_IDLE
)
;
riscv-011.c:442
dbus_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
&
field
,
TAP_IDLE
)
;
riscv-011.c:1393
halt()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:1445
step()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:1901
poll_target()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:1936
riscv011_resume()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:1947
assert_reset()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:1980
deassert_reset()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:1995
read_memory()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-011.c:2161
write_memory()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-013.c:239
get_dm()
unsigned
int
abs_chain_position
=
target
->
tap
->
abs_chain_position
;
riscv-013.c:414
select_dmi()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv-013.c:428
dtmcontrol_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dtmcontrol
,
TAP_IDLE
)
;
riscv-013.c:433
dtmcontrol_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
&
field
,
TAP_IDLE
)
;
riscv-013.c:509
dmi_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
&
field
,
TAP_IDLE
)
;
riscv.c:284
select_dmi_via_bscan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_user4
,
TAP_IDLE
)
;
riscv.c:286
select_dmi_via_bscan()
jtag_add_dr_scan
(
target
->
tap
,
bscan_tunnel_data_register_select_dmi_num_fields
,
riscv.c:289
select_dmi_via_bscan()
jtag_add_dr_scan
(
target
->
tap
,
bscan_tunnel_nested_tap_select_dmi_num_fields
,
riscv.c:359
dtmcontrol_scan_via_bscan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_user4
,
TAP_IDLE
)
;
riscv.c:360
dtmcontrol_scan_via_bscan()
jtag_add_dr_scan
(
target
->
tap
,
ARRAY_SIZE
(
tunneled_ir
)
,
tunneled_ir
,
TAP_IDLE
)
;
riscv.c:361
dtmcontrol_scan_via_bscan()
jtag_add_dr_scan
(
target
->
tap
,
ARRAY_SIZE
(
tunneled_dr
)
,
tunneled_dr
,
TAP_IDLE
)
;
riscv.c:389
dtmcontrol_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dtmcontrol
,
TAP_IDLE
)
;
riscv.c:394
dtmcontrol_scan()
jtag_add_dr_scan
(
target
->
tap
,
1
,
&
field
,
TAP_IDLE
)
;
riscv.c:397
dtmcontrol_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_dbus
,
TAP_IDLE
)
;
riscv.c:449
riscv_init_target()
select_dtmcontrol
.
num_bits
=
target
->
tap
->
ir_length
;
riscv.c:450
riscv_init_target()
select_dbus
.
num_bits
=
target
->
tap
->
ir_length
;
riscv.c:451
riscv_init_target()
select_idcode
.
num_bits
=
target
->
tap
->
ir_length
;
riscv.c:455
riscv_init_target()
uint32_t
ir_user4_raw
=
0x23
<
<
(
target
->
tap
->
ir_length
-
6
)
;
riscv.c:457
riscv_init_target()
select_user4
.
num_bits
=
target
->
tap
->
ir_length
;
riscv.c:4421
riscv_add_bscan_tunneled_scan()
jtag_add_ir_scan
(
target
->
tap
,
&
select_user4
,
TAP_IDLE
)
;
riscv.c:4454
riscv_add_bscan_tunneled_scan()
jtag_add_dr_scan
(
target
->
tap
,
ARRAY_SIZE
(
ctxt
->
tunneled_dr
)
,
ctxt
->
tunneled_dr
,
TAP_IDLE
)
;
sh_qspi.c:766
sh_qspi_probe()
if
(
target_device
->
tap_idcode
==
target
->
tap
->
idcode
)
sh_qspi.c:770
sh_qspi_probe()
target
->
tap
->
idcode
)
;
stm8.c:1117
stm8_target_create()
stm8_init_arch_info
(
target
,
stm8
,
target
->
tap
)
;
stmsmi.c:525
stmsmi_probe()
if
(
target_device
->
tap_idcode
==
target
->
tap
->
idcode
)
stmsmi.c:529
stmsmi_probe()
target
->
tap
->
idcode
)
;
target.c:698
jtag_enable_callback()
if
(
event
!=
JTAG_TAP_EVENT_ENABLE
||
!
target
->
tap
->
enabled
)
target.c:718
target_examine()
if
(
!
target
->
tap
->
enabled
)
{
target.c:2799
find_target()
if
(
!
target
->
tap
->
enabled
)
{
target.c:2802
find_target()
target
->
tap
->
dotted_name
)
;
target.c:2832
handle_targets_command()
if
(
target
->
tap
->
enabled
)
target.c:2849
handle_targets_command()
target
->
tap
->
dotted_name
,
target.c:2983
handle_target()
if
(
!
target
->
tap
->
enabled
)
target.c:3182
handle_poll_command()
target
->
tap
->
dotted_name
,
target.c:3183
handle_poll_command()
target
->
tap
->
enabled
?
"enabled"
:
"disabled"
)
;
target.c:3184
handle_poll_command()
if
(
!
target
->
tap
->
enabled
)
target.c:5266
target_configure()
target
->
tap
=
tap
;
target.c:5272
target_configure()
Jim_SetResultString
(
goi
->
interp
,
target
->
tap
->
dotted_name
,
-
1
)
;
target.c:5385
handle_target_examine()
if
(
!
target
->
tap
->
enabled
)
{
target.c:5447
handle_target_poll()
if
(
!
target
->
tap
->
enabled
)
{
target.c:5474
handle_target_reset()
if
(
!
target
->
tap
->
enabled
)
{
target.c:5506
handle_target_halt()
if
(
!
target
->
tap
->
enabled
)
{
target.c:5529
handle_target_wait_state()
if
(
!
target
->
tap
->
enabled
)
{
target.c:5952
target_create()
if
(
!
target
->
tap
)
x86_32_common.c:91
x86_32_common_init_arch_info()
x86_32
->
curr_tap
=
t
->
tap
;
xcf.c:89
product_name()
switch
(
bank
->
target
->
tap
->
idcode
&
ID_MEANINGFUL_MASK
)
{
xcf.c:130
read_status()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:157
isc_enter()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:186
isc_leave()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:226
isc_read_register()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_DRSHIFT
)
;
xcf.c:231
isc_read_register()
jtag_add_dr_scan
(
bank
->
target
->
tap
,
1
,
&
scan
,
TAP_IDLE
)
;
xcf.c:265
isc_set_register()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_DRSHIFT
)
;
xcf.c:270
isc_set_register()
jtag_add_dr_scan
(
bank
->
target
->
tap
,
1
,
&
scan
,
TAP_IDLE
)
;
xcf.c:291
isc_program_register()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_DRSHIFT
)
;
xcf.c:296
isc_program_register()
jtag_add_dr_scan
(
bank
->
target
->
tap
,
1
,
&
scan
,
TAP_IRSHIFT
)
;
xcf.c:301
isc_program_register()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:360
isc_data_read_out()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:365
isc_data_read_out()
jtag_add_dr_scan
(
bank
->
target
->
tap
,
1
,
&
scan
,
TAP_IDLE
)
;
xcf.c:547
fpga_configure()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:594
xcf_probe()
if
(
!
bank
->
target
->
tap
)
{
xcf.c:600
xcf_probe()
if
(
!
bank
->
target
->
tap
->
has_idcode
)
xcf.c:604
xcf_probe()
id
=
bank
->
target
->
tap
->
idcode
;
xcf.c:632
xcf_probe()
LOG_INFO
(
"device id = 0x%"
PRIX32
,
bank
->
target
->
tap
->
idcode
)
;
xcf.c:678
xcf_erase_check()
jtag_add_ir_scan
(
bank
->
target
->
tap
,
&
scan
,
TAP_IDLE
)
;
xcf.c:684
xcf_erase_check()
jtag_add_dr_scan
(
bank
->
target
->
tap
,
1
,
&
scan
,
TAP_IDLE
)
;
xscale.c:171
xscale_read_dcsr()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:193
xscale_read_dcsr()
jtag_add_dr_scan
(
target
->
tap
,
3
,
fields
,
TAP_DRPAUSE
)
;
xscale.c:214
xscale_read_dcsr()
jtag_add_dr_scan
(
target
->
tap
,
3
,
fields
,
TAP_DRPAUSE
)
;
xscale.c:267
xscale_receive()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:285
xscale_receive()
jtag_add_dr_scan_check
(
target
->
tap
,
3
,
fields
,
TAP_IDLE
)
;
xscale.c:344
xscale_read_tx()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:384
xscale_read_tx()
jtag_add_dr_scan
(
target
->
tap
,
3
,
fields
,
TAP_IDLE
)
;
xscale.c:430
xscale_write_rx()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:454
xscale_write_rx()
jtag_add_dr_scan
(
target
->
tap
,
3
,
fields
,
TAP_IDLE
)
;
xscale.c:483
xscale_write_rx()
jtag_add_dr_scan
(
target
->
tap
,
3
,
fields
,
TAP_IDLE
)
;
xscale.c:501
xscale_send()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:541
xscale_send()
jtag_add_dr_scan
(
target
->
tap
,
xscale.c:583
xscale_write_dcsr()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:605
xscale_write_dcsr()
jtag_add_dr_scan
(
target
->
tap
,
3
,
fields
,
TAP_IDLE
)
;
xscale.c:645
xscale_load_ic()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:666
xscale_load_ic()
jtag_add_dr_scan
(
target
->
tap
,
2
,
fields
,
TAP_IDLE
)
;
xscale.c:682
xscale_load_ic()
jtag_add_dr_scan
(
target
->
tap
,
2
,
fields
,
TAP_IDLE
)
;
xscale.c:695
xscale_invalidate_ic_line()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:713
xscale_invalidate_ic_line()
jtag_add_dr_scan
(
target
->
tap
,
2
,
fields
,
TAP_IDLE
)
;
xscale.c:1456
xscale_assert_reset()
xscale_jtag_set_instr
(
target
->
tap
,
xscale.c:1466
xscale_assert_reset()
xscale_jtag_set_instr
(
target
->
tap
,
~
0
,
TAP_IDLE
)
;
xscale.c:3028
xscale_target_create()
return
xscale_init_arch_info
(
target
,
xscale
,
target
->
tap
)
;
xtensa_chip.c:105
xtensa_chip_target_create()
xtensa_chip_dm_cfg
.
tap
=
target
->
tap
;
xtensa_chip.c:106
xtensa_chip_target_create()
LOG_DEBUG
(
"JTAG: %s:%s pos %u"
,
target
->
tap
->
chip
,
target
->
tap
->
tapname
,
xtensa_chip.c:107
xtensa_chip_target_create()
target
->
tap
->
abs_chain_position
)
;
Data Use
Functions writing
target::tap
Functions reading
target::tap
adiv5_jim_configure_ext()
target_configure()
all items filtered out
target::tap
ath79_probe()
jtagspi_flash_bank_command()
stmsmi_probe()
product_name()
read_status()
isc_enter()
isc_leave()
isc_read_register()
isc_set_register()
isc_program_register()
isc_data_read_out()
fpga_configure()
xcf_probe()
xcf_erase_check()
fespi_probe()
sh_qspi_probe()
hl_interface_init_target()
or1k_init_target()
or1k_target_create()
arm11_debug_entry()
arm11_leave_debug_state()
arm11_target_create()
arm11_examine()
arm11_add_ir()
arm11_add_debug_scan_n()
arm11_add_debug_inst()
arm11_read_dscr()
arm11_write_dscr()
arm11_run_instr_data_to_core()
arm11_run_instr_data_to_core_noack()
arm11_run_instr_data_from_core()
arm11_sc7_run()
arm720t_target_create()
arm7tdmi_target_create()
arm920t_target_create()
arm926ejs_target_create()
arm946e_target_create()
arm966e_target_create()
arm9tdmi_target_create()
avr32_ap7k_init_target()
avr_target_create()
dsp563xx_reg_read_high_io()
dsp563xx_reg_write_high_io()
dsp563xx_reg_read()
dsp563xx_reg_write()
dsp563xx_target_create()
dsp563xx_examine()
dsp563xx_debug_once_init()
dsp563xx_debug_init()
dsp563xx_jtag_debug_request()
dsp563xx_poll()
dsp563xx_resume()
dsp563xx_step_ex()
dsp563xx_read_memory_core()
dsp563xx_write_memory_core()
dsp563xx_add_custom_watchpoint()
dsp563xx_remove_custom_watchpoint()
dsp5680xx_drscan()
dsp5680xx_irscan()
dsp5680xx_f_sim_reset()
fa526_target_create()
feroceon_target_create()
dragonite_target_create()
target_to_adapter()
adapter_target_create()
irscan()
drscan()
ls1_sap_target_create()
ls1_sap_read_memory()
ls1_sap_write_memory()
mips_m4k_target_create()
jtag_enable_callback()
target_examine()
find_target()
handle_targets_command()
handle_target()
handle_poll_command()
target_configure()
handle_target_examine()
handle_target_poll()
handle_target_reset()
handle_target_halt()
handle_target_wait_state()
target_create()
x86_32_common_init_arch_info()
xscale_read_dcsr()
xscale_receive()
xscale_read_tx()
xscale_write_rx()
xscale_send()
xscale_write_dcsr()
xscale_load_ic()
xscale_invalidate_ic_line()
xscale_assert_reset()
xscale_target_create()
stm8_target_create()
riscv_batch_run()
select_dmi_via_bscan()
dtmcontrol_scan_via_bscan()
dtmcontrol_scan()
riscv_init_target()
riscv_add_bscan_tunneled_scan()
dtmcontrol_scan()
idcode_scan()
add_dbus_scan()
dbus_scan()
halt()
step()
poll_target()
riscv011_resume()
assert_reset()
deassert_reset()
read_memory()
write_memory()
get_dm()
select_dmi()
dtmcontrol_scan()
dmi_scan()
esirisc_target_create()
mips_mips64_target_create()
arc_target_create()
esp32_target_create()
esp32s2_target_create()
esp32s3_target_create()
xtensa_chip_target_create()
all items filtered out
Type of
target::tap
target::tap
jtag_tap
all items filtered out