OpenOCD
TARGET_ADDR_FMT is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDTARGET_ADDR_FMT

TARGET_ADDR_FMT macro

Syntax

#define TARGET_ADDR_FMT "0x%8.8" TARGET_PRIxADDR

References

LocationText
types.h:342
#define TARGET_ADDR_FMT "0x%8.8" TARGET_PRIxADDR
aarch64.c:2665
LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
arm11.c:347
LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr);
arm_adi_v5.c:583
LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
arm_adi_v5.c:681
LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
arm_adi_v5.c:2099
command_print(cmd, "%sMEM-AP BASE " TARGET_ADDR_FMT, tabs, dbgbase);
arm_adi_v5.c:2124
command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, v->component_base);
arm_adi_v5.c:2139
command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, v->component_base - 0x1000 * size);
armv7m.c:1007
TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
armv8.c:1357
LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
at91sam4.c:2625
command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
at91sam4.c:2668
LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
at91sam4.c:2669
TARGET_ADDR_FMT ", idx %d", bank->base,
at91sam4l.c:196
LOG_ERROR("Address " TARGET_ADDR_FMT
at91samd.c:945
LOG_ERROR("Address " TARGET_ADDR_FMT
ath79.c:782
LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
atsame5.c:737
LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try "
bluenrg-x.c:328
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
bluenrg-x.c:329
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
bluenrg-x.c:330
LOG_DEBUG("write_algorithm_stack->address = " TARGET_ADDR_FMT, write_algorithm_stack->address);
breakpoints.c:55
LOG_TARGET_ERROR(target, "Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")",
breakpoints.c:93
LOG_TARGET_DEBUG(target, "added %s breakpoint at " TARGET_ADDR_FMT
breakpoints.c:171
LOG_TARGET_ERROR(target, "Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")",
breakpoints.c:199
"added %s Hybrid breakpoint at address " TARGET_ADDR_FMT " of length 0x%8.8x, (BPID: %" PRIu32 ")",
breakpoints.c:359
LOG_TARGET_ERROR(curr, "failed to remove breakpoint at address " TARGET_ADDR_FMT, address);
breakpoints.c:372
LOG_TARGET_ERROR(target, "failed to remove breakpoint at address " TARGET_ADDR_FMT, address);
breakpoints.c:377
LOG_TARGET_ERROR(target, "no breakpoint at address " TARGET_ADDR_FMT " found", address);
breakpoints.c:516
LOG_TARGET_ERROR(target, "address " TARGET_ADDR_FMT
breakpoints.c:550
LOG_TARGET_ERROR(target, "can't add %s watchpoint at " TARGET_ADDR_FMT ", %s",
breakpoints.c:558
LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT
breakpoints.c:620
LOG_TARGET_ERROR(curr, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address);
breakpoints.c:632
LOG_TARGET_ERROR(target, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address);
breakpoints.c:637
LOG_TARGET_ERROR(target, "no watchpoint at address " TARGET_ADDR_FMT " found", address);
breakpoints.c:675
LOG_TARGET_DEBUG(target, "Found hit watchpoint at " TARGET_ADDR_FMT " (WPID: %d)",
cfi.c:868
TARGET_ADDR_FMT, i, bank->base);
cfi.c:923
TARGET_ADDR_FMT, i, bank->base);
cfi.c:1288
LOG_DEBUG("Using target buffer at " TARGET_ADDR_FMT " and of size 0x%04" PRIx32,
cfi.c:1979
LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
cfi.c:2004
LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%"
cfi.c:2034
"couldn't start buffer write operation at base " TARGET_ADDR_FMT
cfi.c:2064
LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT
cfi.c:2095
LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
cfi.c:2119
LOG_ERROR("Write address at base " TARGET_ADDR_FMT
cfi.c:2161
LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
core.c:93
"error writing to flash at address " TARGET_ADDR_FMT
core.c:112
"error reading to flash at address " TARGET_ADDR_FMT
core.c:135
LOG_ERROR("verify failed in bank at " TARGET_ADDR_FMT " starting at 0x%8.8" PRIx32,
core.c:156
LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
core.c:327
LOG_ERROR("No flash at address " TARGET_ADDR_FMT, addr);
core.c:525
TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT,
core.c:546
TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT,
core.c:561
LOG_ERROR("address range " TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT
core.c:801
LOG_WARNING("no flash bank found for address " TARGET_ADDR_FMT, run_address);
core.c:825
LOG_ERROR("Section at " TARGET_ADDR_FMT
core.c:826
" overlaps section ending at " TARGET_ADDR_FMT,
core.c:836
LOG_INFO("Flash write discontinued at " TARGET_ADDR_FMT
core.c:837
", next section at " TARGET_ADDR_FMT,
core.c:843
LOG_INFO("Padding image section %d at " TARGET_ADDR_FMT
core.c:868
LOG_WARNING("Section start address " TARGET_ADDR_FMT
core.c:871
LOG_WARNING("Padding %" PRIu32 " bytes from " TARGET_ADDR_FMT,
core.c:882
LOG_INFO("Padding image section %d at " TARGET_ADDR_FMT
cortex_a.c:1012
LOG_DEBUG("target resumed at " TARGET_ADDR_FMT, address);
cortex_a.c:1016
LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT, address);
cortex_a.c:2720
LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2737
LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2756
LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2773
LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
cortex_a.c:2938
LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT,
cortex_m.c:1380
LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
cortex_m.c:1444
LOG_TARGET_DEBUG(curr, "SMP resumed at " TARGET_ADDR_FMT, address);
cortex_m.c:1470
LOG_TARGET_DEBUG(target, "%sresumed at " TARGET_ADDR_FMT,
cortex_m.c:2098
LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (n=%u)",
cortex_m.c:2119
LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (n=%u)",
eneispif.c:67
LOG_INFO("ASSUMING ISPI device at ctrl_base = " TARGET_ADDR_FMT,
eneispif.c:81
LOG_ERROR("%s error at " TARGET_ADDR_FMT, __func__,
eneispif.c:85
LOG_DEBUG("Read address " TARGET_ADDR_FMT " = 0x%" PRIx32,
eneispif.c:95
LOG_DEBUG("Write address " TARGET_ADDR_FMT " = 0x%" PRIx32,
eneispif.c:99
LOG_ERROR("%s error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT, __func__,
eneispif.c:342
LOG_INFO("Assuming ISPI flash at address " TARGET_ADDR_FMT
eneispif.c:343
" with controller at " TARGET_ADDR_FMT,
esp_algorithm.c:95
LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT,
esp_algorithm.c:165
LOG_DEBUG("Algorithm start @ " TARGET_ADDR_FMT ", stack %d bytes @ " TARGET_ADDR_FMT,
esp_algorithm.c:352
LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64,
esp_algorithm.c:368
LOG_ERROR("working area " TARGET_ADDR_FMT " and stub code section " TARGET_ADDR_FMT
esp_algorithm.c:408
LOG_DEBUG("Write reversed tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, al_tramp_size);
esp_algorithm.c:411
LOG_DEBUG("Write tramp to addr " TARGET_ADDR_FMT ", sz %zu", run->stub.tramp_addr, tramp_sz);
esp_algorithm.c:422
LOG_DEBUG("Tramp mapped to addr " TARGET_ADDR_FMT, run->stub.tramp_mapped_addr);
esp_algorithm.c:446
LOG_DEBUG("addr " TARGET_ADDR_FMT ", sz %d, flags %" PRIx64, section->base_address, section->size,
esp_algorithm.c:463
LOG_ERROR("working area " TARGET_ADDR_FMT
esp_algorithm.c:464
" and stub data section " TARGET_ADDR_FMT
fespi.c:153
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
fespi.c:167
LOG_ERROR("fespi_read_reg() error at " TARGET_ADDR_FMT,
fespi.c:181
LOG_ERROR("fespi_write_reg() error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT,
fespi.c:539
LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
fespi.c:586
LOG_DEBUG("Failed to write %d bytes to " TARGET_ADDR_FMT ": %d",
fespi.c:600
LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
fespi.c:750
LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
fespi.c:754
LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
fespi.c:755
" with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
fm4.c:276
LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
gdb_server.c:2014
"<memory type=\"ram\" start=\"" TARGET_ADDR_FMT "\" "
gdb_server.c:2015
"length=\"" TARGET_ADDR_FMT "\"/>\n",
gdb_server.c:2039
"start=\"" TARGET_ADDR_FMT "\" ",
gdb_server.c:2071
"<memory type=\"ram\" start=\"" TARGET_ADDR_FMT "\" "
gdb_server.c:2072
"length=\"" TARGET_ADDR_FMT "\"/>\n",
hla_target.c:448
LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
hla_target.c:496
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
hla_target.c:601
LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
hla_target.c:616
LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
kinetis.c:1827
LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
kinetis.c:1834
LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
kinetis.c:1850
LOG_ERROR("Error writing section at " TARGET_ADDR_FMT,
kinetis.c:1856
LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
kinetis.c:1899
LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
kinetis.c:1952
LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT,
kinetis.c:1958
LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
kinetis.c:3062
"%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
kinetis_ke.c:1145
command_print_sameline(cmd, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
lpc2000.c:711
LOG_ERROR("Write memory at address " TARGET_ADDR_FMT " failed (check work_area definition)",
lpc2000.c:1180
LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
lpcspifi.c:178
LOG_DEBUG("Writing algorithm to working area at " TARGET_ADDR_FMT,
mem_ap.c:241
LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
mem_ap.c:256
LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
mips64_pracc.c:276
LOG_ERROR("Error reading address " TARGET_ADDR_FMT " (0x%08llx expected)",
mips64_pracc.c:1351
LOG_DEBUG("%s using " TARGET_ADDR_FMT " for write handler", __func__,
mips64_pracc.c:1368
LOG_ERROR("! @MIPS64_PRACC_FASTDATA_AREA (" TARGET_ADDR_FMT ")", address);
mips64_pracc.c:1373
LOG_DEBUG("start: " TARGET_ADDR_FMT, val);
mips64_pracc.c:1383
LOG_DEBUG("stop: " TARGET_ADDR_FMT, val);
mips_m4k.c:466
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
mips_m4k.c:1013
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1078
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1205
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1233
LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
mips_m4k.c:1234
"(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
mips_m4k.c:1271
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_m4k.c:1299
LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within read area "
mips_m4k.c:1300
"(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
mips_mips64.c:952
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
mips_mips64.c:979
LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
mips_mips64.c:980
"(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
niietcm4.c:1576
TARGET_ADDR_FMT " base address", bank->base);
nrf5.c:1032
LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base);
nrf5.c:1387
LOG_ERROR("Invalid nRF bank address " TARGET_ADDR_FMT, bank->base);
numicro.c:879
LOG_DEBUG("erasing sector %u at address " TARGET_ADDR_FMT, i, bank->base + bank->sectors[i].offset);
numicro.c:1058
LOG_INFO("bank base = " TARGET_ADDR_FMT ", size = 0x%08"
pic32mx.c:610
LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
psoc5lp.c:1188
LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT,
qn908x.c:246
LOG_DEBUG("Error reading reg at " TARGET_ADDR_FMT
qn908x.c:254
LOG_DEBUG("Error writing reg at " TARGET_ADDR_FMT " with 0x%08"
qn908x.c:259
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08"
qn908x.c:262
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32
qn908x.c:360
LOG_ERROR("Address " TARGET_ADDR_FMT
renesas_rpchf.c:447
LOG_ERROR("Write address at base " TARGET_ADDR_FMT
renesas_rpchf.c:478
LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
riscv-013.c:2723
LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
riscv-013.c:2751
LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT,
riscv.c:2043
LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
rp2040.c:243
LOG_DEBUG("Allocated flash bounce buffer @" TARGET_ADDR_FMT, bounce->address);
rp2040.c:480
LOG_INFO("RP2040 B0 Flash Probe: %" PRIu32 " bytes @" TARGET_ADDR_FMT ", in %u sectors\n",
rsl10.c:624
LOG_INFO("Creating flash @ " TARGET_ADDR_FMT, bank->base);
rsl10.c:634
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
sh_qspi.c:776
LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
stm32h7x.c:841
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
stm32h7x.c:852
TARGET_ADDR_FMT " but should be 0x%" PRIx32,
stm32h7x.c:858
LOG_INFO("Bank (%u) size is %" PRIu16 " kb, base address is " TARGET_ADDR_FMT,
stm32l4x.c:1655
LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
stm32l4x.c:1880
LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
stm32lx.c:819
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
stm8.c:993
LOG_DEBUG("%d " TARGET_ADDR_FMT " %d %d", current, address,
stm8.c:1032
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT,
stm8.c:1298
LOG_DEBUG("%x " TARGET_ADDR_FMT " %x",
stm8.c:1419
LOG_ERROR("Unable to set breakpoint at address " TARGET_ADDR_FMT
stmqspi.c:1346
LOG_DEBUG("addr " TARGET_ADDR_FMT ", len 0x%08" PRIx32 ", crc 0x%08" PRIx32 " 0x%08" PRIx32,
stmsmi.c:547
LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
stmsmi.c:553
LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
target.c:1910
LOG_DEBUG("%c%c " TARGET_ADDR_FMT "-" TARGET_ADDR_FMT " (%" PRIu32 " bytes)",
target.c:1990
"address for working memory " TARGET_ADDR_FMT,
target.c:2001
"address for working memory " TARGET_ADDR_FMT,
target.c:2043
LOG_DEBUG("allocated new working area of %" PRIu32 " bytes at address " TARGET_ADDR_FMT,
target.c:2088
LOG_ERROR("failed to restore %" PRIu32 " bytes of working area at address " TARGET_ADDR_FMT,
target.c:2111
LOG_DEBUG("freed %" PRIu32 " bytes of working area at address " TARGET_ADDR_FMT,
target.c:2354
LOG_DEBUG("writing buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
target.c:2367
LOG_ERROR("address + size wrapped (" TARGET_ADDR_FMT ", 0x%08" PRIx32 ")",
target.c:2419
LOG_DEBUG("reading buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
target.c:2432
LOG_ERROR("address + size wrapped (" TARGET_ADDR_FMT ", 0x%08" PRIx32 ")",
target.c:2548
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2553
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2572
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2577
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2596
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%4.4" PRIx16,
target.c:2601
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2618
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2623
LOG_DEBUG("address: " TARGET_ADDR_FMT " failed",
target.c:2639
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2660
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2681
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16,
target.c:2701
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:2720
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
target.c:2741
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
target.c:2762
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx16,
target.c:2782
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%2.2" PRIx8,
target.c:3390
TARGET_ADDR_FMT ": ",
target.c:3782
command_print(CMD, "%u bytes written at address " TARGET_ADDR_FMT "",
target.c:3985
command_print(CMD, "address " TARGET_ADDR_FMT " length 0x%08zx",
target.c:4032
command_print(cmd, "Software breakpoint(IVA): addr=" TARGET_ADDR_FMT ", len=0x%x, orig_instr=0x%s",
target.c:4043
command_print(cmd, "Hybrid breakpoint(IVA): addr=" TARGET_ADDR_FMT ", len=0x%x, num=%u",
target.c:4049
command_print(cmd, "Hardware breakpoint(IVA): addr=" TARGET_ADDR_FMT ", len=0x%x, num=%u",
target.c:4069
command_print(cmd, "breakpoint set at " TARGET_ADDR_FMT "", addr);
target.c:4161
command_print(CMD, "Error during removal of breakpoint at address " TARGET_ADDR_FMT, addr);
target.c:4176
command_print(CMD, "address: " TARGET_ADDR_FMT
target.c:4263
command_print(CMD, "Error during removal of watchpoint at address " TARGET_ADDR_FMT, addr);
target.c:4287
command_print(CMD, "Physical address " TARGET_ADDR_FMT "", pa);
target.c:4591
LOG_DEBUG("read_memory: read at " TARGET_ADDR_FMT " with width=%u and count=%zu failed",
target.c:4756
LOG_ERROR("write_memory: write at " TARGET_ADDR_FMT " with width=%u and count=%zu failed",
tcl.c:103
"#%u : %s at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32
tcl.c:168
"flash '%s' found at " TARGET_ADDR_FMT,
tcl.c:196
TARGET_ADDR_FMT,
tcl.c:279
command_print(CMD, "erased address " TARGET_ADDR_FMT " (length %" PRIu32 ")"
tcl.c:581
LOG_WARNING("Start address " TARGET_ADDR_FMT
tcl.c:584
LOG_WARNING("Padding %" PRIu32 " bytes from " TARGET_ADDR_FMT,
tcl.c:614
LOG_INFO("Padding at " TARGET_ADDR_FMT " with %" PRIu32
tcl.c:649
"Verification error address " TARGET_ADDR_FMT
tcl.c:659
command_print(CMD, "wrote %" PRIu32 " bytes to " TARGET_ADDR_FMT
tcl.c:802
LOG_WARNING("Padding %" PRIu32 " bytes from " TARGET_ADDR_FMT,
tcl.c:825
LOG_INFO("Padding at " TARGET_ADDR_FMT " with %" PRIu32
tcl.c:1299
LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
tcl.c:1321
command_print(CMD, "#%d : %s (%s) at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32 ", "
tcl.c:1339
" base " TARGET_ADDR_FMT "\n"
tms470.c:156
TARGET_ADDR_FMT ".",
tms470.c:195
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
tms470.c:235
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
tms470.c:890
LOG_INFO("Writing %" PRIu32 " bytes starting at " TARGET_ADDR_FMT,
virtual.c:171
command_print_sameline(cmd, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
x86_32_common.c:127
LOG_ERROR("%s failed to calculate physical address from " TARGET_ADDR_FMT,
x86_32_common.c:228
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=" TARGET_ADDR_FMT,
x86_32_common.c:573
LOG_DEBUG("addr=" TARGET_ADDR_FMT ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:577
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=" TARGET_ADDR_FMT,
x86_32_common.c:593
LOG_ERROR("%s failed to calculate physical address from " TARGET_ADDR_FMT,
x86_32_common.c:604
LOG_ERROR("%s failed to read memory from physical address " TARGET_ADDR_FMT,
x86_32_common.c:616
LOG_ERROR("%s failed to read memory from address " TARGET_ADDR_FMT,
x86_32_common.c:630
LOG_DEBUG("addr=" TARGET_ADDR_FMT ", size=%" PRIu32 ", count=0x%" PRIx32 ", buf=%p",
x86_32_common.c:634
LOG_ERROR("%s invalid params count=0x%" PRIx32 ", buf=%p, addr=" TARGET_ADDR_FMT,
x86_32_common.c:649
LOG_ERROR("%s failed to calculate physical address from " TARGET_ADDR_FMT,
x86_32_common.c:659
LOG_ERROR("%s failed to write memory to physical address " TARGET_ADDR_FMT,
x86_32_common.c:672
LOG_ERROR("%s failed to write memory to address " TARGET_ADDR_FMT,
x86_32_common.c:861
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:872
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1012
LOG_USER("%s hardware breakpoint %" PRIu32 " removed from " TARGET_ADDR_FMT " (hwreg=%d)",
x86_32_common.c:1041
LOG_ERROR("%s software breakpoint error at " TARGET_ADDR_FMT ", check memory",
x86_32_common.c:1068
LOG_USER("%s software breakpoint %" PRIu32 " set at " TARGET_ADDR_FMT,
x86_32_common.c:1090
LOG_ERROR("%s software breakpoint remove error at " TARGET_ADDR_FMT ", check memory",
x86_32_common.c:1116
LOG_USER("%s software breakpoint %" PRIu32 " removed from " TARGET_ADDR_FMT,
x86_32_common.c:1125
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1133
LOG_ERROR("%s error setting hardware breakpoint at " TARGET_ADDR_FMT,
x86_32_common.c:1141
LOG_ERROR("%s error setting software breakpoint at " TARGET_ADDR_FMT,
x86_32_common.c:1155
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, bp->type, bp->address);
x86_32_common.c:1163
LOG_ERROR("%s error removing hardware breakpoint at " TARGET_ADDR_FMT,
x86_32_common.c:1169
LOG_ERROR("%s error removing software breakpoint at " TARGET_ADDR_FMT,
x86_32_common.c:1183
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, wp->rw, wp->address);
x86_32_common.c:1228
LOG_USER("'%s' watchpoint %d set at " TARGET_ADDR_FMT " with length %" PRIu32 " (hwreg=%d)",
x86_32_common.c:1239
LOG_DEBUG("type=%d, addr=" TARGET_ADDR_FMT, wp->rw, wp->address);
x86_32_common.c:1257
LOG_USER("'%s' watchpoint %d removed from " TARGET_ADDR_FMT " with length %" PRIu32 " (hwreg=%d)",
xmc1xxx.c:307
LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
xmc4xxx.c:769
LOG_INFO("Padding end of page @" TARGET_ADDR_FMT " by %d bytes",
xscale.c:1155
LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
xscale.c:1213
LOG_DEBUG("set breakpoint at " TARGET_ADDR_FMT "",
xscale.c:1778
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
xscale.c:1877
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
xtensa.c:580
LOG_TARGET_DEBUG(target, "PPTLB(" TARGET_ADDR_FMT ") -> 0x%08" PRIx32 " exec_acc %d",
xtensa.c:1603
"current=%d address=" TARGET_ADDR_FMT ", handle_breakpoints=%i, debug_execution=%i)",
xtensa.c:1732
LOG_TARGET_DEBUG(target, "current=%d, address=" TARGET_ADDR_FMT ", handle_breakpoints=%i",
xtensa.c:2017
LOG_DEBUG("address " TARGET_ADDR_FMT " not readable", address);
xtensa.c:2069
LOG_TARGET_WARNING(target, "Failed reading %d bytes at address "TARGET_ADDR_FMT,
xtensa.c:2112
LOG_WARNING("address " TARGET_ADDR_FMT " not writable", address);
xtensa.c:2239
LOG_TARGET_WARNING(target, "Failed writing %d bytes at address "TARGET_ADDR_FMT,
xtensa.c:2460
LOG_TARGET_DEBUG(target, "IHI %d, DHWBI %d for address " TARGET_ADDR_FMT,
xtensa.c:2466
"DHWBI second dcache line for address "TARGET_ADDR_FMT,
xtensa.c:2475
"IHI second icache line for address "TARGET_ADDR_FMT,
xtensa.c:2502
LOG_DEBUG("DHWB dcache line for address "TARGET_ADDR_FMT, address);
xtensa.c:2504
LOG_TARGET_DEBUG(target, "DHWB second dcache line for address "TARGET_ADDR_FMT, address + 4);
xtensa.c:2574
LOG_TARGET_DEBUG(target, "placed SW breakpoint %u @ " TARGET_ADDR_FMT,
xtensa.c:2591
LOG_TARGET_DEBUG(target, "placed HW breakpoint %u @ " TARGET_ADDR_FMT,
xtensa.c:2617
LOG_TARGET_DEBUG(target, "cleared SW breakpoint %u @ " TARGET_ADDR_FMT, slot, breakpoint->address);
xtensa.c:2632
LOG_TARGET_DEBUG(target, "cleared HW breakpoint %u @ " TARGET_ADDR_FMT, slot, breakpoint->address);
xtensa.c:2668
"Watchpoint with length %d on address " TARGET_ADDR_FMT
xtensa.c:2687
LOG_TARGET_DEBUG(target, "placed HW watchpoint @ " TARGET_ADDR_FMT,
xtensa.c:2702
LOG_TARGET_WARNING(target, "HW watchpoint " TARGET_ADDR_FMT " not found!", watchpoint->address);
xtensa.c:2707
LOG_TARGET_DEBUG(target, "cleared HW watchpoint @ " TARGET_ADDR_FMT,
xtensa.c:2834
LOG_ERROR("failed algorithm halted at 0x%" PRIx32 ", expected " TARGET_ADDR_FMT, pc, exit_point);
xtensa.c:2855
LOG_DEBUG("Check mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
xtensa.c:2857
LOG_DEBUG("Read mem param @ " TARGET_ADDR_FMT, mem_params[i].address);