Outline ![]()
Files ![]()
loading...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Xtensa application tracing module for OpenOCD *
* Copyright (C) 2017 Espressif Systems Ltd. *
***************************************************************************/
/*
How it works?
https://github.com/espressif/esp-idf/blob/master/components/app_trace/port/xtensa/port.c#L8
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/align.h>
#include <target/xtensa/xtensa.h>
#include <target/xtensa/xtensa_debug_module.h>
#include "esp_xtensa_apptrace.h"
/* TRAX is disabled, so we use its registers for our own purposes
* | 31..XXXXXX..24 | 23 .(host_connect). 23 | 22 .(host_data). 22| 21..(block_id)..15 | 14..(block_len)..0 |
*/
#define XTENSA_APPTRACE_CTRL_REG XDMREG_DELAYCNT
#define XTENSA_APPTRACE_BLOCK_ID_MSK 0x7FUL
#define XTENSA_APPTRACE_BLOCK_ID_MAX XTENSA_APPTRACE_BLOCK_ID_MSK
/* if non-zero then apptrace code entered the critical section and the value is an address of the
* critical section's exit point */
#define XTENSA_APPTRACE_STAT_REG XDMREG_TRIGGERPC
#define XTENSA_APPTRACE_BLOCK_LEN_MSK 0x7FFFUL
#define XTENSA_APPTRACE_BLOCK_LEN(_l_) ((_l_) & XTENSA_APPTRACE_BLOCK_LEN_MSK)
#define XTENSA_APPTRACE_BLOCK_LEN_GET(_v_) ((_v_) & XTENSA_APPTRACE_BLOCK_LEN_MSK)
#define XTENSA_APPTRACE_BLOCK_ID(_id_) (((_id_) & XTENSA_APPTRACE_BLOCK_ID_MSK) << 15)
#define XTENSA_APPTRACE_BLOCK_ID_GET(_v_) (((_v_) >> 15) & XTENSA_APPTRACE_BLOCK_ID_MSK)
#define XTENSA_APPTRACE_HOST_DATA BIT(22)
#define XTENSA_APPTRACE_HOST_CONNECT BIT(23)
static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target);
static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target);
static int esp_xtensa_apptrace_buffs_write(struct target *target,
uint32_t bufs_num,
uint32_t buf_sz[],
const uint8_t *bufs[],
uint32_t block_id,
bool ack,
bool data);
struct esp32_apptrace_hw esp_xtensa_apptrace_hw = {
.max_block_id = XTENSA_APPTRACE_BLOCK_ID_MAX,
.max_block_size_get = esp_xtensa_apptrace_block_max_size_get,
.status_reg_read = esp_xtensa_apptrace_status_reg_read,
.ctrl_reg_write = esp_xtensa_apptrace_ctrl_reg_write,
.ctrl_reg_read = esp_xtensa_apptrace_ctrl_reg_read,
.data_len_read = esp_xtensa_apptrace_data_len_read,
.data_read = esp_xtensa_apptrace_data_read,
.usr_block_max_size_get = esp_xtensa_apptrace_usr_block_max_size_get,
.buffs_write = esp_xtensa_apptrace_buffs_write,
.leave_trace_crit_section_start = esp_xtensa_apptrace_leave_crit_section_start,
.leave_trace_crit_section_stop = esp_xtensa_apptrace_leave_crit_section_stop,
};
uint32_t esp_xtensa_apptrace_block_max_size_get(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
struct xtensa_trace_status trace_status;
struct xtensa_trace_config trace_config;
uint32_t max_trace_block_sz;
int res = xtensa_dm_trace_status_read(&xtensa->dbg_mod, &trace_status);
if (res != ERROR_OK) {
LOG_ERROR("Failed to read TRAX status (%d)!", res);
return 0;
}
max_trace_block_sz = BIT(((trace_status.stat >> 8) & 0x1f) - 2) * 4;
res = xtensa_dm_trace_config_read(&xtensa->dbg_mod, &trace_config);
if (res != ERROR_OK) {
LOG_ERROR("Failed to read TRAX config (%d)!", res);
return 0;
}
LOG_DEBUG("ctrl=0x%" PRIx32 " memadrstart=0x%" PRIx32 " memadrend=0x%" PRIx32 " traxadr=0x%" PRIx32,
trace_config.ctrl,
trace_config.memaddr_start,
trace_config.memaddr_end,
trace_config.addr);
return max_trace_block_sz;
}
uint32_t esp_xtensa_apptrace_usr_block_max_size_get(struct target *target)
{
return esp_xtensa_apptrace_block_max_size_get(target) - sizeof(struct esp_apptrace_host2target_hdr);
}
int esp_xtensa_apptrace_data_len_read(struct target *target,
uint32_t *block_id,
uint32_t *len)
{
return esp_xtensa_apptrace_ctrl_reg_read(target, block_id, len, NULL);
}
int esp_xtensa_apptrace_usr_block_write(struct target *target,
uint32_t block_id,
const uint8_t *data,
uint32_t size)
{
return esp_apptrace_usr_block_write(&esp_xtensa_apptrace_hw, target, block_id, data, size);
}
static int esp_xtensa_apptrace_data_reverse_read(struct xtensa *xtensa,
uint32_t size,
uint8_t *buffer,
uint8_t *unal_bytes)
{
int res = 0;
uint32_t rd_sz = ALIGN_UP(size, 4);
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - rd_sz) / 4);
if (res != ERROR_OK)
return res;
if (!IS_ALIGNED(size, 4)) {
res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes);
if (res != ERROR_OK)
return res;
}
for (unsigned int i = size / 4; i != 0; i--) {
res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[(i - 1) * 4]);
if (res != ERROR_OK)
return res;
}
return ERROR_OK;
}
static int esp_xtensa_apptrace_data_normal_read(struct xtensa *xtensa,
uint32_t size,
uint8_t *buffer,
uint8_t *unal_bytes)
{
int res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0);
if (res != ERROR_OK)
return res;
for (unsigned int i = 0; i < size / 4; i++) {
res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[i * 4]);
if (res != ERROR_OK)
return res;
}
if (!IS_ALIGNED(size, 4)) {
res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes);
if (res != ERROR_OK)
return res;
}
return ERROR_OK;
}
int esp_xtensa_apptrace_data_read(struct target *target,
uint32_t size,
uint8_t *buffer,
uint32_t block_id,
bool ack)
{
struct xtensa *xtensa = target_to_xtensa(target);
int res;
uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT | XTENSA_APPTRACE_BLOCK_ID(block_id) |
XTENSA_APPTRACE_BLOCK_LEN(0);
uint8_t unal_bytes[4];
LOG_DEBUG("Read data on target (%s)", target_name(target));
if (xtensa->core_config->trace.reversed_mem_access)
res = esp_xtensa_apptrace_data_reverse_read(xtensa, size, buffer, unal_bytes);
else
res = esp_xtensa_apptrace_data_normal_read(xtensa, size, buffer, unal_bytes);
if (res != ERROR_OK)
return res;
if (ack) {
LOG_DEBUG("Ack block %" PRIu32 " target (%s)!", block_id, target_name(target));
res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
if (res != ERROR_OK)
return res;
}
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to exec JTAG queue!");
return res;
}
if (!IS_ALIGNED(size, 4)) {
/* copy the last unaligned bytes */
memcpy(buffer + ALIGN_DOWN(size, 4), unal_bytes, size & 0x3UL);
}
return ERROR_OK;
}
int esp_xtensa_apptrace_ctrl_reg_write(struct target *target,
uint32_t block_id,
uint32_t len,
bool conn,
bool data)
{
struct xtensa *xtensa = target_to_xtensa(target);
uint32_t tmp = (conn ? XTENSA_APPTRACE_HOST_CONNECT : 0) |
(data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) |
XTENSA_APPTRACE_BLOCK_LEN(len);
xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to exec JTAG queue!");
return res;
}
return ERROR_OK;
}
int esp_xtensa_apptrace_ctrl_reg_read(struct target *target,
uint32_t *block_id,
uint32_t *len,
bool *conn)
{
struct xtensa *xtensa = target_to_xtensa(target);
uint8_t tmp[4];
xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
uint32_t val = target_buffer_get_u32(target, tmp);
if (block_id)
*block_id = XTENSA_APPTRACE_BLOCK_ID_GET(val);
if (len)
*len = XTENSA_APPTRACE_BLOCK_LEN_GET(val);
if (conn)
*conn = val & XTENSA_APPTRACE_HOST_CONNECT;
return ERROR_OK;
}
int esp_xtensa_apptrace_status_reg_read(struct target *target, uint32_t *stat)
{
struct xtensa *xtensa = target_to_xtensa(target);
uint8_t tmp[4];
int res = xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_STAT_REG, tmp);
if (res != ERROR_OK)
return res;
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to exec JTAG queue!");
return res;
}
*stat = buf_get_u32(tmp, 0, 32);
return ERROR_OK;
}
int esp_xtensa_apptrace_status_reg_write(struct target *target, uint32_t stat)
{
struct xtensa *xtensa = target_to_xtensa(target);
xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_STAT_REG, stat);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to exec JTAG queue!");
return res;
}
return ERROR_OK;
}
static int esp_xtensa_swdbg_activate(struct target *target, int enab)
{
struct xtensa *xtensa = target_to_xtensa(target);
xtensa_queue_dbg_reg_write(xtensa, enab ? XDMREG_DCRSET : XDMREG_DCRCLR, OCDDCR_DEBUGSWACTIVE);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("%s: writing DCR failed!", target->cmd_name);
return res;
}
return ERROR_OK;
}
static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target)
{
/* TODO: not sure that we need this, but it seems that we fail to leave tracing critical
*section w/o this */
int res = esp_xtensa_swdbg_activate(target, 1 /*enable*/);
if (res != ERROR_OK) {
LOG_ERROR("Failed to activate SW debug (%d)!", res);
return res;
}
return ERROR_OK;
}
static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target)
{
int res = esp_xtensa_swdbg_activate(target, 0 /*disable*/);
if (res != ERROR_OK) {
LOG_ERROR("Failed to activate SW debug (%d)!", res);
return res;
}
return ERROR_OK;
}
static int esp_xtensa_apptrace_queue_reverse_write(struct target *target, uint32_t bufs_num,
uint32_t buf_sz[], const uint8_t *bufs[])
{
int res = ERROR_OK;
uint32_t cached_bytes = 0, total_sz = 0;
uint8_t cached_data8[sizeof(uint32_t)] = { 0 };
uint32_t cached_data32 = 0;
struct xtensa *xtensa = target_to_xtensa(target);
for (uint32_t i = 0; i < bufs_num; i++)
total_sz += buf_sz[i];
if (!IS_ALIGNED(total_sz, 4)) {
cached_bytes = sizeof(uint32_t) - (total_sz & 0x3UL);
total_sz = ALIGN_UP(total_sz, 4);
}
xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - total_sz) / 4);
for (uint32_t i = bufs_num; i > 0; i--) {
uint32_t bsz = buf_sz[i - 1];
const uint8_t *cur_buf = &bufs[i - 1][bsz];
uint32_t bytes_to_cache;
/* if there are cached bytes from the previous buffer, combine them with the last
* from the current buffer */
if (cached_bytes) {
if ((cached_bytes + bsz) < sizeof(uint32_t))
bytes_to_cache = bsz;
else
bytes_to_cache = sizeof(uint32_t) - cached_bytes;
memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache],
cur_buf - bytes_to_cache,
bytes_to_cache);
cached_data32 = target_buffer_get_u32(target, cached_data8);
cached_bytes += bytes_to_cache;
if (cached_bytes < sizeof(uint32_t))
continue;
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
if (res != ERROR_OK)
return res;
bsz -= bytes_to_cache;
cur_buf -= bytes_to_cache;
memset(cached_data8, 0x00, sizeof(cached_data8));
cached_bytes = 0;
}
/* write full dwords */
for (unsigned int k = bsz; k >= sizeof(uint32_t); k -= sizeof(uint32_t)) {
uint32_t temp = target_buffer_get_u32(target, cur_buf - sizeof(uint32_t));
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp);
if (res != ERROR_OK)
return res;
cur_buf -= sizeof(uint32_t);
}
/* if there are bytes to be cached (1..3) */
bytes_to_cache = bsz & 0x3UL;
if (bytes_to_cache > 0) {
if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) {
/* filling the cache buffer from the end to beginning */
uint32_t to_copy = sizeof(uint32_t) - cached_bytes;
memcpy(&cached_data8[0], cur_buf - to_copy, to_copy);
cached_data32 = target_buffer_get_u32(target, cached_data8);
/* write full word of cached bytes */
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
if (res != ERROR_OK)
return res;
/* cache remaining bytes */
memset(cached_data8, 0x00, sizeof(cached_data8));
cur_buf -= to_copy;
to_copy = bytes_to_cache + cached_bytes - sizeof(uint32_t);
memcpy(&cached_data8[sizeof(uint32_t) - to_copy], cur_buf - to_copy, to_copy);
cached_bytes = to_copy;
} else {
/* filling the cache buffer from the end to beginning */
memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache],
cur_buf - bytes_to_cache,
bytes_to_cache);
cached_bytes += bytes_to_cache;
}
}
}
return ERROR_OK;
}
static int esp_xtensa_apptrace_queue_normal_write(struct target *target, uint32_t bufs_num,
uint32_t buf_sz[], const uint8_t *bufs[])
{
int res = ERROR_OK;
uint32_t cached_bytes = 0;
uint8_t cached_data8[4] = { 0 };
uint32_t cached_data32 = 0;
struct xtensa *xtensa = target_to_xtensa(target);
/* | 1 | 2 | 1 | 2 | 4 |.......|
* | 4 | 4 | 4 | */
xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0);
for (unsigned int i = 0; i < bufs_num; i++) {
uint32_t bsz = buf_sz[i];
const uint8_t *cur_buf = bufs[i];
uint32_t bytes_to_cache;
/* if there are cached bytes from the previous buffer, combine them with the last
* from the current buffer */
if (cached_bytes) {
if ((cached_bytes + bsz) < sizeof(uint32_t))
bytes_to_cache = bsz;
else
bytes_to_cache = sizeof(uint32_t) - cached_bytes;
memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache);
cached_bytes += bytes_to_cache;
if (cached_bytes < sizeof(uint32_t))
continue;
cached_data32 = target_buffer_get_u32(target, cached_data8);
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
if (res != ERROR_OK)
return res;
bsz -= bytes_to_cache;
cur_buf += bytes_to_cache;
memset(cached_data8, 0x00, sizeof(cached_data8));
cached_bytes = 0;
}
/* write full dwords */
for (unsigned int k = 0; (k + sizeof(uint32_t)) <= bsz; k += sizeof(uint32_t)) {
uint32_t temp = target_buffer_get_u32(target, cur_buf);
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp);
if (res != ERROR_OK)
return res;
cur_buf += sizeof(uint32_t);
}
/* if there are bytes to be cached (1..3) */
bytes_to_cache = bsz & 0x3UL;
if (bytes_to_cache > 0) {
if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) {
memcpy(&cached_data8[0], cur_buf, sizeof(uint32_t) - cached_bytes);
cached_data32 = target_buffer_get_u32(target, cached_data8);
/* write full word of cached bytes */
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
if (res != ERROR_OK)
return res;
/* cache remaining bytes */
memset(cached_data8, 0x00, sizeof(cached_data8));
cur_buf += sizeof(uint32_t) - cached_bytes;
cached_bytes = bytes_to_cache + cached_bytes - sizeof(uint32_t);
memcpy(&cached_data8[0], cur_buf, cached_bytes);
} else {
memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache);
cached_bytes += bytes_to_cache;
}
}
}
if (cached_bytes) {
/* write remaining cached bytes */
cached_data32 = target_buffer_get_u32(target, cached_data8);
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
if (res != ERROR_OK)
return res;
}
return ERROR_OK;
}
static int esp_xtensa_apptrace_buffs_write(struct target *target,
uint32_t bufs_num,
uint32_t buf_sz[],
const uint8_t *bufs[],
uint32_t block_id,
bool ack,
bool data)
{
struct xtensa *xtensa = target_to_xtensa(target);
int res = ERROR_OK;
uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT |
(data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) |
XTENSA_APPTRACE_BLOCK_LEN(0);
if (xtensa->core_config->trace.reversed_mem_access)
res = esp_xtensa_apptrace_queue_reverse_write(target, bufs_num, buf_sz, bufs);
else
res = esp_xtensa_apptrace_queue_normal_write(target, bufs_num, buf_sz, bufs);
if (res != ERROR_OK)
return res;
if (ack) {
LOG_DEBUG("Ack block %" PRId32 " on target (%s)!", block_id, target_name(target));
res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
if (res != ERROR_OK)
return res;
}
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_ERROR("Failed to exec JTAG queue!");
return res;
}
return ERROR_OK;
}