OpenOCD
cache_set32() is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDcache_set32()

cache_set32() function

Syntax

static void cache_set32(struct target *target,     unsigned int index,     uint32_t data);

Arguments

target

index

data

References

LocationReferrerText
riscv-011.c:766
static void cache_set32(struct target *target, unsigned int index, uint32_t data)
riscv-011.c:784cache_set()
cache_set32(target, offset, data);
riscv-011.c:786cache_set()
cache_set32(target, offset + 1, data >> 32);
riscv-011.c:791cache_set_jump()
cache_set32(target, index,
riscv-011.c:799cache_set_load()
cache_set32(target, index, load(target, reg, ZERO, offset));
riscv-011.c:806cache_set_store()
cache_set32(target, index, store(target, reg, ZERO, offset));
riscv-011.c:1040read_remote_csr()
cache_set32(target, 0, csrr(S0, csr));
riscv-011.c:1063write_remote_csr()
cache_set32(target, 1, csrw(S0, csr));
riscv-011.c:1121execute_resume()
cache_set32(target, 1, csrw(S0, CSR_DPC));
riscv-011.c:1132execute_resume()
cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
riscv-011.c:1246register_read()
cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
riscv-011.c:1283register_write()
cache_set32(target, 1, csrw(S0, CSR_DSCRATCH0));
riscv-011.c:1303register_write()
cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
riscv-011.c:1308register_write()
cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
riscv-011.c:1310register_write()
cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
riscv-011.c:1314register_write()
cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
riscv-011.c:1359get_register()
cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
riscv-011.c:1364get_register()
cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
riscv-011.c:1366get_register()
cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
riscv-011.c:1395halt()
cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
riscv-011.c:1396halt()
cache_set32(target, 1, csrr(S0, CSR_MHARTID));
riscv-011.c:1397halt()
cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
riscv-011.c:1532examine()
cache_set32(target, 0, xori(S1, ZERO, -1));
riscv-011.c:1534examine()
cache_set32(target, 1, srli(S1, S1, 31));
riscv-011.c:1536examine()
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
riscv-011.c:1537examine()
cache_set32(target, 3, srli(S1, S1, 31));
riscv-011.c:1539examine()
cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
riscv-011.c:1542examine()
cache_set32(target, i, i * 0x01020304);
riscv-011.c:1997read_memory()
cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2000read_memory()
cache_set32(target, 1, lb(S1, S0, 0));
riscv-011.c:2001read_memory()
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2004read_memory()
cache_set32(target, 1, lh(S1, S0, 0));
riscv-011.c:2005read_memory()
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2008read_memory()
cache_set32(target, 1, lw(S1, S0, 0));
riscv-011.c:2009read_memory()
cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2135setup_write_memory()
cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2136setup_write_memory()
cache_set32(target, 1, sb(S0, T0, 0));
riscv-011.c:2139setup_write_memory()
cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2140setup_write_memory()
cache_set32(target, 1, sh(S0, T0, 0));
riscv-011.c:2143setup_write_memory()
cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2144setup_write_memory()
cache_set32(target, 1, sw(S0, T0, 0));
riscv-011.c:2150setup_write_memory()
cache_set32(target, 2, addi(T0, T0, size));

Call Tree

Type of cache_set32()
cache_set32()
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