S0 - syntax, references, description

References

Location	Text
opcodes.h:7	#define S0 8
riscv-011.c:1040	cache_set32(target, 0, csrr(S0, csr));
riscv-011.c:1041	cache_set_store(target, 1, S0, SLOT0);
riscv-011.c:1062	cache_set_load(target, 0, S0, SLOT0);
riscv-011.c:1063	cache_set32(target, 1, csrw(S0, csr));
riscv-011.c:1120	cache_set_load(target, 0, S0, SLOT0);
riscv-011.c:1121	cache_set32(target, 1, csrw(S0, CSR_DPC));
riscv-011.c:1131	cache_set_load(target, 0, S0, SLOT0);
riscv-011.c:1132	cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
riscv-011.c:1151	dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
riscv-011.c:1152	dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
riscv-011.c:1246	cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
riscv-011.c:1247	cache_set_store(target, 1, S0, SLOT0);
riscv-011.c:1281	if (number == S0) {
riscv-011.c:1282	cache_set_load(target, 0, S0, SLOT0);
riscv-011.c:1283	cache_set32(target, 1, csrw(S0, CSR_DSCRATCH0));
riscv-011.c:1286	cache_set_load(target, 0, S0, SLOT0);
riscv-011.c:1287	cache_set_store(target, 1, S0, SLOT_LAST);
riscv-011.c:1302	cache_set_load(target, i++, S0, SLOT1);
riscv-011.c:1303	cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
riscv-011.c:1313	cache_set_load(target, 0, S0, SLOT0);
riscv-011.c:1314	cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
riscv-011.c:1358	cache_set_load(target, i++, S0, SLOT1);
riscv-011.c:1359	cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
riscv-011.c:1396	cache_set32(target, 1, csrr(S0, CSR_MHARTID));
riscv-011.c:1397	cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
riscv-011.c:1616	if (reg == S0 \|\| reg == S1)
riscv-011.c:1627	scans_add_write_store(scans, 1, S0, SLOT0, false);
riscv-011.c:1632	scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
riscv-011.c:1639	scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
riscv-011.c:1778	reg = S0;
riscv-011.c:1966	dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
riscv-011.c:1967	dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
riscv-011.c:1997	cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2000	cache_set32(target, 1, lb(S1, S0, 0));
riscv-011.c:2004	cache_set32(target, 1, lh(S1, S0, 0));
riscv-011.c:2008	cache_set32(target, 1, lw(S1, S0, 0));
riscv-011.c:2135	cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2136	cache_set32(target, 1, sb(S0, T0, 0));
riscv-011.c:2139	cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2140	cache_set32(target, 1, sh(S0, T0, 0));
riscv-011.c:2143	cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
riscv-011.c:2144	cache_set32(target, 1, sw(S0, T0, 0));
riscv-013.c:1027	riscv_program_insert(&program, auipc(S0));
riscv-013.c:1035	riscv_program_insert(&program, sw(S0, S0, 0));
riscv-013.c:1327	riscv_program_insert(&program, fld(number - GDB_REGNO_FPR0, S0, 0));
riscv-013.c:1344	riscv_program_insert(&program, csrr(S0, CSR_VL));
riscv-013.c:1345	riscv_program_insert(&program, vsetvli(ZERO, S0, value));
riscv-013.c:1353	riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0));
riscv-013.c:1355	riscv_program_insert(&program, fmv_w_x(number - GDB_REGNO_FPR0, S0));
riscv-013.c:1363	if (riscv_program_insert(&program, vsetvli(ZERO, S0, vtype)) != ERROR_OK)
riscv-013.c:1366	riscv_program_csrw(&program, S0, number);
riscv-013.c:1440	riscv_program_insert(&program, fsd(number - GDB_REGNO_FPR0, S0,
riscv-013.c:1453	riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0));
riscv-013.c:1455	riscv_program_insert(&program, fmv_x_w(S0, number - GDB_REGNO_FPR0));
riscv-013.c:1458	riscv_program_csrr(&program, S0, number);
riscv-013.c:1977	riscv_program_insert(&program, vmv_x_s(S0, vnum));
riscv-013.c:1978	riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));
riscv-013.c:2036	riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));

S0 macro

Syntax

References