OpenOCD
DEBUG_RAM_START
is only used within OpenOCD.
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DEBUG_RAM_START
DEBUG_RAM_START macro
Syntax
from
riscv.c:43
#define
DEBUG_RAM_START
0x400
References
Location
Text
riscv-011.c:87
#define
DEBUG_RAM_START
0x400
riscv.c:43
#define
DEBUG_RAM_START
0x400
riscv-011.c:263
unsigned
int
offset
=
DEBUG_RAM_START
+
4
*
slot_offset
(
target
,
slot
)
;
riscv-011.c:270
unsigned
int
offset
=
DEBUG_RAM_START
+
4
*
slot_offset
(
target
,
slot
)
;
riscv-011.c:609
jal
(
0
,
(
uint32_t
)
(
DEBUG_ROM_RESUME
-
(
DEBUG_RAM_START
+
4
*
address
)
)
)
,
riscv-011.c:792
jal
(
0
,
(
uint32_t
)
(
DEBUG_ROM_RESUME
-
(
DEBUG_RAM_START
+
4
*
index
)
)
)
)
;
riscv-011.c:798
uint16_t
offset
=
DEBUG_RAM_START
+
4
*
slot_offset
(
target
,
slot
)
;
riscv-011.c:805
uint16_t
offset
=
DEBUG_RAM_START
+
4
*
slot_offset
(
target
,
slot
)
;
riscv-011.c:1016
jal
(
0
,
(
uint32_t
)
(
DEBUG_ROM_RESUME
-
(
DEBUG_RAM_START
+
4
*
index
)
)
)
,
riscv-011.c:1151
dram_write32
(
target
,
0
,
lw
(
S0
,
ZERO
,
DEBUG_RAM_START
+
16
)
,
false
)
;
riscv-011.c:1308
cache_set32
(
target
,
i
++
,
flw
(
number
-
GDB_REGNO_FPR0
,
0
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:1310
cache_set32
(
target
,
i
++
,
fld
(
number
-
GDB_REGNO_FPR0
,
0
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:1364
cache_set32
(
target
,
i
++
,
fsw
(
regid
-
GDB_REGNO_FPR0
,
0
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:1366
cache_set32
(
target
,
i
++
,
fsd
(
regid
-
GDB_REGNO_FPR0
,
0
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:1536
cache_set32
(
target
,
2
,
sw
(
S1
,
ZERO
,
DEBUG_RAM_START
)
)
;
riscv-011.c:1539
cache_set32
(
target
,
4
,
sw
(
S1
,
ZERO
,
DEBUG_RAM_START
+
4
)
)
;
riscv-011.c:1966
dram_write32
(
target
,
0
,
lw
(
S0
,
ZERO
,
DEBUG_RAM_START
+
16
)
,
false
)
;
riscv-011.c:1997
cache_set32
(
target
,
0
,
lw
(
S0
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:2001
cache_set32
(
target
,
2
,
sw
(
S1
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:2005
cache_set32
(
target
,
2
,
sw
(
S1
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:2009
cache_set32
(
target
,
2
,
sw
(
S1
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:2135
cache_set32
(
target
,
0
,
lb
(
S0
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:2139
cache_set32
(
target
,
0
,
lh
(
S0
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;
riscv-011.c:2143
cache_set32
(
target
,
0
,
lw
(
S0
,
ZERO
,
DEBUG_RAM_START
+
16
)
)
;