riscv011_info_t::dram_cache - syntax, references, description

References

Location	Referrer	Text
riscv-011.c:193		struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
riscv-011.c:769	cache_set32()	if (info->dram_cache[index].valid &&
riscv-011.c:770	cache_set32()	info->dram_cache[index].data == data) {
riscv-011.c:776	cache_set32()	info->dram_cache[index].data = data;
riscv-011.c:777	cache_set32()	info->dram_cache[index].valid = true;
riscv-011.c:778	cache_set32()	info->dram_cache[index].dirty = true;
riscv-011.c:822	cache_invalidate()	info->dram_cache[i].valid = false;
riscv-011.c:823	cache_invalidate()	info->dram_cache[i].dirty = false;
riscv-011.c:834	cache_clean()	info->dram_cache[i].valid = false;
riscv-011.c:835	cache_clean()	info->dram_cache[i].dirty = false;
riscv-011.c:845	cache_check()	if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
riscv-011.c:846	cache_check()	if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
riscv-011.c:872	cache_write()	if (info->dram_cache[i].dirty)
riscv-011.c:882	cache_write()	if (info->dram_cache[i].dirty) {
riscv-011.c:884	cache_write()	scans_add_write32(scans, i, info->dram_cache[i].data,
riscv-011.c:935	cache_write()	dram_write32(target, last, info->dram_cache[last].data, true);
riscv-011.c:937	cache_write()	dram_write32(target, i, info->dram_cache[i].data, false);
riscv-011.c:938	cache_write()	info->dram_cache[i].dirty = false;
riscv-011.c:955	cache_write()	info->dram_cache[i].dirty = false;
riscv-011.c:978	cache_write()	info->dram_cache[read_addr].data =
riscv-011.c:980	cache_write()	info->dram_cache[read_addr].valid = true;
riscv-011.c:994	cache_get32()	if (!info->dram_cache[address].valid) {
riscv-011.c:995	cache_get32()	info->dram_cache[address].data = dram_read32(target, address);
riscv-011.c:996	cache_get32()	info->dram_cache[address].valid = true;
riscv-011.c:998	cache_get32()	return info->dram_cache[address].data;