mips32_pracc_synchronize_cache() function

\b mips32_pracc_sync_cache Synchronize Caches to Make Instruction Writes Effective (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, Document Number: MD00086, Revision 2.00, June 9, 2003) When the instruction stream is written, the SYNCI instruction should be used in conjunction with other instructions to make the newly-written instructions effective. Explanation : A program that loads another program into memory is actually writing the D- side cache. The instructions it has loaded can't be executed until they reach the I-cache. After the instructions have been written, the loader should arrange to write back any containing D-cache line and invalidate any locations already in the I-cache. If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need to write back. In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, which does the whole job for a cache-line-sized chunk of the memory you just loaded: That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate. The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1.