OpenOCD
pracc_queue_info::isa is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDpracc_queue_info::isa

pracc_queue_info::isa field

Syntax

unsigned isa;

References

LocationReferrerText
mips32_pracc.h:48
unsigned isa;
mips32_pracc.c:304pracc_queue_init()
ctx->isa = ctx->ejtag_info->isa ? 1 : 0;
mips32_pracc.c:330pracc_add_li32()
pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, reg_num, UPPER16(data))); /* load only upper value */
mips32_pracc.c:332pracc_add_li32()
pracc_add(ctx, 0, MIPS32_ORI(ctx->isa, reg_num, 0, LOWER16(data))); /* load only lower */
mips32_pracc.c:334pracc_add_li32()
pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, reg_num, UPPER16(data))); /* load upper and lower */
mips32_pracc.c:335pracc_add_li32()
pracc_add(ctx, 0, MIPS32_ORI(ctx->isa, reg_num, reg_num, LOWER16(data)));
mips32_pracc.c:453mips32_pracc_read_u32()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:454mips32_pracc_read_u32()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper addr */
mips32_pracc.c:455mips32_pracc_read_u32()
pracc_add(&ctx, 0, MIPS32_LW(ctx.isa, 8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */
mips32_pracc.c:457mips32_pracc_read_u32()
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
mips32_pracc.c:459mips32_pracc_read_u32()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
mips32_pracc.c:461mips32_pracc_read_u32()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:462mips32_pracc_read_u32()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* move COP0 DeSave to $15 */
mips32_pracc.c:497mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:498mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 9, last_upper_base_addr)); /* upper memory addr to $9 */
mips32_pracc.c:503mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 9, upper_base_addr));
mips32_pracc.c:508mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_LW(ctx.isa, 8, LOWER16(addr), 9));
mips32_pracc.c:510mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_LHU(ctx.isa, 8, LOWER16(addr), 9));
mips32_pracc.c:512mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_LBU(ctx.isa, 8, LOWER16(addr), 9));
mips32_pracc.c:515mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
mips32_pracc.c:517mips32_pracc_read_mem()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + i * 4, 15));
mips32_pracc.c:523mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:524mips32_pracc_read_mem()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
mips32_pracc.c:557mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:559mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
mips32_pracc.c:560mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, cp0_reg, cp0_sel)); /* move cp0 reg / sel to $8 */
mips32_pracc.c:562mips32_cp0_read()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
mips32_pracc.c:563mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
mips32_pracc.c:564mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
mips32_pracc.c:565mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:566mips32_cp0_read()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
mips32_pracc.c:580mips32_cp0_write()
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, cp0_reg, cp0_sel)); /* write $15 to cp0 reg / sel */
mips32_pracc.c:582mips32_cp0_write()
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
mips32_pracc.c:583mips32_cp0_write()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:584mips32_cp0_write()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
mips32_pracc.c:596mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:597mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
mips32_pracc.c:598mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, cp1_c_reg)); /* move cp1c reg to $8 */
mips32_pracc.c:600mips32_cp1_control_read()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
mips32_pracc.c:601mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
mips32_pracc.c:602mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
mips32_pracc.c:603mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:604mips32_cp1_control_read()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
mips32_pracc.c:647mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:649mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_RDHWR(ctx.isa, 8, MIPS32_SYNCI_STEP)); /* load synci_step value to $8 */
mips32_pracc.c:652mips32_pracc_synchronize_cache()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
mips32_pracc.c:656mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:657mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
mips32_pracc.c:697mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, last_upper_base_addr)); /* load upper memory base addr to $15 */
mips32_pracc.c:702mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, upper_base_addr));
mips32_pracc.c:706mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_SYNCI(ctx.isa, LOWER16(start_addr), 15));
mips32_pracc.c:710mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_CACHE(ctx.isa, MIPS32_CACHE_D_HIT_WRITEBACK,
mips32_pracc.c:713mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_CACHE(ctx.isa, MIPS32_CACHE_I_HIT_INVALIDATE,
mips32_pracc.c:719mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* to start */
mips32_pracc.c:731mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
mips32_pracc.c:732mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:733mips32_pracc_synchronize_cache()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave*/
mips32_pracc.c:758mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, last_upper_base_addr));
mips32_pracc.c:763mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, upper_base_addr));
mips32_pracc.c:769mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_SW(ctx.isa, 8, LOWER16(addr), 15)); /* store word to mem */
mips32_pracc.c:773mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 0, *buf16)); /* load lower value */
mips32_pracc.c:774mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_SH(ctx.isa, 8, LOWER16(addr), 15)); /* store half word */
mips32_pracc.c:778mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 0, *buf8)); /* load lower value */
mips32_pracc.c:779mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_SB(ctx.isa, 8, LOWER16(addr), 15)); /* store byte */
mips32_pracc.c:787mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:788mips32_pracc_write_mem_generic()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
mips32_pracc.c:857mips32_pracc_write_mem()
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
mips32_pracc.c:859mips32_pracc_write_mem()
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
mips32_pracc.c:860mips32_pracc_write_mem()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips32_pracc.c:886mips32_pracc_write_regs()
MIPS32_MTC0(ctx.isa, 1, 12, 0), /* move $1 to status */
mips32_pracc.c:887mips32_pracc_write_regs()
MIPS32_MTLO(ctx.isa, 1), /* move $1 to lo */
mips32_pracc.c:888mips32_pracc_write_regs()
MIPS32_MTHI(ctx.isa, 1), /* move $1 to hi */
mips32_pracc.c:889mips32_pracc_write_regs()
MIPS32_MTC0(ctx.isa, 1, 8, 0), /* move $1 to badvaddr */
mips32_pracc.c:890mips32_pracc_write_regs()
MIPS32_MTC0(ctx.isa, 1, 13, 0), /* move $1 to cause*/
mips32_pracc.c:891mips32_pracc_write_regs()
MIPS32_MTC0(ctx.isa, 1, 24, 0), /* move $1 to depc (pc) */
mips32_pracc.c:920mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
mips32_pracc.c:931mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_MTC1(ctx.isa, 2, i));
mips32_pracc.c:932mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_MTHC1(ctx.isa, 3, i));
mips32_pracc.c:938mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_MTC1(ctx.isa, 2, i));
mips32_pracc.c:943mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
mips32_pracc.c:951mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
mips32_pracc.c:953mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((gprs[1]))));
mips32_pracc.c:955mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
mips32_pracc.c:957mips32_pracc_write_regs()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((gprs[1]))));
mips32_pracc.c:971mips32_pracc_store_regs_set_base_addr()
pracc_add(ctx, 0, MIPS32_MTC0(ctx->isa, 1, 31, 0));
mips32_pracc.c:973mips32_pracc_store_regs_set_base_addr()
pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, 1, PRACC_UPPER_BASE_ADDR));
mips32_pracc.c:983mips32_pracc_store_regs_gpr()
MIPS32_SW(ctx->isa, i, PRACC_OUT_OFFSET + offset_gpr + (i * 4), 1));
mips32_pracc.c:989mips32_pracc_store_regs_lohi()
MIPS32_MFLO(ctx->isa, 8), /* move lo to $8 */
mips32_pracc.c:990mips32_pracc_store_regs_lohi()
MIPS32_MFHI(ctx->isa, 8), /* move hi to $8 */
mips32_pracc.c:999mips32_pracc_store_regs_lohi()
MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
mips32_pracc.c:1007mips32_pracc_store_regs_cp0_context()
MIPS32_MFC0(ctx->isa, 8, 12, 0), /* move status to $8 */
mips32_pracc.c:1008mips32_pracc_store_regs_cp0_context()
MIPS32_MFC0(ctx->isa, 8, 8, 0), /* move badvaddr to $8 */
mips32_pracc.c:1009mips32_pracc_store_regs_cp0_context()
MIPS32_MFC0(ctx->isa, 8, 13, 0), /* move cause to $8 */
mips32_pracc.c:1010mips32_pracc_store_regs_cp0_context()
MIPS32_MFC0(ctx->isa, 8, 24, 0), /* move depc (pc) to $8 */
mips32_pracc.c:1021mips32_pracc_store_regs_cp0_context()
MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + offset, 1));
mips32_pracc.c:1032mips32_pracc_store_regs_restore()
pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 8, 31, 0));
mips32_pracc.c:1035mips32_pracc_store_regs_restore()
MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + 4, 1));
mips32_pracc.c:1038mips32_pracc_store_regs_restore()
pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 1, 31, 0));
mips32_pracc.c:1082mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
mips32_pracc.c:1084mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
mips32_pracc.c:1107mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, 31));
mips32_pracc.c:1109mips32_pracc_read_regs()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_fpcr, 1));
mips32_pracc.c:1112mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, 0));
mips32_pracc.c:1114mips32_pracc_read_regs()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_fpcr + 4, 1));
mips32_pracc.c:1124mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_MFC1(ctx.isa, 8, i));
mips32_pracc.c:1126mips32_pracc_read_regs()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset, 1));
mips32_pracc.c:1129mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_MFHC1(ctx.isa, 8, i));
mips32_pracc.c:1131mips32_pracc_read_regs()
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset + 4, 1));
mips32_pracc.c:1137mips32_pracc_read_regs()
MIPS32_SWC1(ctx.isa, i, PRACC_OUT_OFFSET + offset, 1));
mips32_pracc.c:1144mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
mips32_pracc.c:1146mips32_pracc_read_regs()
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
mips_ejtag.c:191mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 23, 0)); /* move COP0 Debug to $8 */
mips_ejtag.c:192mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, 0x0100)); /* set SSt bit in debug reg */
mips_ejtag.c:194mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_XORI(ctx.isa, 8, 8, 0x0100)); /* clear SSt bit in debug reg */
mips_ejtag.c:196mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 8, 23, 0)); /* move $8 to COP0 Debug */
mips_ejtag.c:197mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
mips_ejtag.c:198mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
mips_ejtag.c:199mips_ejtag_config_step()
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */

Data Use