MIPS32_LUI - syntax, references, description

References

Location	Text
mips32.h:734	#define MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
ath79.c:127	MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR),
ath79.c:129	MIPS32_LUI(0, 1, UPPER16(io_base)),
ath79.c:139	MIPS32_LUI(0, 2, UPPER16(1)),
ath79.c:144	MIPS32_LUI(0, 2, UPPER16(cs_high)),
ath79.c:153	MIPS32_LUI(0, 8, UPPER16((clock_low + 0))),
ath79.c:156	MIPS32_LUI(0, 9, UPPER16((clock_low + 1))),
ath79.c:159	MIPS32_LUI(0, 10, UPPER16((clock_high + 0))),
ath79.c:162	MIPS32_LUI(0, 11, UPPER16((clock_high + 1))),
ath79.c:212	MIPS32_LUI(0, 2, UPPER16(cs_high)),
cfi.c:1431	MIPS32_LUI(0, 9, 0), /* lui $t1, 0 */
mips32.c:1224	MIPS32_LUI(isa, 2, 0x04c1), /* lui $v0, 0x04c1 */
mips32.c:1709	pracc_add(ctx, 0, MIPS32_LUI(isa, 15, UPPER16(MIPS32_DSP_ENABLE)));
mips32.c:1787	pracc_add(&ctx, 0, MIPS32_LUI(isa, 15, PRACC_UPPER_BASE_ADDR));
mips32.c:1793	pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
mips32.c:1797	pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
mips32.c:1853	pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(val)));
mips32.c:1868	pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
mips32.c:1872	pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
mips32_pracc.c:330	pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, reg_num, UPPER16(data))); /* load only upper value */
mips32_pracc.c:334	pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, reg_num, UPPER16(data))); /* load upper and lower */
mips32_pracc.c:453	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:454	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper addr */
mips32_pracc.c:497	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:498	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 9, last_upper_base_addr)); /* upper memory addr to $9 */
mips32_pracc.c:503	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 9, upper_base_addr));
mips32_pracc.c:557	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:564	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
mips32_pracc.c:596	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:602	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
mips32_pracc.c:647	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
mips32_pracc.c:697	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, last_upper_base_addr)); /* load upper memory base addr to $15 */
mips32_pracc.c:702	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, upper_base_addr));
mips32_pracc.c:758	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, last_upper_base_addr));
mips32_pracc.c:763	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, upper_base_addr));
mips32_pracc.c:953	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((gprs[1]))));
mips32_pracc.c:973	pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, 1, PRACC_UPPER_BASE_ADDR));
mips32_pracc.c:1237	MIPS32_LUI(isa, 8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)),
mips32_pracc.c:1257	MIPS32_LUI(isa, 15, UPPER16(MIPS32_PRACC_TEXT)),
mips32_pracc.c:1279	MIPS32_LUI(isa, 15, UPPER16(source->address)), /* load addr of jump in $15 */
mips_ejtag.c:197	pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */

MIPS32_LUI macro

Syntax

Arguments

isa

reg

val

References