[R2COM]

guys seriously? can i get at least something from support team? am i not asking the legitimate question?

[R2COM]

i will put example here again, for example here is a linkers script i have (some portion of it):

SECTIONS {
__stacktop = ORIGIN(SRAM) + LENGTH(SRAM);
__data_load = LOADADDR(.data);
. = ORIGIN(SRAM);

.data ALIGN(4) : {
__data_start = .;
*(.data)
*(.data*)
. = ALIGN(4);
__data_end = .;
} >SRAM AT >FLASH

.bss ALIGN(4) (NOLOAD) : {
__bss_start = .;
/* PROVIDE(__bss_start__ = __bss_start); */
*(.bss)
*(.bss*)
. = ALIGN(4);
__bss_end = .;
PROVIDE(__bss_end__ = __bss_end);
*(.noinit)
*(.noinit*)
} >SRAM

. = ALIGN(4);
__heap_start = .;
}

 

do you see the commented out line in bold? so if this line is commented out – it causes the error which i talked about in first post.

but if that line is there, then all works. my question: WHY?

the startup code inside my .cpp file references __bss_start, so why is this stuff happening?

what is hidden from me?

• This reply was modified 3 years, 10 months ago by R2COM.

[R2COM]

so can i get an explanation from support team? what is happening under the hood what prevents me using custom names of memory sections?

 

why using “__bss_start” label together with my startup code was problematic and lead to problems described in first post but usage of name like “__bss_start__” is totally fine?

[R2COM]

i noticed that i can remove these errors by changing the name of sections inside my linker & startup from “__bss_start” to “__bss_start__” same thing with end macro.

can someone explain why it solves problem?

[R2COM]

here is another visual snapshot to the problem:

https://i.imgur.com/UxMR6lQ.jpg

so any ideas?

[R2COM]

it was such a mess that the only way to solve problem was to close VS, install 5.5 again, create new project, and copy in source files.

please make sure that update procedures are not painful!

[R2COM]

I updated to 5.5 and problem seems to be gone;

at least for this project, if something similar happens I’ll Repost here again

[R2COM]

wait a second…im not talking about support of product in a way how it operates etc; this is perpetual license, if i paid money i must have working software; the reason im contacting is the software stopped operating.

 

i know that i cant get technical support – but my question now is because of the fact that software which was paid for is not working!

[R2COM]

alright, the TIM3 really was not clocked properly, now the debug register shows up right.

 

regarding the reg scheme, id like it to be fixed by you guys maybe on some of the next updates… not that i cant live without that feature, its just…if its there already, it would be nice to have it implemented fully and up to hardware spec.

[R2COM]

by the way, why register scheme for CR2 is looking like its CR2 of TIM1 rather than CR2 of TIM3?

[R2COM]

As for checking, the TIM3 has following address according to manual:
<table class=”NormalTable”>
<tbody>
<tr>
<td width=”266″><span class=”fontstyle0″>0x4000 0400 – 0x4000 07FF </span></td>
<td width=”88″><span class=”fontstyle0″>1 KB </span></td>
<td width=”177″><span class=”fontstyle0″>TIM3</span></td>
</tr>
</tbody>
</table>
I am attaching snapshot with address info as well as register layout, you can see that TIM3 there starts at right addrexx 0x40000400,
However, the register scheme shows that it also has bits after bit 7 , but according to ref. manual TIM3->CR2 only has up to bit 7 used, others reserved. Not sure if its relevant or result of some copy-paste (maybe copy paste from CR2 of TIM1, who has those bits as i showed in another snapshot).

but, at least i can see that address of register is correct.

I also evaluated the command mon mdw 0x40000400 in debug console, and attaching what i got, i think i got all zeros as well.

then I did this in program code:

volatile int test = *((int *)0x40000400);

and during break, pointing cursor to “test” shows 0.

so..at this point its 100% not debugging related issue then…I assume?

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