__IO macro

Defines 'read / write' permissions

Syntax

from core_cm4.h:227

#define __IO volatile

Examples

__IO is referenced by 666 libraries and example projects.

References

Location	Text
core_cm4.h:227	#define __IO volatile /!< Defines 'read / write' permissions /
stm32f401xc.h:153	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f401xc.h:154	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f401xc.h:155	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f401xc.h:156	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f401xc.h:157	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f401xc.h:158	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f401xc.h:159	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f401xc.h:160	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f401xc.h:161	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f401xc.h:162	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f401xc.h:163	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f401xc.h:164	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f401xc.h:165	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f401xc.h:166	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f401xc.h:167	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f401xc.h:168	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f401xc.h:169	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f401xc.h:170	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f401xc.h:171	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f401xc.h:172	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f401xc.h:177	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f401xc.h:178	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f401xc.h:179	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f401xc.h:189	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f401xc.h:190	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f401xc.h:193	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f401xc.h:202	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f401xc.h:203	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f401xc.h:204	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f401xc.h:205	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f401xc.h:215	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f401xc.h:216	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f401xc.h:217	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f401xc.h:218	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f401xc.h:219	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f401xc.h:220	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f401xc.h:225	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f401xc.h:226	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f401xc.h:227	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f401xc.h:228	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f401xc.h:237	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f401xc.h:238	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f401xc.h:239	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f401xc.h:240	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f401xc.h:241	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f401xc.h:242	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f401xc.h:251	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f401xc.h:252	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f401xc.h:253	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f401xc.h:254	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f401xc.h:255	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f401xc.h:256	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f401xc.h:257	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f401xc.h:266	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f401xc.h:267	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f401xc.h:268	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f401xc.h:269	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f401xc.h:270	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f401xc.h:271	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f401xc.h:272	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f401xc.h:273	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f401xc.h:274	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f401xc.h:283	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f401xc.h:284	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f401xc.h:285	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f401xc.h:287	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f401xc.h:296	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f401xc.h:297	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f401xc.h:298	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f401xc.h:299	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f401xc.h:300	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f401xc.h:301	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f401xc.h:302	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f401xc.h:303	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f401xc.h:304	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f401xc.h:305	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f401xc.h:314	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f401xc.h:315	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f401xc.h:316	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f401xc.h:317	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f401xc.h:327	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f401xc.h:328	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f401xc.h:337	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f401xc.h:338	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f401xc.h:339	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f401xc.h:340	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f401xc.h:341	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f401xc.h:342	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f401xc.h:343	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f401xc.h:345	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f401xc.h:346	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f401xc.h:348	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f401xc.h:349	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f401xc.h:350	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f401xc.h:352	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f401xc.h:353	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f401xc.h:355	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f401xc.h:356	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f401xc.h:357	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f401xc.h:359	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f401xc.h:360	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f401xc.h:362	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f401xc.h:363	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f401xc.h:365	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f401xc.h:366	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f401xc.h:368	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f401xc.h:377	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f401xc.h:378	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f401xc.h:379	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f401xc.h:380	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f401xc.h:381	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f401xc.h:382	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f401xc.h:383	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f401xc.h:384	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f401xc.h:385	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f401xc.h:386	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f401xc.h:387	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f401xc.h:388	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f401xc.h:389	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f401xc.h:390	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f401xc.h:391	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f401xc.h:392	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f401xc.h:393	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f401xc.h:394	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f401xc.h:395	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f401xc.h:397	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f401xc.h:398	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f401xc.h:399	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f401xc.h:400	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f401xc.h:401	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f401xc.h:402	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f401xc.h:403	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f401xc.h:404	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f401xc.h:405	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f401xc.h:406	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f401xc.h:407	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f401xc.h:408	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f401xc.h:409	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f401xc.h:410	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f401xc.h:411	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f401xc.h:412	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f401xc.h:413	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f401xc.h:414	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f401xc.h:415	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f401xc.h:416	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f401xc.h:425	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f401xc.h:426	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f401xc.h:427	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f401xc.h:428	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f401xc.h:429	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f401xc.h:430	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f401xc.h:431	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f401xc.h:432	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f401xc.h:433	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f401xc.h:434	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f401xc.h:435	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f401xc.h:436	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f401xc.h:437	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f401xc.h:438	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f401xc.h:439	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f401xc.h:440	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f401xc.h:442	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f401xc.h:444	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f401xc.h:453	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f401xc.h:454	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f401xc.h:455	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f401xc.h:456	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f401xc.h:457	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f401xc.h:458	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f401xc.h:459	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f401xc.h:460	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f401xc.h:461	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f401xc.h:471	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f401xc.h:472	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f401xc.h:473	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f401xc.h:474	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f401xc.h:475	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f401xc.h:476	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f401xc.h:477	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f401xc.h:478	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f401xc.h:479	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f401xc.h:480	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f401xc.h:481	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f401xc.h:482	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f401xc.h:483	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f401xc.h:484	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f401xc.h:485	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f401xc.h:486	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f401xc.h:487	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f401xc.h:488	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f401xc.h:489	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f401xc.h:490	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f401xc.h:491	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f401xc.h:500	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f401xc.h:501	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f401xc.h:502	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f401xc.h:503	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f401xc.h:504	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f401xc.h:505	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f401xc.h:506	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f401xc.h:515	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f401xc.h:516	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f401xc.h:517	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f401xc.h:524	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f401xc.h:525	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f401xc.h:526	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f401xc.h:527	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f401xc.h:528	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f401xc.h:529	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f401xc.h:530	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f401xc.h:531	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f401xc.h:532	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f401xc.h:533	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f401xc.h:534	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f401xc.h:535	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f401xc.h:537	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f401xc.h:538	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f401xc.h:540	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f401xc.h:541	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f401xc.h:549	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f401xc.h:550	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f401xc.h:551	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f401xc.h:553	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f401xc.h:554	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f401xc.h:555	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f401xc.h:556	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f401xc.h:559	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f401xc.h:560	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f401xc.h:561	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f401xc.h:562	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f401xc.h:563	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f401xc.h:564	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f401xc.h:566	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f401xc.h:568	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f401xc.h:576	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f401xc.h:578	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f401xc.h:580	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f401xc.h:581	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f401xc.h:582	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f401xc.h:591	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f401xc.h:593	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f401xc.h:595	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f401xc.h:596	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f401xc.h:605	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f401xc.h:606	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f401xc.h:607	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f401xc.h:609	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f401xc.h:610	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f401xc.h:611	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f401xc.h:619	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f401xc.h:620	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f401xc.h:621	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f401xc.h:622	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f401xc.h:623	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f401xc.h:624	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f401xe.h:153	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f401xe.h:154	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f401xe.h:155	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f401xe.h:156	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f401xe.h:157	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f401xe.h:158	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f401xe.h:159	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f401xe.h:160	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f401xe.h:161	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f401xe.h:162	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f401xe.h:163	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f401xe.h:164	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f401xe.h:165	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f401xe.h:166	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f401xe.h:167	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f401xe.h:168	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f401xe.h:169	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f401xe.h:170	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f401xe.h:171	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f401xe.h:172	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f401xe.h:177	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f401xe.h:178	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f401xe.h:179	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f401xe.h:189	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f401xe.h:190	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f401xe.h:193	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f401xe.h:202	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f401xe.h:203	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f401xe.h:204	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f401xe.h:205	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f401xe.h:215	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f401xe.h:216	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f401xe.h:217	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f401xe.h:218	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f401xe.h:219	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f401xe.h:220	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f401xe.h:225	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f401xe.h:226	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f401xe.h:227	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f401xe.h:228	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f401xe.h:237	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f401xe.h:238	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f401xe.h:239	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f401xe.h:240	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f401xe.h:241	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f401xe.h:242	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f401xe.h:251	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f401xe.h:252	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f401xe.h:253	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f401xe.h:254	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f401xe.h:255	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f401xe.h:256	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f401xe.h:257	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f401xe.h:266	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f401xe.h:267	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f401xe.h:268	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f401xe.h:269	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f401xe.h:270	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f401xe.h:271	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f401xe.h:272	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f401xe.h:273	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f401xe.h:274	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f401xe.h:283	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f401xe.h:284	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f401xe.h:285	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f401xe.h:287	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f401xe.h:296	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f401xe.h:297	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f401xe.h:298	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f401xe.h:299	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f401xe.h:300	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f401xe.h:301	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f401xe.h:302	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f401xe.h:303	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f401xe.h:304	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f401xe.h:305	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f401xe.h:314	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f401xe.h:315	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f401xe.h:316	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f401xe.h:317	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f401xe.h:327	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f401xe.h:328	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f401xe.h:337	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f401xe.h:338	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f401xe.h:339	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f401xe.h:340	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f401xe.h:341	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f401xe.h:342	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f401xe.h:343	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f401xe.h:345	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f401xe.h:346	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f401xe.h:348	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f401xe.h:349	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f401xe.h:350	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f401xe.h:352	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f401xe.h:353	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f401xe.h:355	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f401xe.h:356	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f401xe.h:357	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f401xe.h:359	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f401xe.h:360	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f401xe.h:362	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f401xe.h:363	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f401xe.h:365	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f401xe.h:366	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f401xe.h:368	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f401xe.h:377	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f401xe.h:378	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f401xe.h:379	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f401xe.h:380	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f401xe.h:381	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f401xe.h:382	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f401xe.h:383	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f401xe.h:384	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f401xe.h:385	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f401xe.h:386	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f401xe.h:387	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f401xe.h:388	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f401xe.h:389	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f401xe.h:390	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f401xe.h:391	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f401xe.h:392	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f401xe.h:393	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f401xe.h:394	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f401xe.h:395	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f401xe.h:397	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f401xe.h:398	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f401xe.h:399	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f401xe.h:400	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f401xe.h:401	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f401xe.h:402	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f401xe.h:403	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f401xe.h:404	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f401xe.h:405	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f401xe.h:406	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f401xe.h:407	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f401xe.h:408	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f401xe.h:409	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f401xe.h:410	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f401xe.h:411	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f401xe.h:412	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f401xe.h:413	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f401xe.h:414	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f401xe.h:415	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f401xe.h:416	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f401xe.h:425	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f401xe.h:426	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f401xe.h:427	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f401xe.h:428	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f401xe.h:429	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f401xe.h:430	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f401xe.h:431	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f401xe.h:432	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f401xe.h:433	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f401xe.h:434	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f401xe.h:435	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f401xe.h:436	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f401xe.h:437	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f401xe.h:438	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f401xe.h:439	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f401xe.h:440	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f401xe.h:442	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f401xe.h:444	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f401xe.h:453	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f401xe.h:454	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f401xe.h:455	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f401xe.h:456	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f401xe.h:457	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f401xe.h:458	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f401xe.h:459	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f401xe.h:460	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f401xe.h:461	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f401xe.h:471	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f401xe.h:472	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f401xe.h:473	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f401xe.h:474	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f401xe.h:475	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f401xe.h:476	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f401xe.h:477	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f401xe.h:478	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f401xe.h:479	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f401xe.h:480	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f401xe.h:481	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f401xe.h:482	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f401xe.h:483	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f401xe.h:484	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f401xe.h:485	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f401xe.h:486	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f401xe.h:487	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f401xe.h:488	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f401xe.h:489	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f401xe.h:490	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f401xe.h:491	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f401xe.h:500	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f401xe.h:501	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f401xe.h:502	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f401xe.h:503	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f401xe.h:504	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f401xe.h:505	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f401xe.h:506	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f401xe.h:515	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f401xe.h:516	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f401xe.h:517	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f401xe.h:524	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f401xe.h:525	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f401xe.h:526	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f401xe.h:527	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f401xe.h:528	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f401xe.h:529	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f401xe.h:530	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f401xe.h:531	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f401xe.h:532	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f401xe.h:533	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f401xe.h:534	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f401xe.h:535	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f401xe.h:537	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f401xe.h:538	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f401xe.h:540	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f401xe.h:541	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f401xe.h:549	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f401xe.h:550	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f401xe.h:551	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f401xe.h:553	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f401xe.h:554	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f401xe.h:555	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f401xe.h:556	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f401xe.h:559	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f401xe.h:560	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f401xe.h:561	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f401xe.h:562	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f401xe.h:563	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f401xe.h:564	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f401xe.h:566	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f401xe.h:568	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f401xe.h:576	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f401xe.h:578	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f401xe.h:580	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f401xe.h:581	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f401xe.h:582	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f401xe.h:591	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f401xe.h:593	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f401xe.h:595	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f401xe.h:596	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f401xe.h:605	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f401xe.h:606	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f401xe.h:607	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f401xe.h:609	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f401xe.h:610	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f401xe.h:611	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f401xe.h:619	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f401xe.h:620	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f401xe.h:621	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f401xe.h:622	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f401xe.h:623	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f401xe.h:624	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f407xx.h:180	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f407xx.h:181	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f407xx.h:182	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f407xx.h:183	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f407xx.h:184	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f407xx.h:185	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f407xx.h:186	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f407xx.h:187	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f407xx.h:188	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f407xx.h:189	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f407xx.h:190	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f407xx.h:191	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f407xx.h:192	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f407xx.h:193	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f407xx.h:194	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f407xx.h:195	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f407xx.h:196	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f407xx.h:197	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f407xx.h:198	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f407xx.h:199	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f407xx.h:204	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f407xx.h:205	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f407xx.h:206	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f407xx.h:217	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f407xx.h:218	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f407xx.h:219	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f407xx.h:220	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f407xx.h:229	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f407xx.h:230	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f407xx.h:231	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f407xx.h:232	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f407xx.h:241	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f407xx.h:242	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f407xx.h:251	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f407xx.h:252	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f407xx.h:253	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f407xx.h:254	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f407xx.h:255	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f407xx.h:256	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f407xx.h:257	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f407xx.h:258	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f407xx.h:263	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f407xx.h:264	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f407xx.h:266	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f407xx.h:268	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f407xx.h:270	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f407xx.h:281	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f407xx.h:282	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f407xx.h:285	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f407xx.h:294	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f407xx.h:295	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f407xx.h:296	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f407xx.h:297	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f407xx.h:298	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f407xx.h:299	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f407xx.h:300	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f407xx.h:301	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f407xx.h:302	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f407xx.h:303	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f407xx.h:304	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f407xx.h:305	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f407xx.h:306	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f407xx.h:307	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f407xx.h:316	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f407xx.h:317	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f407xx.h:318	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f407xx.h:319	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f407xx.h:328	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f407xx.h:329	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f407xx.h:330	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f407xx.h:331	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f407xx.h:332	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f407xx.h:333	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f407xx.h:334	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f407xx.h:335	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f407xx.h:336	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f407xx.h:337	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f407xx.h:338	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f407xx.h:347	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f407xx.h:348	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f407xx.h:349	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f407xx.h:350	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f407xx.h:351	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f407xx.h:352	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f407xx.h:357	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f407xx.h:358	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f407xx.h:359	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f407xx.h:360	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f407xx.h:369	__IO uint32_t MACCR;
stm32f407xx.h:370	__IO uint32_t MACFFR;
stm32f407xx.h:371	__IO uint32_t MACHTHR;
stm32f407xx.h:372	__IO uint32_t MACHTLR;
stm32f407xx.h:373	__IO uint32_t MACMIIAR;
stm32f407xx.h:374	__IO uint32_t MACMIIDR;
stm32f407xx.h:375	__IO uint32_t MACFCR;
stm32f407xx.h:376	__IO uint32_t MACVLANTR; /* 8 */
stm32f407xx.h:378	__IO uint32_t MACRWUFFR; /* 11 */
stm32f407xx.h:379	__IO uint32_t MACPMTCSR;
stm32f407xx.h:381	__IO uint32_t MACDBGR;
stm32f407xx.h:382	__IO uint32_t MACSR; /* 15 */
stm32f407xx.h:383	__IO uint32_t MACIMR;
stm32f407xx.h:384	__IO uint32_t MACA0HR;
stm32f407xx.h:385	__IO uint32_t MACA0LR;
stm32f407xx.h:386	__IO uint32_t MACA1HR;
stm32f407xx.h:387	__IO uint32_t MACA1LR;
stm32f407xx.h:388	__IO uint32_t MACA2HR;
stm32f407xx.h:389	__IO uint32_t MACA2LR;
stm32f407xx.h:390	__IO uint32_t MACA3HR;
stm32f407xx.h:391	__IO uint32_t MACA3LR; /* 24 */
stm32f407xx.h:393	__IO uint32_t MMCCR; /* 65 */
stm32f407xx.h:394	__IO uint32_t MMCRIR;
stm32f407xx.h:395	__IO uint32_t MMCTIR;
stm32f407xx.h:396	__IO uint32_t MMCRIMR;
stm32f407xx.h:397	__IO uint32_t MMCTIMR; /* 69 */
stm32f407xx.h:399	__IO uint32_t MMCTGFSCCR; /* 84 */
stm32f407xx.h:400	__IO uint32_t MMCTGFMSCCR;
stm32f407xx.h:402	__IO uint32_t MMCTGFCR;
stm32f407xx.h:404	__IO uint32_t MMCRFCECR;
stm32f407xx.h:405	__IO uint32_t MMCRFAECR;
stm32f407xx.h:407	__IO uint32_t MMCRGUFCR;
stm32f407xx.h:409	__IO uint32_t PTPTSCR;
stm32f407xx.h:410	__IO uint32_t PTPSSIR;
stm32f407xx.h:411	__IO uint32_t PTPTSHR;
stm32f407xx.h:412	__IO uint32_t PTPTSLR;
stm32f407xx.h:413	__IO uint32_t PTPTSHUR;
stm32f407xx.h:414	__IO uint32_t PTPTSLUR;
stm32f407xx.h:415	__IO uint32_t PTPTSAR;
stm32f407xx.h:416	__IO uint32_t PTPTTHR;
stm32f407xx.h:417	__IO uint32_t PTPTTLR;
stm32f407xx.h:418	__IO uint32_t RESERVED8;
stm32f407xx.h:419	__IO uint32_t PTPTSSR;
stm32f407xx.h:421	__IO uint32_t DMABMR;
stm32f407xx.h:422	__IO uint32_t DMATPDR;
stm32f407xx.h:423	__IO uint32_t DMARPDR;
stm32f407xx.h:424	__IO uint32_t DMARDLAR;
stm32f407xx.h:425	__IO uint32_t DMATDLAR;
stm32f407xx.h:426	__IO uint32_t DMASR;
stm32f407xx.h:427	__IO uint32_t DMAOMR;
stm32f407xx.h:428	__IO uint32_t DMAIER;
stm32f407xx.h:429	__IO uint32_t DMAMFBOCR;
stm32f407xx.h:430	__IO uint32_t DMARSWTR;
stm32f407xx.h:432	__IO uint32_t DMACHTDR;
stm32f407xx.h:433	__IO uint32_t DMACHRDR;
stm32f407xx.h:434	__IO uint32_t DMACHTBAR;
stm32f407xx.h:435	__IO uint32_t DMACHRBAR;
stm32f407xx.h:444	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f407xx.h:445	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f407xx.h:446	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f407xx.h:447	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f407xx.h:448	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f407xx.h:449	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f407xx.h:458	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f407xx.h:459	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f407xx.h:460	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f407xx.h:461	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f407xx.h:462	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f407xx.h:463	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f407xx.h:464	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f407xx.h:475	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f407xx.h:484	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f407xx.h:493	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
stm32f407xx.h:494	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
stm32f407xx.h:495	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
stm32f407xx.h:496	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
stm32f407xx.h:498	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
stm32f407xx.h:501	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
stm32f407xx.h:502	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
stm32f407xx.h:503	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
stm32f407xx.h:504	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
stm32f407xx.h:506	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
stm32f407xx.h:515	__IO uint32_t PCR4; /!< PC Card control register 4, Address offset: 0xA0 /
stm32f407xx.h:516	__IO uint32_t SR4; /!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 /
stm32f407xx.h:517	__IO uint32_t PMEM4; /!< PC Card Common memory space timing register 4, Address offset: 0xA8 /
stm32f407xx.h:518	__IO uint32_t PATT4; /!< PC Card Attribute memory space timing register 4, Address offset: 0xAC /
stm32f407xx.h:519	__IO uint32_t PIO4; /!< PC Card I/O space timing register 4, Address offset: 0xB0 /
stm32f407xx.h:528	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f407xx.h:529	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f407xx.h:530	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f407xx.h:531	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f407xx.h:532	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f407xx.h:533	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f407xx.h:534	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f407xx.h:535	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f407xx.h:536	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f407xx.h:545	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f407xx.h:546	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f407xx.h:547	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f407xx.h:549	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f407xx.h:558	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f407xx.h:559	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f407xx.h:560	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f407xx.h:561	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f407xx.h:562	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f407xx.h:563	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f407xx.h:564	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f407xx.h:565	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f407xx.h:566	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f407xx.h:575	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f407xx.h:576	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f407xx.h:577	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f407xx.h:578	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f407xx.h:588	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f407xx.h:589	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f407xx.h:598	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f407xx.h:599	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f407xx.h:600	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f407xx.h:601	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f407xx.h:602	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f407xx.h:603	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f407xx.h:604	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f407xx.h:606	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f407xx.h:607	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f407xx.h:609	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f407xx.h:610	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f407xx.h:611	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f407xx.h:613	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f407xx.h:614	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f407xx.h:616	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f407xx.h:617	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f407xx.h:618	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f407xx.h:620	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f407xx.h:621	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f407xx.h:623	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f407xx.h:624	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f407xx.h:626	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f407xx.h:627	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f407xx.h:636	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f407xx.h:637	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f407xx.h:638	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f407xx.h:639	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f407xx.h:640	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f407xx.h:641	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f407xx.h:642	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f407xx.h:643	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f407xx.h:644	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f407xx.h:645	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f407xx.h:646	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f407xx.h:647	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f407xx.h:648	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f407xx.h:649	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f407xx.h:650	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f407xx.h:651	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f407xx.h:652	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f407xx.h:653	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f407xx.h:654	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f407xx.h:656	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f407xx.h:657	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f407xx.h:658	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f407xx.h:659	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f407xx.h:660	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f407xx.h:661	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f407xx.h:662	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f407xx.h:663	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f407xx.h:664	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f407xx.h:665	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f407xx.h:666	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f407xx.h:667	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f407xx.h:668	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f407xx.h:669	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f407xx.h:670	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f407xx.h:671	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f407xx.h:672	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f407xx.h:673	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f407xx.h:674	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f407xx.h:675	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f407xx.h:684	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f407xx.h:685	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f407xx.h:686	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f407xx.h:687	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f407xx.h:688	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f407xx.h:689	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f407xx.h:690	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f407xx.h:691	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f407xx.h:692	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f407xx.h:693	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f407xx.h:694	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f407xx.h:695	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f407xx.h:696	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f407xx.h:697	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f407xx.h:698	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f407xx.h:699	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f407xx.h:701	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f407xx.h:703	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f407xx.h:712	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f407xx.h:713	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f407xx.h:714	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f407xx.h:715	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f407xx.h:716	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f407xx.h:717	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f407xx.h:718	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f407xx.h:719	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f407xx.h:720	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f407xx.h:730	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f407xx.h:731	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f407xx.h:732	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f407xx.h:733	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f407xx.h:734	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f407xx.h:735	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f407xx.h:736	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f407xx.h:737	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f407xx.h:738	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f407xx.h:739	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f407xx.h:740	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f407xx.h:741	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f407xx.h:742	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f407xx.h:743	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f407xx.h:744	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f407xx.h:745	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f407xx.h:746	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f407xx.h:747	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f407xx.h:748	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f407xx.h:749	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f407xx.h:750	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f407xx.h:759	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f407xx.h:760	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f407xx.h:761	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f407xx.h:762	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f407xx.h:763	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f407xx.h:764	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f407xx.h:765	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f407xx.h:774	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f407xx.h:775	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f407xx.h:776	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f407xx.h:785	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f407xx.h:786	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f407xx.h:787	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f407xx.h:795	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f407xx.h:796	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f407xx.h:797	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f407xx.h:798	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f407xx.h:799	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f407xx.h:800	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f407xx.h:801	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f407xx.h:802	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f407xx.h:803	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f407xx.h:804	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f407xx.h:805	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f407xx.h:806	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f407xx.h:808	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f407xx.h:809	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f407xx.h:811	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f407xx.h:812	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f407xx.h:820	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f407xx.h:821	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f407xx.h:822	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f407xx.h:824	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f407xx.h:825	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f407xx.h:826	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f407xx.h:827	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f407xx.h:830	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f407xx.h:831	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f407xx.h:832	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f407xx.h:833	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f407xx.h:834	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f407xx.h:835	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f407xx.h:837	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f407xx.h:839	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f407xx.h:847	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f407xx.h:849	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f407xx.h:851	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f407xx.h:852	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f407xx.h:853	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f407xx.h:862	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f407xx.h:864	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f407xx.h:866	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f407xx.h:867	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f407xx.h:876	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f407xx.h:877	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f407xx.h:878	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f407xx.h:880	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f407xx.h:881	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f407xx.h:882	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f407xx.h:890	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f407xx.h:891	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f407xx.h:892	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f407xx.h:893	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f407xx.h:894	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f407xx.h:895	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f410rx.h:149	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f410rx.h:150	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f410rx.h:151	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f410rx.h:152	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f410rx.h:153	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f410rx.h:154	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f410rx.h:155	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f410rx.h:156	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f410rx.h:157	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f410rx.h:158	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f410rx.h:159	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f410rx.h:160	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f410rx.h:161	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f410rx.h:162	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f410rx.h:163	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f410rx.h:164	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f410rx.h:165	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f410rx.h:166	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f410rx.h:167	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f410rx.h:168	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f410rx.h:173	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f410rx.h:174	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f410rx.h:175	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f410rx.h:185	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f410rx.h:186	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f410rx.h:189	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f410rx.h:198	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f410rx.h:199	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f410rx.h:200	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f410rx.h:201	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f410rx.h:202	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f410rx.h:203	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f410rx.h:204	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f410rx.h:205	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f410rx.h:206	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f410rx.h:207	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f410rx.h:208	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f410rx.h:209	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f410rx.h:210	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f410rx.h:211	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f410rx.h:220	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f410rx.h:221	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f410rx.h:222	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f410rx.h:223	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f410rx.h:233	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f410rx.h:234	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f410rx.h:235	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f410rx.h:236	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f410rx.h:237	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f410rx.h:238	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f410rx.h:243	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f410rx.h:244	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f410rx.h:245	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f410rx.h:246	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f410rx.h:255	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f410rx.h:256	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f410rx.h:257	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f410rx.h:258	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f410rx.h:259	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f410rx.h:260	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f410rx.h:269	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f410rx.h:270	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f410rx.h:271	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f410rx.h:272	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f410rx.h:273	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f410rx.h:274	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f410rx.h:275	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f410rx.h:284	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f410rx.h:285	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f410rx.h:286	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f410rx.h:287	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f410rx.h:288	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f410rx.h:289	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f410rx.h:290	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f410rx.h:291	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f410rx.h:292	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f410rx.h:301	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f410rx.h:302	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f410rx.h:303	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f410rx.h:305	__IO uint32_t CFGR2; /!< SYSCFG Configuration register2, Address offset: 0x1C /
stm32f410rx.h:306	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f410rx.h:307	__IO uint32_t CFGR; /!< SYSCFG Configuration register, Address offset: 0x24 /
stm32f410rx.h:316	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f410rx.h:317	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f410rx.h:318	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f410rx.h:319	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f410rx.h:320	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f410rx.h:321	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f410rx.h:322	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f410rx.h:323	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f410rx.h:324	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f410rx.h:325	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f410rx.h:334	__IO uint32_t CR1; /!< FMPI2C Control register 1, Address offset: 0x00 /
stm32f410rx.h:335	__IO uint32_t CR2; /!< FMPI2C Control register 2, Address offset: 0x04 /
stm32f410rx.h:336	__IO uint32_t OAR1; /!< FMPI2C Own address 1 register, Address offset: 0x08 /
stm32f410rx.h:337	__IO uint32_t OAR2; /!< FMPI2C Own address 2 register, Address offset: 0x0C /
stm32f410rx.h:338	__IO uint32_t TIMINGR; /!< FMPI2C Timing register, Address offset: 0x10 /
stm32f410rx.h:339	__IO uint32_t TIMEOUTR; /!< FMPI2C Timeout register, Address offset: 0x14 /
stm32f410rx.h:340	__IO uint32_t ISR; /!< FMPI2C Interrupt and status register, Address offset: 0x18 /
stm32f410rx.h:341	__IO uint32_t ICR; /!< FMPI2C Interrupt clear register, Address offset: 0x1C /
stm32f410rx.h:342	__IO uint32_t PECR; /!< FMPI2C PEC register, Address offset: 0x20 /
stm32f410rx.h:343	__IO uint32_t RXDR; /!< FMPI2C Receive data register, Address offset: 0x24 /
stm32f410rx.h:344	__IO uint32_t TXDR; /!< FMPI2C Transmit data register, Address offset: 0x28 /
stm32f410rx.h:353	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f410rx.h:354	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f410rx.h:355	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f410rx.h:356	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f410rx.h:366	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f410rx.h:367	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f410rx.h:376	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f410rx.h:377	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f410rx.h:378	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f410rx.h:379	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f410rx.h:380	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f410rx.h:382	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f410rx.h:383	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f410rx.h:385	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f410rx.h:387	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f410rx.h:388	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f410rx.h:390	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f410rx.h:392	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f410rx.h:393	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f410rx.h:395	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f410rx.h:396	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f410rx.h:398	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f410rx.h:400	__IO uint32_t DCKCFGR; /!< RCC DCKCFGR configuration register, Address offset: 0x8C /
stm32f410rx.h:401	__IO uint32_t CKGATENR; /!< RCC Clocks Gated ENable Register, Address offset: 0x90 /
stm32f410rx.h:402	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 /
stm32f410rx.h:411	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f410rx.h:412	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f410rx.h:413	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f410rx.h:414	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f410rx.h:415	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f410rx.h:416	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f410rx.h:417	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f410rx.h:418	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f410rx.h:419	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f410rx.h:420	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f410rx.h:421	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f410rx.h:422	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f410rx.h:423	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f410rx.h:424	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f410rx.h:425	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f410rx.h:426	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f410rx.h:427	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f410rx.h:428	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f410rx.h:429	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f410rx.h:431	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f410rx.h:432	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f410rx.h:433	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f410rx.h:434	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f410rx.h:435	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f410rx.h:436	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f410rx.h:437	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f410rx.h:438	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f410rx.h:439	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f410rx.h:440	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f410rx.h:441	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f410rx.h:442	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f410rx.h:443	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f410rx.h:444	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f410rx.h:445	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f410rx.h:446	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f410rx.h:447	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f410rx.h:448	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f410rx.h:449	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f410rx.h:450	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f410rx.h:459	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f410rx.h:460	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f410rx.h:461	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f410rx.h:462	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f410rx.h:463	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f410rx.h:464	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f410rx.h:465	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f410rx.h:466	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f410rx.h:467	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f410rx.h:477	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f410rx.h:478	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f410rx.h:479	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f410rx.h:480	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f410rx.h:481	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f410rx.h:482	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f410rx.h:483	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f410rx.h:484	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f410rx.h:485	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f410rx.h:486	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f410rx.h:487	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f410rx.h:488	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f410rx.h:489	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f410rx.h:490	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f410rx.h:491	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f410rx.h:492	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f410rx.h:493	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f410rx.h:494	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f410rx.h:495	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f410rx.h:496	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f410rx.h:497	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f410rx.h:506	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f410rx.h:507	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f410rx.h:508	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f410rx.h:509	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f410rx.h:510	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f410rx.h:511	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f410rx.h:512	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f410rx.h:521	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f410rx.h:522	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f410rx.h:523	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f410rx.h:532	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f410rx.h:533	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f410rx.h:534	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f410rx.h:543	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
stm32f410rx.h:544	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
stm32f410rx.h:545	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
stm32f410rx.h:546	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
stm32f410rx.h:547	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
stm32f410rx.h:548	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
stm32f410rx.h:549	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
stm32f410rx.h:550	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
stm32f410rx.h:551	__IO uint32_t OR; /!< LPTIM Option register, Address offset: 0x20 /
stm32f410tx.h:146	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f410tx.h:147	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f410tx.h:148	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f410tx.h:149	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f410tx.h:150	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f410tx.h:151	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f410tx.h:152	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f410tx.h:153	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f410tx.h:154	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f410tx.h:155	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f410tx.h:156	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f410tx.h:157	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f410tx.h:158	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f410tx.h:159	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f410tx.h:160	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f410tx.h:161	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f410tx.h:162	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f410tx.h:163	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f410tx.h:164	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f410tx.h:165	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f410tx.h:170	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f410tx.h:171	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f410tx.h:172	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f410tx.h:182	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f410tx.h:183	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f410tx.h:186	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f410tx.h:195	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f410tx.h:196	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f410tx.h:197	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f410tx.h:198	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f410tx.h:199	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f410tx.h:200	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f410tx.h:201	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f410tx.h:202	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f410tx.h:203	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f410tx.h:204	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f410tx.h:205	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f410tx.h:206	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f410tx.h:207	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f410tx.h:208	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f410tx.h:217	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f410tx.h:218	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f410tx.h:219	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f410tx.h:220	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f410tx.h:230	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f410tx.h:231	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f410tx.h:232	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f410tx.h:233	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f410tx.h:234	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f410tx.h:235	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f410tx.h:240	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f410tx.h:241	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f410tx.h:242	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f410tx.h:243	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f410tx.h:252	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f410tx.h:253	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f410tx.h:254	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f410tx.h:255	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f410tx.h:256	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f410tx.h:257	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f410tx.h:266	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f410tx.h:267	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f410tx.h:268	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f410tx.h:269	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f410tx.h:270	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f410tx.h:271	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f410tx.h:272	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f410tx.h:281	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f410tx.h:282	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f410tx.h:283	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f410tx.h:284	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f410tx.h:285	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f410tx.h:286	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f410tx.h:287	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f410tx.h:288	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f410tx.h:289	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f410tx.h:298	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f410tx.h:299	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f410tx.h:300	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f410tx.h:302	__IO uint32_t CFGR2; /!< SYSCFG Configuration register2, Address offset: 0x1C /
stm32f410tx.h:303	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f410tx.h:304	__IO uint32_t CFGR; /!< SYSCFG Configuration register, Address offset: 0x24 /
stm32f410tx.h:313	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f410tx.h:314	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f410tx.h:315	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f410tx.h:316	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f410tx.h:317	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f410tx.h:318	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f410tx.h:319	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f410tx.h:320	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f410tx.h:321	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f410tx.h:322	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f410tx.h:331	__IO uint32_t CR1; /!< FMPI2C Control register 1, Address offset: 0x00 /
stm32f410tx.h:332	__IO uint32_t CR2; /!< FMPI2C Control register 2, Address offset: 0x04 /
stm32f410tx.h:333	__IO uint32_t OAR1; /!< FMPI2C Own address 1 register, Address offset: 0x08 /
stm32f410tx.h:334	__IO uint32_t OAR2; /!< FMPI2C Own address 2 register, Address offset: 0x0C /
stm32f410tx.h:335	__IO uint32_t TIMINGR; /!< FMPI2C Timing register, Address offset: 0x10 /
stm32f410tx.h:336	__IO uint32_t TIMEOUTR; /!< FMPI2C Timeout register, Address offset: 0x14 /
stm32f410tx.h:337	__IO uint32_t ISR; /!< FMPI2C Interrupt and status register, Address offset: 0x18 /
stm32f410tx.h:338	__IO uint32_t ICR; /!< FMPI2C Interrupt clear register, Address offset: 0x1C /
stm32f410tx.h:339	__IO uint32_t PECR; /!< FMPI2C PEC register, Address offset: 0x20 /
stm32f410tx.h:340	__IO uint32_t RXDR; /!< FMPI2C Receive data register, Address offset: 0x24 /
stm32f410tx.h:341	__IO uint32_t TXDR; /!< FMPI2C Transmit data register, Address offset: 0x28 /
stm32f410tx.h:350	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f410tx.h:351	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f410tx.h:352	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f410tx.h:353	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f410tx.h:363	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f410tx.h:364	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f410tx.h:373	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f410tx.h:374	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f410tx.h:375	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f410tx.h:376	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f410tx.h:377	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f410tx.h:379	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f410tx.h:380	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f410tx.h:382	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f410tx.h:384	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f410tx.h:385	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f410tx.h:387	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f410tx.h:389	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f410tx.h:390	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f410tx.h:392	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f410tx.h:393	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f410tx.h:395	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f410tx.h:397	__IO uint32_t DCKCFGR; /!< RCC DCKCFGR configuration register, Address offset: 0x8C /
stm32f410tx.h:398	__IO uint32_t CKGATENR; /!< RCC Clocks Gated ENable Register, Address offset: 0x90 /
stm32f410tx.h:399	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 /
stm32f410tx.h:408	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f410tx.h:409	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f410tx.h:410	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f410tx.h:411	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f410tx.h:412	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f410tx.h:413	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f410tx.h:414	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f410tx.h:415	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f410tx.h:416	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f410tx.h:417	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f410tx.h:418	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f410tx.h:419	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f410tx.h:420	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f410tx.h:421	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f410tx.h:422	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f410tx.h:423	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f410tx.h:424	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f410tx.h:425	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f410tx.h:426	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f410tx.h:428	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f410tx.h:429	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f410tx.h:430	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f410tx.h:431	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f410tx.h:432	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f410tx.h:433	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f410tx.h:434	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f410tx.h:435	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f410tx.h:436	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f410tx.h:437	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f410tx.h:438	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f410tx.h:439	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f410tx.h:440	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f410tx.h:441	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f410tx.h:442	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f410tx.h:443	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f410tx.h:444	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f410tx.h:445	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f410tx.h:446	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f410tx.h:447	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f410tx.h:456	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f410tx.h:457	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f410tx.h:458	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f410tx.h:459	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f410tx.h:460	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f410tx.h:461	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f410tx.h:462	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f410tx.h:463	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f410tx.h:464	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f410tx.h:474	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f410tx.h:475	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f410tx.h:476	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f410tx.h:477	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f410tx.h:478	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f410tx.h:479	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f410tx.h:480	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f410tx.h:481	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f410tx.h:482	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f410tx.h:483	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f410tx.h:484	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f410tx.h:485	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f410tx.h:486	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f410tx.h:487	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f410tx.h:488	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f410tx.h:489	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f410tx.h:490	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f410tx.h:491	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f410tx.h:492	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f410tx.h:493	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f410tx.h:494	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f410tx.h:503	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f410tx.h:504	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f410tx.h:505	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f410tx.h:506	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f410tx.h:507	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f410tx.h:508	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f410tx.h:509	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f410tx.h:518	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f410tx.h:519	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f410tx.h:520	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f410tx.h:529	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f410tx.h:530	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f410tx.h:531	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f410tx.h:540	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
stm32f410tx.h:541	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
stm32f410tx.h:542	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
stm32f410tx.h:543	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
stm32f410tx.h:544	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
stm32f410tx.h:545	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
stm32f410tx.h:546	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
stm32f410tx.h:547	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
stm32f410tx.h:548	__IO uint32_t OR; /!< LPTIM Option register, Address offset: 0x20 /
stm32f411xe.h:154	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f411xe.h:155	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f411xe.h:156	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f411xe.h:157	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f411xe.h:158	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f411xe.h:159	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f411xe.h:160	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f411xe.h:161	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f411xe.h:162	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f411xe.h:163	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f411xe.h:164	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f411xe.h:165	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f411xe.h:166	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f411xe.h:167	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f411xe.h:168	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f411xe.h:169	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f411xe.h:170	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f411xe.h:171	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f411xe.h:172	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f411xe.h:173	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f411xe.h:178	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f411xe.h:179	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f411xe.h:180	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f411xe.h:190	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f411xe.h:191	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f411xe.h:194	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f411xe.h:203	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f411xe.h:204	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f411xe.h:205	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f411xe.h:206	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f411xe.h:216	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f411xe.h:217	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f411xe.h:218	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f411xe.h:219	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f411xe.h:220	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f411xe.h:221	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f411xe.h:226	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f411xe.h:227	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f411xe.h:228	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f411xe.h:229	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f411xe.h:238	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f411xe.h:239	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f411xe.h:240	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f411xe.h:241	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f411xe.h:242	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f411xe.h:243	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f411xe.h:252	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f411xe.h:253	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f411xe.h:254	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f411xe.h:255	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f411xe.h:256	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f411xe.h:257	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f411xe.h:258	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f411xe.h:267	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f411xe.h:268	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f411xe.h:269	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f411xe.h:270	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f411xe.h:271	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f411xe.h:272	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f411xe.h:273	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f411xe.h:274	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f411xe.h:275	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f411xe.h:284	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f411xe.h:285	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f411xe.h:286	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f411xe.h:288	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f411xe.h:297	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f411xe.h:298	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f411xe.h:299	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f411xe.h:300	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f411xe.h:301	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f411xe.h:302	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f411xe.h:303	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f411xe.h:304	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f411xe.h:305	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f411xe.h:306	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f411xe.h:315	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f411xe.h:316	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f411xe.h:317	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f411xe.h:318	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f411xe.h:328	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f411xe.h:329	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f411xe.h:338	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f411xe.h:339	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f411xe.h:340	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f411xe.h:341	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f411xe.h:342	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f411xe.h:343	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f411xe.h:344	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f411xe.h:346	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f411xe.h:347	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f411xe.h:349	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f411xe.h:350	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f411xe.h:351	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f411xe.h:353	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f411xe.h:354	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f411xe.h:356	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f411xe.h:357	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f411xe.h:358	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f411xe.h:360	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f411xe.h:361	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f411xe.h:363	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f411xe.h:364	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f411xe.h:366	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f411xe.h:367	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f411xe.h:369	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f411xe.h:378	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f411xe.h:379	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f411xe.h:380	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f411xe.h:381	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f411xe.h:382	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f411xe.h:383	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f411xe.h:384	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f411xe.h:385	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f411xe.h:386	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f411xe.h:387	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f411xe.h:388	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f411xe.h:389	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f411xe.h:390	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f411xe.h:391	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f411xe.h:392	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f411xe.h:393	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f411xe.h:394	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f411xe.h:395	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f411xe.h:396	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f411xe.h:398	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f411xe.h:399	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f411xe.h:400	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f411xe.h:401	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f411xe.h:402	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f411xe.h:403	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f411xe.h:404	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f411xe.h:405	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f411xe.h:406	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f411xe.h:407	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f411xe.h:408	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f411xe.h:409	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f411xe.h:410	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f411xe.h:411	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f411xe.h:412	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f411xe.h:413	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f411xe.h:414	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f411xe.h:415	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f411xe.h:416	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f411xe.h:417	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f411xe.h:426	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f411xe.h:427	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f411xe.h:428	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f411xe.h:429	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f411xe.h:430	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f411xe.h:431	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f411xe.h:432	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f411xe.h:433	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f411xe.h:434	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f411xe.h:435	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f411xe.h:436	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f411xe.h:437	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f411xe.h:438	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f411xe.h:439	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f411xe.h:440	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f411xe.h:441	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f411xe.h:443	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f411xe.h:445	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f411xe.h:454	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f411xe.h:455	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f411xe.h:456	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f411xe.h:457	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f411xe.h:458	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f411xe.h:459	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f411xe.h:460	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f411xe.h:461	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f411xe.h:462	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f411xe.h:472	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f411xe.h:473	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f411xe.h:474	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f411xe.h:475	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f411xe.h:476	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f411xe.h:477	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f411xe.h:478	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f411xe.h:479	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f411xe.h:480	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f411xe.h:481	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f411xe.h:482	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f411xe.h:483	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f411xe.h:484	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f411xe.h:485	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f411xe.h:486	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f411xe.h:487	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f411xe.h:488	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f411xe.h:489	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f411xe.h:490	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f411xe.h:491	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f411xe.h:492	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f411xe.h:501	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f411xe.h:502	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f411xe.h:503	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f411xe.h:504	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f411xe.h:505	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f411xe.h:506	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f411xe.h:507	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f411xe.h:516	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f411xe.h:517	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f411xe.h:518	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f411xe.h:525	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f411xe.h:526	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f411xe.h:527	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f411xe.h:528	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f411xe.h:529	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f411xe.h:530	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f411xe.h:531	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f411xe.h:532	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f411xe.h:533	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f411xe.h:534	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f411xe.h:535	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f411xe.h:536	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f411xe.h:538	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f411xe.h:539	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f411xe.h:541	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f411xe.h:542	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f411xe.h:550	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f411xe.h:551	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f411xe.h:552	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f411xe.h:554	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f411xe.h:555	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f411xe.h:556	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f411xe.h:557	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f411xe.h:560	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f411xe.h:561	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f411xe.h:562	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f411xe.h:563	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f411xe.h:564	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f411xe.h:565	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f411xe.h:567	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f411xe.h:569	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f411xe.h:577	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f411xe.h:579	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f411xe.h:581	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f411xe.h:582	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f411xe.h:583	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f411xe.h:592	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f411xe.h:594	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f411xe.h:596	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f411xe.h:597	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f411xe.h:606	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f411xe.h:607	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f411xe.h:608	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f411xe.h:610	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f411xe.h:611	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f411xe.h:612	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f411xe.h:620	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f411xe.h:621	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f411xe.h:622	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f411xe.h:623	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f411xe.h:624	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f411xe.h:625	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f412zx.h:175	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f412zx.h:176	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f412zx.h:177	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f412zx.h:178	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f412zx.h:179	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f412zx.h:180	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f412zx.h:181	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f412zx.h:182	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f412zx.h:183	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f412zx.h:184	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f412zx.h:185	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f412zx.h:186	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f412zx.h:187	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f412zx.h:188	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f412zx.h:189	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f412zx.h:190	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f412zx.h:191	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f412zx.h:192	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f412zx.h:193	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f412zx.h:194	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f412zx.h:199	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f412zx.h:200	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f412zx.h:201	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f412zx.h:212	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f412zx.h:213	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f412zx.h:214	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f412zx.h:215	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f412zx.h:224	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f412zx.h:225	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f412zx.h:226	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f412zx.h:227	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f412zx.h:236	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f412zx.h:237	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f412zx.h:246	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f412zx.h:247	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f412zx.h:248	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f412zx.h:249	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f412zx.h:250	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f412zx.h:251	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f412zx.h:252	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f412zx.h:253	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f412zx.h:258	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f412zx.h:259	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f412zx.h:261	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f412zx.h:263	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f412zx.h:265	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f412zx.h:276	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f412zx.h:277	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f412zx.h:280	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f412zx.h:288	__IO uint32_t FLTCR1; /!< DFSDM control register1, Address offset: 0x100 /
stm32f412zx.h:289	__IO uint32_t FLTCR2; /!< DFSDM control register2, Address offset: 0x104 /
stm32f412zx.h:290	__IO uint32_t FLTISR; /!< DFSDM interrupt and status register, Address offset: 0x108 /
stm32f412zx.h:291	__IO uint32_t FLTICR; /!< DFSDM interrupt flag clear register, Address offset: 0x10C /
stm32f412zx.h:292	__IO uint32_t FLTJCHGR; /!< DFSDM injected channel group selection register, Address offset: 0x110 /
stm32f412zx.h:293	__IO uint32_t FLTFCR; /!< DFSDM filter control register, Address offset: 0x114 /
stm32f412zx.h:294	__IO uint32_t FLTJDATAR; /!< DFSDM data register for injected group, Address offset: 0x118 /
stm32f412zx.h:295	__IO uint32_t FLTRDATAR; /!< DFSDM data register for regular group, Address offset: 0x11C /
stm32f412zx.h:296	__IO uint32_t FLTAWHTR; /!< DFSDM analog watchdog high threshold register, Address offset: 0x120 /
stm32f412zx.h:297	__IO uint32_t FLTAWLTR; /!< DFSDM analog watchdog low threshold register, Address offset: 0x124 /
stm32f412zx.h:298	__IO uint32_t FLTAWSR; /!< DFSDM analog watchdog status register Address offset: 0x128 /
stm32f412zx.h:299	__IO uint32_t FLTAWCFR; /!< DFSDM analog watchdog clear flag register Address offset: 0x12C /
stm32f412zx.h:300	__IO uint32_t FLTEXMAX; /!< DFSDM extreme detector maximum register, Address offset: 0x130 /
stm32f412zx.h:301	__IO uint32_t FLTEXMIN; /!< DFSDM extreme detector minimum register Address offset: 0x134 /
stm32f412zx.h:302	__IO uint32_t FLTCNVTIMR; /!< DFSDM conversion timer, Address offset: 0x138 /
stm32f412zx.h:310	__IO uint32_t CHCFGR1; /!< DFSDM channel configuration register1, Address offset: 0x00 /
stm32f412zx.h:311	__IO uint32_t CHCFGR2; /!< DFSDM channel configuration register2, Address offset: 0x04 /
stm32f412zx.h:312	__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
stm32f412zx.h:314	__IO uint32_t CHWDATAR; /!< DFSDM channel watchdog filter data register, Address offset: 0x0C /
stm32f412zx.h:315	__IO uint32_t CHDATINR; /!< DFSDM channel data input register, Address offset: 0x10 /
stm32f412zx.h:324	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f412zx.h:325	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f412zx.h:326	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f412zx.h:327	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f412zx.h:337	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f412zx.h:338	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f412zx.h:339	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f412zx.h:340	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f412zx.h:341	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f412zx.h:342	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f412zx.h:347	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f412zx.h:348	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f412zx.h:349	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f412zx.h:350	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f412zx.h:359	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f412zx.h:360	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f412zx.h:361	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f412zx.h:362	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f412zx.h:363	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f412zx.h:364	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f412zx.h:373	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f412zx.h:374	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f412zx.h:375	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f412zx.h:376	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f412zx.h:377	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f412zx.h:378	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f412zx.h:379	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f412zx.h:390	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f412zx.h:399	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f412zx.h:407	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f412zx.h:408	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f412zx.h:409	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f412zx.h:410	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f412zx.h:411	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f412zx.h:412	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f412zx.h:413	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f412zx.h:414	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f412zx.h:415	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f412zx.h:424	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f412zx.h:425	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f412zx.h:426	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f412zx.h:428	__IO uint32_t CFGR2; /!< SYSCFG Configuration register2, Address offset: 0x1C /
stm32f412zx.h:429	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f412zx.h:430	__IO uint32_t CFGR; /!< SYSCFG Configuration register, Address offset: 0x24 /
stm32f412zx.h:439	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f412zx.h:440	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f412zx.h:441	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f412zx.h:442	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f412zx.h:443	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f412zx.h:444	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f412zx.h:445	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f412zx.h:446	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f412zx.h:447	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f412zx.h:448	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f412zx.h:457	__IO uint32_t CR1; /!< FMPI2C Control register 1, Address offset: 0x00 /
stm32f412zx.h:458	__IO uint32_t CR2; /!< FMPI2C Control register 2, Address offset: 0x04 /
stm32f412zx.h:459	__IO uint32_t OAR1; /!< FMPI2C Own address 1 register, Address offset: 0x08 /
stm32f412zx.h:460	__IO uint32_t OAR2; /!< FMPI2C Own address 2 register, Address offset: 0x0C /
stm32f412zx.h:461	__IO uint32_t TIMINGR; /!< FMPI2C Timing register, Address offset: 0x10 /
stm32f412zx.h:462	__IO uint32_t TIMEOUTR; /!< FMPI2C Timeout register, Address offset: 0x14 /
stm32f412zx.h:463	__IO uint32_t ISR; /!< FMPI2C Interrupt and status register, Address offset: 0x18 /
stm32f412zx.h:464	__IO uint32_t ICR; /!< FMPI2C Interrupt clear register, Address offset: 0x1C /
stm32f412zx.h:465	__IO uint32_t PECR; /!< FMPI2C PEC register, Address offset: 0x20 /
stm32f412zx.h:466	__IO uint32_t RXDR; /!< FMPI2C Receive data register, Address offset: 0x24 /
stm32f412zx.h:467	__IO uint32_t TXDR; /!< FMPI2C Transmit data register, Address offset: 0x28 /
stm32f412zx.h:476	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f412zx.h:477	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f412zx.h:478	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f412zx.h:479	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f412zx.h:489	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f412zx.h:490	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f412zx.h:499	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f412zx.h:500	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f412zx.h:501	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f412zx.h:502	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f412zx.h:503	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f412zx.h:504	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f412zx.h:505	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f412zx.h:507	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f412zx.h:508	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f412zx.h:510	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f412zx.h:511	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f412zx.h:512	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f412zx.h:514	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f412zx.h:515	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f412zx.h:517	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f412zx.h:518	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f412zx.h:519	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f412zx.h:521	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f412zx.h:522	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f412zx.h:524	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f412zx.h:525	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f412zx.h:527	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f412zx.h:528	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f412zx.h:530	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f412zx.h:531	__IO uint32_t CKGATENR; /!< RCC Clocks Gated ENable Register, Address offset: 0x90 /
stm32f412zx.h:532	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 /
stm32f412zx.h:541	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f412zx.h:542	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f412zx.h:543	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f412zx.h:544	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f412zx.h:545	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f412zx.h:546	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f412zx.h:547	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f412zx.h:548	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f412zx.h:549	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f412zx.h:550	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f412zx.h:551	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f412zx.h:552	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f412zx.h:553	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f412zx.h:554	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f412zx.h:555	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f412zx.h:556	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f412zx.h:557	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f412zx.h:558	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f412zx.h:559	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f412zx.h:561	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f412zx.h:562	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f412zx.h:563	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f412zx.h:564	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f412zx.h:565	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f412zx.h:566	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f412zx.h:567	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f412zx.h:568	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f412zx.h:569	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f412zx.h:570	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f412zx.h:571	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f412zx.h:572	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f412zx.h:573	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f412zx.h:574	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f412zx.h:575	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f412zx.h:576	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f412zx.h:577	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f412zx.h:578	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f412zx.h:579	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f412zx.h:580	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f412zx.h:589	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f412zx.h:590	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f412zx.h:591	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f412zx.h:592	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f412zx.h:593	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f412zx.h:594	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f412zx.h:595	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f412zx.h:596	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f412zx.h:597	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f412zx.h:598	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f412zx.h:599	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f412zx.h:600	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f412zx.h:601	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f412zx.h:602	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f412zx.h:603	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f412zx.h:604	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f412zx.h:606	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f412zx.h:608	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f412zx.h:617	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f412zx.h:618	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f412zx.h:619	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f412zx.h:620	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f412zx.h:621	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f412zx.h:622	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f412zx.h:623	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f412zx.h:624	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f412zx.h:625	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f412zx.h:634	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
stm32f412zx.h:635	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
stm32f412zx.h:636	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
stm32f412zx.h:637	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
stm32f412zx.h:638	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
stm32f412zx.h:639	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
stm32f412zx.h:640	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
stm32f412zx.h:641	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
stm32f412zx.h:642	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
stm32f412zx.h:643	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
stm32f412zx.h:644	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
stm32f412zx.h:645	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
stm32f412zx.h:646	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
stm32f412zx.h:655	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f412zx.h:656	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f412zx.h:657	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f412zx.h:658	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f412zx.h:659	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f412zx.h:660	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f412zx.h:661	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f412zx.h:662	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f412zx.h:663	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f412zx.h:664	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f412zx.h:665	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f412zx.h:666	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f412zx.h:667	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f412zx.h:668	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f412zx.h:669	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f412zx.h:670	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f412zx.h:671	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f412zx.h:672	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f412zx.h:673	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f412zx.h:674	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f412zx.h:675	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f412zx.h:684	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f412zx.h:685	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f412zx.h:686	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f412zx.h:687	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f412zx.h:688	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f412zx.h:689	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f412zx.h:690	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f412zx.h:699	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f412zx.h:700	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f412zx.h:701	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f412zx.h:710	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f412zx.h:711	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f412zx.h:712	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f412zx.h:720	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f412zx.h:721	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f412zx.h:722	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f412zx.h:723	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f412zx.h:724	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f412zx.h:725	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f412zx.h:726	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f412zx.h:727	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f412zx.h:728	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f412zx.h:729	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f412zx.h:730	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f412zx.h:731	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f412zx.h:733	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f412zx.h:734	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f412zx.h:736	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
stm32f412zx.h:738	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
stm32f412zx.h:740	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
stm32f412zx.h:742	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f412zx.h:743	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f412zx.h:751	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f412zx.h:752	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f412zx.h:753	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f412zx.h:755	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f412zx.h:756	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f412zx.h:757	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f412zx.h:758	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f412zx.h:761	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f412zx.h:762	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f412zx.h:763	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f412zx.h:764	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f412zx.h:765	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f412zx.h:766	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f412zx.h:768	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f412zx.h:770	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f412zx.h:778	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f412zx.h:780	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f412zx.h:782	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f412zx.h:783	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f412zx.h:784	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f412zx.h:793	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f412zx.h:795	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f412zx.h:797	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f412zx.h:798	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f412zx.h:807	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f412zx.h:808	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f412zx.h:809	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f412zx.h:811	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f412zx.h:812	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f412zx.h:813	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f412zx.h:821	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f412zx.h:822	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f412zx.h:823	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f412zx.h:824	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f412zx.h:825	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f412zx.h:826	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f413xx.h:191	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f413xx.h:192	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f413xx.h:193	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f413xx.h:194	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f413xx.h:195	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f413xx.h:196	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f413xx.h:197	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f413xx.h:198	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f413xx.h:199	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f413xx.h:200	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f413xx.h:201	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f413xx.h:202	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f413xx.h:203	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f413xx.h:204	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f413xx.h:205	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f413xx.h:206	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f413xx.h:207	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f413xx.h:208	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f413xx.h:209	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f413xx.h:210	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f413xx.h:215	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f413xx.h:216	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f413xx.h:217	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f413xx.h:228	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f413xx.h:229	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f413xx.h:230	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f413xx.h:231	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f413xx.h:240	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f413xx.h:241	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f413xx.h:242	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f413xx.h:243	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f413xx.h:252	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f413xx.h:253	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f413xx.h:262	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f413xx.h:263	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f413xx.h:264	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f413xx.h:265	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f413xx.h:266	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f413xx.h:267	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f413xx.h:268	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f413xx.h:269	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f413xx.h:274	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f413xx.h:275	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f413xx.h:277	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f413xx.h:279	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f413xx.h:281	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f413xx.h:292	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f413xx.h:293	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f413xx.h:296	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f413xx.h:304	__IO uint32_t FLTCR1; /!< DFSDM control register1, Address offset: 0x100 /
stm32f413xx.h:305	__IO uint32_t FLTCR2; /!< DFSDM control register2, Address offset: 0x104 /
stm32f413xx.h:306	__IO uint32_t FLTISR; /!< DFSDM interrupt and status register, Address offset: 0x108 /
stm32f413xx.h:307	__IO uint32_t FLTICR; /!< DFSDM interrupt flag clear register, Address offset: 0x10C /
stm32f413xx.h:308	__IO uint32_t FLTJCHGR; /!< DFSDM injected channel group selection register, Address offset: 0x110 /
stm32f413xx.h:309	__IO uint32_t FLTFCR; /!< DFSDM filter control register, Address offset: 0x114 /
stm32f413xx.h:310	__IO uint32_t FLTJDATAR; /!< DFSDM data register for injected group, Address offset: 0x118 /
stm32f413xx.h:311	__IO uint32_t FLTRDATAR; /!< DFSDM data register for regular group, Address offset: 0x11C /
stm32f413xx.h:312	__IO uint32_t FLTAWHTR; /!< DFSDM analog watchdog high threshold register, Address offset: 0x120 /
stm32f413xx.h:313	__IO uint32_t FLTAWLTR; /!< DFSDM analog watchdog low threshold register, Address offset: 0x124 /
stm32f413xx.h:314	__IO uint32_t FLTAWSR; /!< DFSDM analog watchdog status register Address offset: 0x128 /
stm32f413xx.h:315	__IO uint32_t FLTAWCFR; /!< DFSDM analog watchdog clear flag register Address offset: 0x12C /
stm32f413xx.h:316	__IO uint32_t FLTEXMAX; /!< DFSDM extreme detector maximum register, Address offset: 0x130 /
stm32f413xx.h:317	__IO uint32_t FLTEXMIN; /!< DFSDM extreme detector minimum register Address offset: 0x134 /
stm32f413xx.h:318	__IO uint32_t FLTCNVTIMR; /!< DFSDM conversion timer, Address offset: 0x138 /
stm32f413xx.h:326	__IO uint32_t CHCFGR1; /!< DFSDM channel configuration register1, Address offset: 0x00 /
stm32f413xx.h:327	__IO uint32_t CHCFGR2; /!< DFSDM channel configuration register2, Address offset: 0x04 /
stm32f413xx.h:328	__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
stm32f413xx.h:330	__IO uint32_t CHWDATAR; /!< DFSDM channel watchdog filter data register, Address offset: 0x0C /
stm32f413xx.h:331	__IO uint32_t CHDATINR; /!< DFSDM channel data input register, Address offset: 0x10 /
stm32f413xx.h:340	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f413xx.h:341	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f413xx.h:342	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f413xx.h:343	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f413xx.h:344	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f413xx.h:345	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f413xx.h:346	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f413xx.h:347	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f413xx.h:348	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f413xx.h:349	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f413xx.h:350	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f413xx.h:351	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f413xx.h:352	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f413xx.h:353	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f413xx.h:362	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f413xx.h:363	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f413xx.h:364	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f413xx.h:365	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f413xx.h:375	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f413xx.h:376	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f413xx.h:377	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f413xx.h:378	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f413xx.h:379	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f413xx.h:380	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f413xx.h:385	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f413xx.h:386	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f413xx.h:387	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f413xx.h:388	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f413xx.h:397	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f413xx.h:398	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f413xx.h:399	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f413xx.h:400	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f413xx.h:401	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f413xx.h:402	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f413xx.h:411	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f413xx.h:412	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f413xx.h:413	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f413xx.h:414	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f413xx.h:415	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f413xx.h:416	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f413xx.h:417	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f413xx.h:428	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f413xx.h:437	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f413xx.h:445	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f413xx.h:446	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f413xx.h:447	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f413xx.h:448	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f413xx.h:449	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f413xx.h:450	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f413xx.h:451	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f413xx.h:452	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f413xx.h:453	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f413xx.h:462	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f413xx.h:463	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f413xx.h:464	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f413xx.h:466	__IO uint32_t CFGR2; /!< SYSCFG Configuration register2, Address offset: 0x1C /
stm32f413xx.h:467	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f413xx.h:469	__IO uint32_t CFGR; /!< SYSCFG Configuration register, Address offset: 0x2C /
stm32f413xx.h:470	__IO uint32_t MCHDLYCR; /!< SYSCFG multi-channel delay register, Address offset: 0x30 /
stm32f413xx.h:479	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f413xx.h:480	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f413xx.h:481	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f413xx.h:482	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f413xx.h:483	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f413xx.h:484	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f413xx.h:485	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f413xx.h:486	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f413xx.h:487	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f413xx.h:488	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f413xx.h:497	__IO uint32_t CR1; /!< FMPI2C Control register 1, Address offset: 0x00 /
stm32f413xx.h:498	__IO uint32_t CR2; /!< FMPI2C Control register 2, Address offset: 0x04 /
stm32f413xx.h:499	__IO uint32_t OAR1; /!< FMPI2C Own address 1 register, Address offset: 0x08 /
stm32f413xx.h:500	__IO uint32_t OAR2; /!< FMPI2C Own address 2 register, Address offset: 0x0C /
stm32f413xx.h:501	__IO uint32_t TIMINGR; /!< FMPI2C Timing register, Address offset: 0x10 /
stm32f413xx.h:502	__IO uint32_t TIMEOUTR; /!< FMPI2C Timeout register, Address offset: 0x14 /
stm32f413xx.h:503	__IO uint32_t ISR; /!< FMPI2C Interrupt and status register, Address offset: 0x18 /
stm32f413xx.h:504	__IO uint32_t ICR; /!< FMPI2C Interrupt clear register, Address offset: 0x1C /
stm32f413xx.h:505	__IO uint32_t PECR; /!< FMPI2C PEC register, Address offset: 0x20 /
stm32f413xx.h:506	__IO uint32_t RXDR; /!< FMPI2C Receive data register, Address offset: 0x24 /
stm32f413xx.h:507	__IO uint32_t TXDR; /!< FMPI2C Transmit data register, Address offset: 0x28 /
stm32f413xx.h:516	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f413xx.h:517	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f413xx.h:518	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f413xx.h:519	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f413xx.h:529	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f413xx.h:530	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f413xx.h:539	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f413xx.h:540	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f413xx.h:541	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f413xx.h:542	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f413xx.h:543	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f413xx.h:544	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f413xx.h:545	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f413xx.h:547	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f413xx.h:548	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f413xx.h:550	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f413xx.h:551	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f413xx.h:552	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f413xx.h:554	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f413xx.h:555	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f413xx.h:557	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f413xx.h:558	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f413xx.h:559	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f413xx.h:561	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f413xx.h:562	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f413xx.h:564	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f413xx.h:565	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f413xx.h:567	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f413xx.h:568	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f413xx.h:570	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f413xx.h:571	__IO uint32_t CKGATENR; /!< RCC Clocks Gated ENable Register, Address offset: 0x90 /
stm32f413xx.h:572	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 /
stm32f413xx.h:581	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f413xx.h:582	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f413xx.h:583	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f413xx.h:584	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f413xx.h:585	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f413xx.h:586	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f413xx.h:587	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f413xx.h:588	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f413xx.h:589	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f413xx.h:590	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f413xx.h:591	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f413xx.h:592	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f413xx.h:593	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f413xx.h:594	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f413xx.h:595	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f413xx.h:596	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f413xx.h:597	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f413xx.h:598	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f413xx.h:599	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f413xx.h:601	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f413xx.h:602	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f413xx.h:603	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f413xx.h:604	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f413xx.h:605	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f413xx.h:606	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f413xx.h:607	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f413xx.h:608	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f413xx.h:609	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f413xx.h:610	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f413xx.h:611	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f413xx.h:612	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f413xx.h:613	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f413xx.h:614	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f413xx.h:615	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f413xx.h:616	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f413xx.h:617	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f413xx.h:618	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f413xx.h:619	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f413xx.h:620	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f413xx.h:629	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
stm32f413xx.h:634	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
stm32f413xx.h:635	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
stm32f413xx.h:636	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
stm32f413xx.h:637	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
stm32f413xx.h:638	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
stm32f413xx.h:639	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
stm32f413xx.h:640	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
stm32f413xx.h:641	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
stm32f413xx.h:650	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f413xx.h:651	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f413xx.h:652	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f413xx.h:653	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f413xx.h:654	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f413xx.h:655	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f413xx.h:656	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f413xx.h:657	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f413xx.h:658	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f413xx.h:659	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f413xx.h:660	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f413xx.h:661	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f413xx.h:662	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f413xx.h:663	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f413xx.h:664	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f413xx.h:665	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f413xx.h:667	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f413xx.h:669	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f413xx.h:678	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f413xx.h:679	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f413xx.h:680	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f413xx.h:681	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f413xx.h:682	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f413xx.h:683	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f413xx.h:684	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f413xx.h:685	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f413xx.h:686	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f413xx.h:695	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
stm32f413xx.h:696	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
stm32f413xx.h:697	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
stm32f413xx.h:698	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
stm32f413xx.h:699	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
stm32f413xx.h:700	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
stm32f413xx.h:701	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
stm32f413xx.h:702	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
stm32f413xx.h:703	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
stm32f413xx.h:704	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
stm32f413xx.h:705	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
stm32f413xx.h:706	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
stm32f413xx.h:707	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
stm32f413xx.h:716	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f413xx.h:717	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f413xx.h:718	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f413xx.h:719	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f413xx.h:720	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f413xx.h:721	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f413xx.h:722	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f413xx.h:723	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f413xx.h:724	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f413xx.h:725	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f413xx.h:726	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f413xx.h:727	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f413xx.h:728	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f413xx.h:729	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f413xx.h:730	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f413xx.h:731	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f413xx.h:732	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f413xx.h:733	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f413xx.h:734	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f413xx.h:735	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f413xx.h:736	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f413xx.h:745	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f413xx.h:746	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f413xx.h:747	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f413xx.h:748	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f413xx.h:749	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f413xx.h:750	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f413xx.h:751	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f413xx.h:760	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f413xx.h:761	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f413xx.h:762	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f413xx.h:771	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f413xx.h:772	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f413xx.h:773	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f413xx.h:781	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f413xx.h:782	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f413xx.h:783	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f413xx.h:784	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f413xx.h:785	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f413xx.h:786	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f413xx.h:787	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f413xx.h:788	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f413xx.h:789	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f413xx.h:790	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f413xx.h:791	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f413xx.h:792	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f413xx.h:794	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f413xx.h:795	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f413xx.h:797	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
stm32f413xx.h:799	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
stm32f413xx.h:801	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
stm32f413xx.h:803	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f413xx.h:804	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f413xx.h:812	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f413xx.h:813	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f413xx.h:814	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f413xx.h:816	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f413xx.h:817	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f413xx.h:818	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f413xx.h:819	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f413xx.h:822	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f413xx.h:823	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f413xx.h:824	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f413xx.h:825	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f413xx.h:826	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f413xx.h:827	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f413xx.h:829	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f413xx.h:831	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f413xx.h:839	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f413xx.h:841	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f413xx.h:843	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f413xx.h:844	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f413xx.h:845	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f413xx.h:854	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f413xx.h:856	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f413xx.h:858	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f413xx.h:859	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f413xx.h:868	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f413xx.h:869	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f413xx.h:870	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f413xx.h:872	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f413xx.h:873	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f413xx.h:874	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f413xx.h:882	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f413xx.h:883	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f413xx.h:884	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f413xx.h:885	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f413xx.h:886	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f413xx.h:887	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f413xx.h:896	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
stm32f413xx.h:897	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
stm32f413xx.h:898	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
stm32f413xx.h:899	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
stm32f413xx.h:900	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
stm32f413xx.h:901	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
stm32f413xx.h:902	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
stm32f413xx.h:903	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
stm32f413xx.h:904	__IO uint32_t OR; /!< LPTIM Option register, Address offset: 0x20 /
stm32f417xx.h:179	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f417xx.h:180	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f417xx.h:181	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f417xx.h:182	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f417xx.h:183	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f417xx.h:184	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f417xx.h:185	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f417xx.h:186	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f417xx.h:187	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f417xx.h:188	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f417xx.h:189	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f417xx.h:190	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f417xx.h:191	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f417xx.h:192	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f417xx.h:193	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f417xx.h:194	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f417xx.h:195	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f417xx.h:196	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f417xx.h:197	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f417xx.h:198	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f417xx.h:203	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f417xx.h:204	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f417xx.h:205	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f417xx.h:216	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f417xx.h:217	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f417xx.h:218	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f417xx.h:219	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f417xx.h:228	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f417xx.h:229	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f417xx.h:230	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f417xx.h:231	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f417xx.h:240	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f417xx.h:241	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f417xx.h:250	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f417xx.h:251	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f417xx.h:252	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f417xx.h:253	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f417xx.h:254	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f417xx.h:255	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f417xx.h:256	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f417xx.h:257	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f417xx.h:262	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f417xx.h:263	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f417xx.h:265	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f417xx.h:267	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f417xx.h:269	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f417xx.h:280	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f417xx.h:281	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f417xx.h:284	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f417xx.h:293	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f417xx.h:294	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f417xx.h:295	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f417xx.h:296	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f417xx.h:297	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f417xx.h:298	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f417xx.h:299	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f417xx.h:300	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f417xx.h:301	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f417xx.h:302	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f417xx.h:303	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f417xx.h:304	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f417xx.h:305	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f417xx.h:306	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f417xx.h:315	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f417xx.h:316	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f417xx.h:317	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f417xx.h:318	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f417xx.h:327	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f417xx.h:328	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f417xx.h:329	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f417xx.h:330	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f417xx.h:331	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f417xx.h:332	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f417xx.h:333	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f417xx.h:334	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f417xx.h:335	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f417xx.h:336	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f417xx.h:337	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f417xx.h:346	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f417xx.h:347	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f417xx.h:348	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f417xx.h:349	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f417xx.h:350	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f417xx.h:351	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f417xx.h:356	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f417xx.h:357	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f417xx.h:358	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f417xx.h:359	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f417xx.h:368	__IO uint32_t MACCR;
stm32f417xx.h:369	__IO uint32_t MACFFR;
stm32f417xx.h:370	__IO uint32_t MACHTHR;
stm32f417xx.h:371	__IO uint32_t MACHTLR;
stm32f417xx.h:372	__IO uint32_t MACMIIAR;
stm32f417xx.h:373	__IO uint32_t MACMIIDR;
stm32f417xx.h:374	__IO uint32_t MACFCR;
stm32f417xx.h:375	__IO uint32_t MACVLANTR; /* 8 */
stm32f417xx.h:377	__IO uint32_t MACRWUFFR; /* 11 */
stm32f417xx.h:378	__IO uint32_t MACPMTCSR;
stm32f417xx.h:380	__IO uint32_t MACDBGR;
stm32f417xx.h:381	__IO uint32_t MACSR; /* 15 */
stm32f417xx.h:382	__IO uint32_t MACIMR;
stm32f417xx.h:383	__IO uint32_t MACA0HR;
stm32f417xx.h:384	__IO uint32_t MACA0LR;
stm32f417xx.h:385	__IO uint32_t MACA1HR;
stm32f417xx.h:386	__IO uint32_t MACA1LR;
stm32f417xx.h:387	__IO uint32_t MACA2HR;
stm32f417xx.h:388	__IO uint32_t MACA2LR;
stm32f417xx.h:389	__IO uint32_t MACA3HR;
stm32f417xx.h:390	__IO uint32_t MACA3LR; /* 24 */
stm32f417xx.h:392	__IO uint32_t MMCCR; /* 65 */
stm32f417xx.h:393	__IO uint32_t MMCRIR;
stm32f417xx.h:394	__IO uint32_t MMCTIR;
stm32f417xx.h:395	__IO uint32_t MMCRIMR;
stm32f417xx.h:396	__IO uint32_t MMCTIMR; /* 69 */
stm32f417xx.h:398	__IO uint32_t MMCTGFSCCR; /* 84 */
stm32f417xx.h:399	__IO uint32_t MMCTGFMSCCR;
stm32f417xx.h:401	__IO uint32_t MMCTGFCR;
stm32f417xx.h:403	__IO uint32_t MMCRFCECR;
stm32f417xx.h:404	__IO uint32_t MMCRFAECR;
stm32f417xx.h:406	__IO uint32_t MMCRGUFCR;
stm32f417xx.h:408	__IO uint32_t PTPTSCR;
stm32f417xx.h:409	__IO uint32_t PTPSSIR;
stm32f417xx.h:410	__IO uint32_t PTPTSHR;
stm32f417xx.h:411	__IO uint32_t PTPTSLR;
stm32f417xx.h:412	__IO uint32_t PTPTSHUR;
stm32f417xx.h:413	__IO uint32_t PTPTSLUR;
stm32f417xx.h:414	__IO uint32_t PTPTSAR;
stm32f417xx.h:415	__IO uint32_t PTPTTHR;
stm32f417xx.h:416	__IO uint32_t PTPTTLR;
stm32f417xx.h:417	__IO uint32_t RESERVED8;
stm32f417xx.h:418	__IO uint32_t PTPTSSR;
stm32f417xx.h:420	__IO uint32_t DMABMR;
stm32f417xx.h:421	__IO uint32_t DMATPDR;
stm32f417xx.h:422	__IO uint32_t DMARPDR;
stm32f417xx.h:423	__IO uint32_t DMARDLAR;
stm32f417xx.h:424	__IO uint32_t DMATDLAR;
stm32f417xx.h:425	__IO uint32_t DMASR;
stm32f417xx.h:426	__IO uint32_t DMAOMR;
stm32f417xx.h:427	__IO uint32_t DMAIER;
stm32f417xx.h:428	__IO uint32_t DMAMFBOCR;
stm32f417xx.h:429	__IO uint32_t DMARSWTR;
stm32f417xx.h:431	__IO uint32_t DMACHTDR;
stm32f417xx.h:432	__IO uint32_t DMACHRDR;
stm32f417xx.h:433	__IO uint32_t DMACHTBAR;
stm32f417xx.h:434	__IO uint32_t DMACHRBAR;
stm32f417xx.h:443	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f417xx.h:444	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f417xx.h:445	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f417xx.h:446	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f417xx.h:447	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f417xx.h:448	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f417xx.h:457	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f417xx.h:458	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f417xx.h:459	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f417xx.h:460	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f417xx.h:461	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f417xx.h:462	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f417xx.h:463	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f417xx.h:474	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f417xx.h:483	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f417xx.h:492	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
stm32f417xx.h:493	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
stm32f417xx.h:494	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
stm32f417xx.h:495	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
stm32f417xx.h:497	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
stm32f417xx.h:500	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
stm32f417xx.h:501	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
stm32f417xx.h:502	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
stm32f417xx.h:503	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
stm32f417xx.h:505	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
stm32f417xx.h:514	__IO uint32_t PCR4; /!< PC Card control register 4, Address offset: 0xA0 /
stm32f417xx.h:515	__IO uint32_t SR4; /!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 /
stm32f417xx.h:516	__IO uint32_t PMEM4; /!< PC Card Common memory space timing register 4, Address offset: 0xA8 /
stm32f417xx.h:517	__IO uint32_t PATT4; /!< PC Card Attribute memory space timing register 4, Address offset: 0xAC /
stm32f417xx.h:518	__IO uint32_t PIO4; /!< PC Card I/O space timing register 4, Address offset: 0xB0 /
stm32f417xx.h:527	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f417xx.h:528	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f417xx.h:529	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f417xx.h:530	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f417xx.h:531	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f417xx.h:532	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f417xx.h:533	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f417xx.h:534	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f417xx.h:535	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f417xx.h:544	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f417xx.h:545	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f417xx.h:546	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f417xx.h:548	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f417xx.h:557	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f417xx.h:558	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f417xx.h:559	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f417xx.h:560	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f417xx.h:561	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f417xx.h:562	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f417xx.h:563	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f417xx.h:564	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f417xx.h:565	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f417xx.h:574	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f417xx.h:575	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f417xx.h:576	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f417xx.h:577	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f417xx.h:587	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f417xx.h:588	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f417xx.h:597	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f417xx.h:598	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f417xx.h:599	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f417xx.h:600	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f417xx.h:601	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f417xx.h:602	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f417xx.h:603	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f417xx.h:605	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f417xx.h:606	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f417xx.h:608	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f417xx.h:609	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f417xx.h:610	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f417xx.h:612	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f417xx.h:613	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f417xx.h:615	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f417xx.h:616	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f417xx.h:617	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f417xx.h:619	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f417xx.h:620	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f417xx.h:622	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f417xx.h:623	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f417xx.h:625	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f417xx.h:626	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f417xx.h:635	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f417xx.h:636	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f417xx.h:637	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f417xx.h:638	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f417xx.h:639	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f417xx.h:640	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f417xx.h:641	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f417xx.h:642	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f417xx.h:643	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f417xx.h:644	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f417xx.h:645	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f417xx.h:646	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f417xx.h:647	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f417xx.h:648	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f417xx.h:649	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f417xx.h:650	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f417xx.h:651	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f417xx.h:652	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f417xx.h:653	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f417xx.h:655	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f417xx.h:656	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f417xx.h:657	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f417xx.h:658	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f417xx.h:659	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f417xx.h:660	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f417xx.h:661	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f417xx.h:662	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f417xx.h:663	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f417xx.h:664	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f417xx.h:665	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f417xx.h:666	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f417xx.h:667	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f417xx.h:668	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f417xx.h:669	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f417xx.h:670	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f417xx.h:671	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f417xx.h:672	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f417xx.h:673	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f417xx.h:674	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f417xx.h:683	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f417xx.h:684	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f417xx.h:685	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f417xx.h:686	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f417xx.h:687	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f417xx.h:688	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f417xx.h:689	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f417xx.h:690	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f417xx.h:691	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f417xx.h:692	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f417xx.h:693	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f417xx.h:694	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f417xx.h:695	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f417xx.h:696	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f417xx.h:697	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f417xx.h:698	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f417xx.h:700	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f417xx.h:702	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f417xx.h:711	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f417xx.h:712	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f417xx.h:713	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f417xx.h:714	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f417xx.h:715	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f417xx.h:716	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f417xx.h:717	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f417xx.h:718	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f417xx.h:719	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f417xx.h:729	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f417xx.h:730	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f417xx.h:731	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f417xx.h:732	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f417xx.h:733	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f417xx.h:734	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f417xx.h:735	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f417xx.h:736	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f417xx.h:737	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f417xx.h:738	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f417xx.h:739	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f417xx.h:740	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f417xx.h:741	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f417xx.h:742	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f417xx.h:743	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f417xx.h:744	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f417xx.h:745	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f417xx.h:746	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f417xx.h:747	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f417xx.h:748	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f417xx.h:749	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f417xx.h:758	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f417xx.h:759	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f417xx.h:760	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f417xx.h:761	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f417xx.h:762	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f417xx.h:763	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f417xx.h:764	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f417xx.h:773	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f417xx.h:774	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f417xx.h:775	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f417xx.h:784	__IO uint32_t CR; /!< CRYP control register, Address offset: 0x00 /
stm32f417xx.h:785	__IO uint32_t SR; /!< CRYP status register, Address offset: 0x04 /
stm32f417xx.h:786	__IO uint32_t DIN; /!< CRYP data input register, Address offset: 0x08 /
stm32f417xx.h:787	__IO uint32_t DOUT; /!< CRYP data output register, Address offset: 0x0C /
stm32f417xx.h:788	__IO uint32_t DMACR; /!< CRYP DMA control register, Address offset: 0x10 /
stm32f417xx.h:789	__IO uint32_t IMSCR; /!< CRYP interrupt mask set/clear register, Address offset: 0x14 /
stm32f417xx.h:790	__IO uint32_t RISR; /!< CRYP raw interrupt status register, Address offset: 0x18 /
stm32f417xx.h:791	__IO uint32_t MISR; /!< CRYP masked interrupt status register, Address offset: 0x1C /
stm32f417xx.h:792	__IO uint32_t K0LR; /!< CRYP key left register 0, Address offset: 0x20 /
stm32f417xx.h:793	__IO uint32_t K0RR; /!< CRYP key right register 0, Address offset: 0x24 /
stm32f417xx.h:794	__IO uint32_t K1LR; /!< CRYP key left register 1, Address offset: 0x28 /
stm32f417xx.h:795	__IO uint32_t K1RR; /!< CRYP key right register 1, Address offset: 0x2C /
stm32f417xx.h:796	__IO uint32_t K2LR; /!< CRYP key left register 2, Address offset: 0x30 /
stm32f417xx.h:797	__IO uint32_t K2RR; /!< CRYP key right register 2, Address offset: 0x34 /
stm32f417xx.h:798	__IO uint32_t K3LR; /!< CRYP key left register 3, Address offset: 0x38 /
stm32f417xx.h:799	__IO uint32_t K3RR; /!< CRYP key right register 3, Address offset: 0x3C /
stm32f417xx.h:800	__IO uint32_t IV0LR; /!< CRYP initialization vector left-word register 0, Address offset: 0x40 /
stm32f417xx.h:801	__IO uint32_t IV0RR; /!< CRYP initialization vector right-word register 0, Address offset: 0x44 /
stm32f417xx.h:802	__IO uint32_t IV1LR; /!< CRYP initialization vector left-word register 1, Address offset: 0x48 /
stm32f417xx.h:803	__IO uint32_t IV1RR; /!< CRYP initialization vector right-word register 1, Address offset: 0x4C /
stm32f417xx.h:804	__IO uint32_t CSGCMCCM0R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 /
stm32f417xx.h:805	__IO uint32_t CSGCMCCM1R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 /
stm32f417xx.h:806	__IO uint32_t CSGCMCCM2R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 /
stm32f417xx.h:807	__IO uint32_t CSGCMCCM3R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C /
stm32f417xx.h:808	__IO uint32_t CSGCMCCM4R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 /
stm32f417xx.h:809	__IO uint32_t CSGCMCCM5R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 /
stm32f417xx.h:810	__IO uint32_t CSGCMCCM6R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 /
stm32f417xx.h:811	__IO uint32_t CSGCMCCM7R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C /
stm32f417xx.h:812	__IO uint32_t CSGCM0R; /!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 /
stm32f417xx.h:813	__IO uint32_t CSGCM1R; /!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 /
stm32f417xx.h:814	__IO uint32_t CSGCM2R; /!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 /
stm32f417xx.h:815	__IO uint32_t CSGCM3R; /!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C /
stm32f417xx.h:816	__IO uint32_t CSGCM4R; /!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 /
stm32f417xx.h:817	__IO uint32_t CSGCM5R; /!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 /
stm32f417xx.h:818	__IO uint32_t CSGCM6R; /!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 /
stm32f417xx.h:819	__IO uint32_t CSGCM7R; /!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C /
stm32f417xx.h:828	__IO uint32_t CR; /!< HASH control register, Address offset: 0x00 /
stm32f417xx.h:829	__IO uint32_t DIN; /!< HASH data input register, Address offset: 0x04 /
stm32f417xx.h:830	__IO uint32_t STR; /!< HASH start register, Address offset: 0x08 /
stm32f417xx.h:831	__IO uint32_t HR[5]; /!< HASH digest registers, Address offset: 0x0C-0x1C /
stm32f417xx.h:832	__IO uint32_t IMR; /!< HASH interrupt enable register, Address offset: 0x20 /
stm32f417xx.h:833	__IO uint32_t SR; /!< HASH status register, Address offset: 0x24 /
stm32f417xx.h:835	__IO uint32_t CSR[54]; /!< HASH context swap registers, Address offset: 0x0F8-0x1CC /
stm32f417xx.h:844	__IO uint32_t HR[5]; /!< HASH digest registers, Address offset: 0x310-0x32C /
stm32f417xx.h:853	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f417xx.h:854	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f417xx.h:855	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f417xx.h:863	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f417xx.h:864	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f417xx.h:865	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f417xx.h:866	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f417xx.h:867	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f417xx.h:868	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f417xx.h:869	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f417xx.h:870	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f417xx.h:871	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f417xx.h:872	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f417xx.h:873	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f417xx.h:874	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f417xx.h:876	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f417xx.h:877	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f417xx.h:879	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f417xx.h:880	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f417xx.h:888	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f417xx.h:889	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f417xx.h:890	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f417xx.h:892	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f417xx.h:893	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f417xx.h:894	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f417xx.h:895	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f417xx.h:898	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f417xx.h:899	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f417xx.h:900	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f417xx.h:901	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f417xx.h:902	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f417xx.h:903	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f417xx.h:905	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f417xx.h:907	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f417xx.h:915	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f417xx.h:917	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f417xx.h:919	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f417xx.h:920	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f417xx.h:921	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f417xx.h:930	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f417xx.h:932	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f417xx.h:934	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f417xx.h:935	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f417xx.h:944	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f417xx.h:945	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f417xx.h:946	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f417xx.h:948	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f417xx.h:949	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f417xx.h:950	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f417xx.h:958	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f417xx.h:959	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f417xx.h:960	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f417xx.h:961	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f417xx.h:962	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f417xx.h:963	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f429xx.h:187	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f429xx.h:188	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f429xx.h:189	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f429xx.h:190	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f429xx.h:191	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f429xx.h:192	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f429xx.h:193	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f429xx.h:194	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f429xx.h:195	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f429xx.h:196	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f429xx.h:197	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f429xx.h:198	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f429xx.h:199	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f429xx.h:200	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f429xx.h:201	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f429xx.h:202	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f429xx.h:203	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f429xx.h:204	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f429xx.h:205	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f429xx.h:206	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f429xx.h:211	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f429xx.h:212	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f429xx.h:213	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f429xx.h:224	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f429xx.h:225	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f429xx.h:226	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f429xx.h:227	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f429xx.h:236	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f429xx.h:237	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f429xx.h:238	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f429xx.h:239	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f429xx.h:248	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f429xx.h:249	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f429xx.h:258	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f429xx.h:259	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f429xx.h:260	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f429xx.h:261	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f429xx.h:262	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f429xx.h:263	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f429xx.h:264	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f429xx.h:265	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f429xx.h:270	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f429xx.h:271	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f429xx.h:273	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f429xx.h:275	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f429xx.h:277	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f429xx.h:288	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f429xx.h:289	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f429xx.h:292	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f429xx.h:301	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f429xx.h:302	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f429xx.h:303	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f429xx.h:304	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f429xx.h:305	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f429xx.h:306	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f429xx.h:307	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f429xx.h:308	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f429xx.h:309	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f429xx.h:310	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f429xx.h:311	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f429xx.h:312	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f429xx.h:313	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f429xx.h:314	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f429xx.h:323	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f429xx.h:324	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f429xx.h:325	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f429xx.h:326	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f429xx.h:335	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f429xx.h:336	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f429xx.h:337	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f429xx.h:338	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f429xx.h:339	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f429xx.h:340	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f429xx.h:341	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f429xx.h:342	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f429xx.h:343	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f429xx.h:344	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f429xx.h:345	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f429xx.h:354	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f429xx.h:355	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f429xx.h:356	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f429xx.h:357	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f429xx.h:358	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f429xx.h:359	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f429xx.h:364	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f429xx.h:365	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f429xx.h:366	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f429xx.h:367	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f429xx.h:376	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
stm32f429xx.h:377	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
stm32f429xx.h:378	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
stm32f429xx.h:379	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
stm32f429xx.h:380	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
stm32f429xx.h:381	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
stm32f429xx.h:382	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
stm32f429xx.h:383	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
stm32f429xx.h:384	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
stm32f429xx.h:385	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
stm32f429xx.h:386	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
stm32f429xx.h:387	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
stm32f429xx.h:388	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
stm32f429xx.h:389	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
stm32f429xx.h:390	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
stm32f429xx.h:391	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
stm32f429xx.h:392	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
stm32f429xx.h:393	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
stm32f429xx.h:394	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
stm32f429xx.h:395	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
stm32f429xx.h:397	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
stm32f429xx.h:398	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
stm32f429xx.h:407	__IO uint32_t MACCR;
stm32f429xx.h:408	__IO uint32_t MACFFR;
stm32f429xx.h:409	__IO uint32_t MACHTHR;
stm32f429xx.h:410	__IO uint32_t MACHTLR;
stm32f429xx.h:411	__IO uint32_t MACMIIAR;
stm32f429xx.h:412	__IO uint32_t MACMIIDR;
stm32f429xx.h:413	__IO uint32_t MACFCR;
stm32f429xx.h:414	__IO uint32_t MACVLANTR; /* 8 */
stm32f429xx.h:416	__IO uint32_t MACRWUFFR; /* 11 */
stm32f429xx.h:417	__IO uint32_t MACPMTCSR;
stm32f429xx.h:419	__IO uint32_t MACDBGR;
stm32f429xx.h:420	__IO uint32_t MACSR; /* 15 */
stm32f429xx.h:421	__IO uint32_t MACIMR;
stm32f429xx.h:422	__IO uint32_t MACA0HR;
stm32f429xx.h:423	__IO uint32_t MACA0LR;
stm32f429xx.h:424	__IO uint32_t MACA1HR;
stm32f429xx.h:425	__IO uint32_t MACA1LR;
stm32f429xx.h:426	__IO uint32_t MACA2HR;
stm32f429xx.h:427	__IO uint32_t MACA2LR;
stm32f429xx.h:428	__IO uint32_t MACA3HR;
stm32f429xx.h:429	__IO uint32_t MACA3LR; /* 24 */
stm32f429xx.h:431	__IO uint32_t MMCCR; /* 65 */
stm32f429xx.h:432	__IO uint32_t MMCRIR;
stm32f429xx.h:433	__IO uint32_t MMCTIR;
stm32f429xx.h:434	__IO uint32_t MMCRIMR;
stm32f429xx.h:435	__IO uint32_t MMCTIMR; /* 69 */
stm32f429xx.h:437	__IO uint32_t MMCTGFSCCR; /* 84 */
stm32f429xx.h:438	__IO uint32_t MMCTGFMSCCR;
stm32f429xx.h:440	__IO uint32_t MMCTGFCR;
stm32f429xx.h:442	__IO uint32_t MMCRFCECR;
stm32f429xx.h:443	__IO uint32_t MMCRFAECR;
stm32f429xx.h:445	__IO uint32_t MMCRGUFCR;
stm32f429xx.h:447	__IO uint32_t PTPTSCR;
stm32f429xx.h:448	__IO uint32_t PTPSSIR;
stm32f429xx.h:449	__IO uint32_t PTPTSHR;
stm32f429xx.h:450	__IO uint32_t PTPTSLR;
stm32f429xx.h:451	__IO uint32_t PTPTSHUR;
stm32f429xx.h:452	__IO uint32_t PTPTSLUR;
stm32f429xx.h:453	__IO uint32_t PTPTSAR;
stm32f429xx.h:454	__IO uint32_t PTPTTHR;
stm32f429xx.h:455	__IO uint32_t PTPTTLR;
stm32f429xx.h:456	__IO uint32_t RESERVED8;
stm32f429xx.h:457	__IO uint32_t PTPTSSR;
stm32f429xx.h:459	__IO uint32_t DMABMR;
stm32f429xx.h:460	__IO uint32_t DMATPDR;
stm32f429xx.h:461	__IO uint32_t DMARPDR;
stm32f429xx.h:462	__IO uint32_t DMARDLAR;
stm32f429xx.h:463	__IO uint32_t DMATDLAR;
stm32f429xx.h:464	__IO uint32_t DMASR;
stm32f429xx.h:465	__IO uint32_t DMAOMR;
stm32f429xx.h:466	__IO uint32_t DMAIER;
stm32f429xx.h:467	__IO uint32_t DMAMFBOCR;
stm32f429xx.h:468	__IO uint32_t DMARSWTR;
stm32f429xx.h:470	__IO uint32_t DMACHTDR;
stm32f429xx.h:471	__IO uint32_t DMACHRDR;
stm32f429xx.h:472	__IO uint32_t DMACHTBAR;
stm32f429xx.h:473	__IO uint32_t DMACHRBAR;
stm32f429xx.h:482	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f429xx.h:483	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f429xx.h:484	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f429xx.h:485	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f429xx.h:486	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f429xx.h:487	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f429xx.h:496	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f429xx.h:497	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f429xx.h:498	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f429xx.h:499	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f429xx.h:500	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f429xx.h:501	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f429xx.h:502	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f429xx.h:511	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f429xx.h:520	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f429xx.h:528	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
stm32f429xx.h:529	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
stm32f429xx.h:530	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
stm32f429xx.h:531	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
stm32f429xx.h:533	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
stm32f429xx.h:536	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
stm32f429xx.h:537	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
stm32f429xx.h:538	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
stm32f429xx.h:539	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
stm32f429xx.h:541	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
stm32f429xx.h:550	__IO uint32_t PCR4; /!< PC Card control register 4, Address offset: 0xA0 /
stm32f429xx.h:551	__IO uint32_t SR4; /!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 /
stm32f429xx.h:552	__IO uint32_t PMEM4; /!< PC Card Common memory space timing register 4, Address offset: 0xA8 /
stm32f429xx.h:553	__IO uint32_t PATT4; /!< PC Card Attribute memory space timing register 4, Address offset: 0xAC /
stm32f429xx.h:554	__IO uint32_t PIO4; /!< PC Card I/O space timing register 4, Address offset: 0xB0 /
stm32f429xx.h:563	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
stm32f429xx.h:564	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
stm32f429xx.h:565	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
stm32f429xx.h:566	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
stm32f429xx.h:567	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
stm32f429xx.h:576	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f429xx.h:577	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f429xx.h:578	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f429xx.h:579	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f429xx.h:580	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f429xx.h:581	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f429xx.h:582	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f429xx.h:583	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f429xx.h:584	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f429xx.h:593	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f429xx.h:594	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f429xx.h:595	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f429xx.h:597	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f429xx.h:606	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f429xx.h:607	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f429xx.h:608	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f429xx.h:609	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f429xx.h:610	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f429xx.h:611	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f429xx.h:612	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f429xx.h:613	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f429xx.h:614	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f429xx.h:615	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f429xx.h:624	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f429xx.h:625	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f429xx.h:626	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f429xx.h:627	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f429xx.h:637	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
stm32f429xx.h:638	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
stm32f429xx.h:639	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
stm32f429xx.h:640	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
stm32f429xx.h:641	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
stm32f429xx.h:643	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
stm32f429xx.h:645	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
stm32f429xx.h:647	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
stm32f429xx.h:648	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
stm32f429xx.h:649	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
stm32f429xx.h:650	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
stm32f429xx.h:651	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
stm32f429xx.h:652	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
stm32f429xx.h:661	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
stm32f429xx.h:662	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
stm32f429xx.h:663	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
stm32f429xx.h:664	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
stm32f429xx.h:665	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
stm32f429xx.h:666	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
stm32f429xx.h:667	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
stm32f429xx.h:668	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
stm32f429xx.h:670	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
stm32f429xx.h:671	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
stm32f429xx.h:672	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
stm32f429xx.h:674	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144/
stm32f429xx.h:683	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f429xx.h:684	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f429xx.h:693	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f429xx.h:694	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f429xx.h:695	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f429xx.h:696	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f429xx.h:697	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f429xx.h:698	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f429xx.h:699	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f429xx.h:701	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f429xx.h:702	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f429xx.h:704	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f429xx.h:705	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f429xx.h:706	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f429xx.h:708	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f429xx.h:709	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f429xx.h:711	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f429xx.h:712	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f429xx.h:713	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f429xx.h:715	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f429xx.h:716	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f429xx.h:718	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f429xx.h:719	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f429xx.h:721	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f429xx.h:722	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f429xx.h:723	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
stm32f429xx.h:724	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f429xx.h:733	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f429xx.h:734	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f429xx.h:735	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f429xx.h:736	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f429xx.h:737	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f429xx.h:738	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f429xx.h:739	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f429xx.h:740	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f429xx.h:741	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f429xx.h:742	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f429xx.h:743	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f429xx.h:744	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f429xx.h:745	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f429xx.h:746	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f429xx.h:747	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f429xx.h:748	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f429xx.h:749	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f429xx.h:750	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f429xx.h:751	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f429xx.h:753	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f429xx.h:754	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f429xx.h:755	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f429xx.h:756	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f429xx.h:757	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f429xx.h:758	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f429xx.h:759	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f429xx.h:760	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f429xx.h:761	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f429xx.h:762	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f429xx.h:763	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f429xx.h:764	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f429xx.h:765	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f429xx.h:766	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f429xx.h:767	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f429xx.h:768	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f429xx.h:769	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f429xx.h:770	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f429xx.h:771	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f429xx.h:772	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f429xx.h:781	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
stm32f429xx.h:786	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
stm32f429xx.h:787	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
stm32f429xx.h:788	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
stm32f429xx.h:789	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
stm32f429xx.h:790	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
stm32f429xx.h:791	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
stm32f429xx.h:792	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
stm32f429xx.h:793	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
stm32f429xx.h:802	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f429xx.h:803	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f429xx.h:804	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f429xx.h:805	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f429xx.h:806	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f429xx.h:807	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f429xx.h:808	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f429xx.h:809	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f429xx.h:810	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f429xx.h:811	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f429xx.h:812	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f429xx.h:813	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f429xx.h:814	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f429xx.h:815	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f429xx.h:816	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f429xx.h:817	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f429xx.h:819	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f429xx.h:821	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f429xx.h:830	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f429xx.h:831	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f429xx.h:832	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f429xx.h:833	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f429xx.h:834	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f429xx.h:835	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f429xx.h:836	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f429xx.h:837	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f429xx.h:838	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f429xx.h:848	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f429xx.h:849	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f429xx.h:850	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f429xx.h:851	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f429xx.h:852	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f429xx.h:853	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f429xx.h:854	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f429xx.h:855	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f429xx.h:856	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f429xx.h:857	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f429xx.h:858	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f429xx.h:859	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f429xx.h:860	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f429xx.h:861	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f429xx.h:862	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f429xx.h:863	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f429xx.h:864	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f429xx.h:865	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f429xx.h:866	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f429xx.h:867	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f429xx.h:868	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f429xx.h:877	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f429xx.h:878	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f429xx.h:879	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f429xx.h:880	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f429xx.h:881	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f429xx.h:882	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f429xx.h:883	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f429xx.h:892	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f429xx.h:893	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f429xx.h:894	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f429xx.h:903	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f429xx.h:904	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f429xx.h:905	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f429xx.h:913	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f429xx.h:914	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f429xx.h:915	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f429xx.h:916	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f429xx.h:917	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f429xx.h:918	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f429xx.h:919	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f429xx.h:920	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f429xx.h:921	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f429xx.h:922	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f429xx.h:923	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f429xx.h:924	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f429xx.h:926	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f429xx.h:927	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f429xx.h:929	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f429xx.h:930	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f429xx.h:938	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f429xx.h:939	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f429xx.h:940	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f429xx.h:942	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f429xx.h:943	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f429xx.h:944	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f429xx.h:945	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f429xx.h:948	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f429xx.h:949	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f429xx.h:950	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f429xx.h:951	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f429xx.h:952	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f429xx.h:953	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f429xx.h:955	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f429xx.h:957	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f429xx.h:965	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f429xx.h:967	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f429xx.h:969	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f429xx.h:970	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f429xx.h:971	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f429xx.h:980	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f429xx.h:982	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f429xx.h:984	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f429xx.h:985	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f429xx.h:994	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f429xx.h:995	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f429xx.h:996	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f429xx.h:998	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f429xx.h:999	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f429xx.h:1000	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f429xx.h:1008	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f429xx.h:1009	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f429xx.h:1010	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f429xx.h:1011	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f429xx.h:1012	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f429xx.h:1013	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f439xx.h:188	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f439xx.h:189	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f439xx.h:190	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f439xx.h:191	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f439xx.h:192	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f439xx.h:193	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f439xx.h:194	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f439xx.h:195	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f439xx.h:196	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f439xx.h:197	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f439xx.h:198	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f439xx.h:199	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f439xx.h:200	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f439xx.h:201	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f439xx.h:202	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f439xx.h:203	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f439xx.h:204	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f439xx.h:205	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f439xx.h:206	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f439xx.h:207	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f439xx.h:212	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f439xx.h:213	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f439xx.h:214	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f439xx.h:225	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f439xx.h:226	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f439xx.h:227	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f439xx.h:228	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f439xx.h:237	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f439xx.h:238	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f439xx.h:239	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f439xx.h:240	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f439xx.h:249	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f439xx.h:250	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f439xx.h:259	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f439xx.h:260	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f439xx.h:261	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f439xx.h:262	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f439xx.h:263	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f439xx.h:264	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f439xx.h:265	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f439xx.h:266	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f439xx.h:271	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f439xx.h:272	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f439xx.h:274	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f439xx.h:276	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f439xx.h:278	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f439xx.h:289	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f439xx.h:290	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f439xx.h:293	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f439xx.h:302	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f439xx.h:303	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f439xx.h:304	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f439xx.h:305	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f439xx.h:306	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f439xx.h:307	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f439xx.h:308	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f439xx.h:309	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f439xx.h:310	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f439xx.h:311	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f439xx.h:312	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f439xx.h:313	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f439xx.h:314	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f439xx.h:315	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f439xx.h:324	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f439xx.h:325	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f439xx.h:326	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f439xx.h:327	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f439xx.h:336	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f439xx.h:337	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f439xx.h:338	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f439xx.h:339	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f439xx.h:340	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f439xx.h:341	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f439xx.h:342	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f439xx.h:343	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f439xx.h:344	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f439xx.h:345	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f439xx.h:346	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f439xx.h:355	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f439xx.h:356	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f439xx.h:357	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f439xx.h:358	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f439xx.h:359	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f439xx.h:360	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f439xx.h:365	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f439xx.h:366	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f439xx.h:367	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f439xx.h:368	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f439xx.h:377	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
stm32f439xx.h:378	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
stm32f439xx.h:379	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
stm32f439xx.h:380	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
stm32f439xx.h:381	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
stm32f439xx.h:382	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
stm32f439xx.h:383	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
stm32f439xx.h:384	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
stm32f439xx.h:385	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
stm32f439xx.h:386	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
stm32f439xx.h:387	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
stm32f439xx.h:388	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
stm32f439xx.h:389	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
stm32f439xx.h:390	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
stm32f439xx.h:391	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
stm32f439xx.h:392	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
stm32f439xx.h:393	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
stm32f439xx.h:394	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
stm32f439xx.h:395	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
stm32f439xx.h:396	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
stm32f439xx.h:398	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
stm32f439xx.h:399	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
stm32f439xx.h:408	__IO uint32_t MACCR;
stm32f439xx.h:409	__IO uint32_t MACFFR;
stm32f439xx.h:410	__IO uint32_t MACHTHR;
stm32f439xx.h:411	__IO uint32_t MACHTLR;
stm32f439xx.h:412	__IO uint32_t MACMIIAR;
stm32f439xx.h:413	__IO uint32_t MACMIIDR;
stm32f439xx.h:414	__IO uint32_t MACFCR;
stm32f439xx.h:415	__IO uint32_t MACVLANTR; /* 8 */
stm32f439xx.h:417	__IO uint32_t MACRWUFFR; /* 11 */
stm32f439xx.h:418	__IO uint32_t MACPMTCSR;
stm32f439xx.h:420	__IO uint32_t MACDBGR;
stm32f439xx.h:421	__IO uint32_t MACSR; /* 15 */
stm32f439xx.h:422	__IO uint32_t MACIMR;
stm32f439xx.h:423	__IO uint32_t MACA0HR;
stm32f439xx.h:424	__IO uint32_t MACA0LR;
stm32f439xx.h:425	__IO uint32_t MACA1HR;
stm32f439xx.h:426	__IO uint32_t MACA1LR;
stm32f439xx.h:427	__IO uint32_t MACA2HR;
stm32f439xx.h:428	__IO uint32_t MACA2LR;
stm32f439xx.h:429	__IO uint32_t MACA3HR;
stm32f439xx.h:430	__IO uint32_t MACA3LR; /* 24 */
stm32f439xx.h:432	__IO uint32_t MMCCR; /* 65 */
stm32f439xx.h:433	__IO uint32_t MMCRIR;
stm32f439xx.h:434	__IO uint32_t MMCTIR;
stm32f439xx.h:435	__IO uint32_t MMCRIMR;
stm32f439xx.h:436	__IO uint32_t MMCTIMR; /* 69 */
stm32f439xx.h:438	__IO uint32_t MMCTGFSCCR; /* 84 */
stm32f439xx.h:439	__IO uint32_t MMCTGFMSCCR;
stm32f439xx.h:441	__IO uint32_t MMCTGFCR;
stm32f439xx.h:443	__IO uint32_t MMCRFCECR;
stm32f439xx.h:444	__IO uint32_t MMCRFAECR;
stm32f439xx.h:446	__IO uint32_t MMCRGUFCR;
stm32f439xx.h:448	__IO uint32_t PTPTSCR;
stm32f439xx.h:449	__IO uint32_t PTPSSIR;
stm32f439xx.h:450	__IO uint32_t PTPTSHR;
stm32f439xx.h:451	__IO uint32_t PTPTSLR;
stm32f439xx.h:452	__IO uint32_t PTPTSHUR;
stm32f439xx.h:453	__IO uint32_t PTPTSLUR;
stm32f439xx.h:454	__IO uint32_t PTPTSAR;
stm32f439xx.h:455	__IO uint32_t PTPTTHR;
stm32f439xx.h:456	__IO uint32_t PTPTTLR;
stm32f439xx.h:457	__IO uint32_t RESERVED8;
stm32f439xx.h:458	__IO uint32_t PTPTSSR;
stm32f439xx.h:460	__IO uint32_t DMABMR;
stm32f439xx.h:461	__IO uint32_t DMATPDR;
stm32f439xx.h:462	__IO uint32_t DMARPDR;
stm32f439xx.h:463	__IO uint32_t DMARDLAR;
stm32f439xx.h:464	__IO uint32_t DMATDLAR;
stm32f439xx.h:465	__IO uint32_t DMASR;
stm32f439xx.h:466	__IO uint32_t DMAOMR;
stm32f439xx.h:467	__IO uint32_t DMAIER;
stm32f439xx.h:468	__IO uint32_t DMAMFBOCR;
stm32f439xx.h:469	__IO uint32_t DMARSWTR;
stm32f439xx.h:471	__IO uint32_t DMACHTDR;
stm32f439xx.h:472	__IO uint32_t DMACHRDR;
stm32f439xx.h:473	__IO uint32_t DMACHTBAR;
stm32f439xx.h:474	__IO uint32_t DMACHRBAR;
stm32f439xx.h:483	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f439xx.h:484	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f439xx.h:485	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f439xx.h:486	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f439xx.h:487	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f439xx.h:488	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f439xx.h:497	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f439xx.h:498	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f439xx.h:499	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f439xx.h:500	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f439xx.h:501	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f439xx.h:502	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f439xx.h:503	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f439xx.h:512	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f439xx.h:521	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f439xx.h:529	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
stm32f439xx.h:530	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
stm32f439xx.h:531	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
stm32f439xx.h:532	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
stm32f439xx.h:534	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
stm32f439xx.h:537	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
stm32f439xx.h:538	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
stm32f439xx.h:539	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
stm32f439xx.h:540	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
stm32f439xx.h:542	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
stm32f439xx.h:551	__IO uint32_t PCR4; /!< PC Card control register 4, Address offset: 0xA0 /
stm32f439xx.h:552	__IO uint32_t SR4; /!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 /
stm32f439xx.h:553	__IO uint32_t PMEM4; /!< PC Card Common memory space timing register 4, Address offset: 0xA8 /
stm32f439xx.h:554	__IO uint32_t PATT4; /!< PC Card Attribute memory space timing register 4, Address offset: 0xAC /
stm32f439xx.h:555	__IO uint32_t PIO4; /!< PC Card I/O space timing register 4, Address offset: 0xB0 /
stm32f439xx.h:564	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
stm32f439xx.h:565	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
stm32f439xx.h:566	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
stm32f439xx.h:567	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
stm32f439xx.h:568	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
stm32f439xx.h:577	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f439xx.h:578	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f439xx.h:579	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f439xx.h:580	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f439xx.h:581	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f439xx.h:582	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f439xx.h:583	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f439xx.h:584	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f439xx.h:585	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f439xx.h:594	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f439xx.h:595	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f439xx.h:596	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f439xx.h:598	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f439xx.h:607	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f439xx.h:608	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f439xx.h:609	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f439xx.h:610	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f439xx.h:611	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f439xx.h:612	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f439xx.h:613	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f439xx.h:614	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f439xx.h:615	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f439xx.h:616	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f439xx.h:625	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f439xx.h:626	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f439xx.h:627	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f439xx.h:628	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f439xx.h:638	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
stm32f439xx.h:639	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
stm32f439xx.h:640	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
stm32f439xx.h:641	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
stm32f439xx.h:642	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
stm32f439xx.h:644	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
stm32f439xx.h:646	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
stm32f439xx.h:648	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
stm32f439xx.h:649	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
stm32f439xx.h:650	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
stm32f439xx.h:651	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
stm32f439xx.h:652	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
stm32f439xx.h:653	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
stm32f439xx.h:662	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
stm32f439xx.h:663	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
stm32f439xx.h:664	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
stm32f439xx.h:665	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
stm32f439xx.h:666	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
stm32f439xx.h:667	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
stm32f439xx.h:668	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
stm32f439xx.h:669	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
stm32f439xx.h:671	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
stm32f439xx.h:672	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
stm32f439xx.h:673	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
stm32f439xx.h:675	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144/
stm32f439xx.h:684	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f439xx.h:685	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f439xx.h:694	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f439xx.h:695	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f439xx.h:696	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f439xx.h:697	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f439xx.h:698	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f439xx.h:699	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f439xx.h:700	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f439xx.h:702	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f439xx.h:703	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f439xx.h:705	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f439xx.h:706	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f439xx.h:707	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f439xx.h:709	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f439xx.h:710	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f439xx.h:712	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f439xx.h:713	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f439xx.h:714	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f439xx.h:716	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f439xx.h:717	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f439xx.h:719	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f439xx.h:720	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f439xx.h:722	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f439xx.h:723	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f439xx.h:724	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
stm32f439xx.h:725	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f439xx.h:734	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f439xx.h:735	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f439xx.h:736	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f439xx.h:737	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f439xx.h:738	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f439xx.h:739	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f439xx.h:740	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f439xx.h:741	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f439xx.h:742	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f439xx.h:743	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f439xx.h:744	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f439xx.h:745	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f439xx.h:746	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f439xx.h:747	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f439xx.h:748	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f439xx.h:749	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f439xx.h:750	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f439xx.h:751	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f439xx.h:752	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f439xx.h:754	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f439xx.h:755	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f439xx.h:756	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f439xx.h:757	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f439xx.h:758	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f439xx.h:759	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f439xx.h:760	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f439xx.h:761	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f439xx.h:762	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f439xx.h:763	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f439xx.h:764	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f439xx.h:765	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f439xx.h:766	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f439xx.h:767	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f439xx.h:768	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f439xx.h:769	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f439xx.h:770	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f439xx.h:771	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f439xx.h:772	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f439xx.h:773	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f439xx.h:782	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
stm32f439xx.h:787	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
stm32f439xx.h:788	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
stm32f439xx.h:789	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
stm32f439xx.h:790	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
stm32f439xx.h:791	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
stm32f439xx.h:792	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
stm32f439xx.h:793	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
stm32f439xx.h:794	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
stm32f439xx.h:803	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f439xx.h:804	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f439xx.h:805	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f439xx.h:806	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f439xx.h:807	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f439xx.h:808	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f439xx.h:809	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f439xx.h:810	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f439xx.h:811	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f439xx.h:812	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f439xx.h:813	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f439xx.h:814	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f439xx.h:815	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f439xx.h:816	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f439xx.h:817	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f439xx.h:818	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f439xx.h:820	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f439xx.h:822	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f439xx.h:831	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f439xx.h:832	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f439xx.h:833	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f439xx.h:834	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f439xx.h:835	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f439xx.h:836	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f439xx.h:837	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f439xx.h:838	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f439xx.h:839	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f439xx.h:849	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f439xx.h:850	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f439xx.h:851	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f439xx.h:852	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f439xx.h:853	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f439xx.h:854	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f439xx.h:855	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f439xx.h:856	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f439xx.h:857	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f439xx.h:858	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f439xx.h:859	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f439xx.h:860	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f439xx.h:861	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f439xx.h:862	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f439xx.h:863	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f439xx.h:864	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f439xx.h:865	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f439xx.h:866	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f439xx.h:867	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f439xx.h:868	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f439xx.h:869	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f439xx.h:878	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f439xx.h:879	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f439xx.h:880	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f439xx.h:881	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f439xx.h:882	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f439xx.h:883	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f439xx.h:884	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f439xx.h:893	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f439xx.h:894	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f439xx.h:895	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f439xx.h:904	__IO uint32_t CR; /!< CRYP control register, Address offset: 0x00 /
stm32f439xx.h:905	__IO uint32_t SR; /!< CRYP status register, Address offset: 0x04 /
stm32f439xx.h:906	__IO uint32_t DIN; /!< CRYP data input register, Address offset: 0x08 /
stm32f439xx.h:907	__IO uint32_t DOUT; /!< CRYP data output register, Address offset: 0x0C /
stm32f439xx.h:908	__IO uint32_t DMACR; /!< CRYP DMA control register, Address offset: 0x10 /
stm32f439xx.h:909	__IO uint32_t IMSCR; /!< CRYP interrupt mask set/clear register, Address offset: 0x14 /
stm32f439xx.h:910	__IO uint32_t RISR; /!< CRYP raw interrupt status register, Address offset: 0x18 /
stm32f439xx.h:911	__IO uint32_t MISR; /!< CRYP masked interrupt status register, Address offset: 0x1C /
stm32f439xx.h:912	__IO uint32_t K0LR; /!< CRYP key left register 0, Address offset: 0x20 /
stm32f439xx.h:913	__IO uint32_t K0RR; /!< CRYP key right register 0, Address offset: 0x24 /
stm32f439xx.h:914	__IO uint32_t K1LR; /!< CRYP key left register 1, Address offset: 0x28 /
stm32f439xx.h:915	__IO uint32_t K1RR; /!< CRYP key right register 1, Address offset: 0x2C /
stm32f439xx.h:916	__IO uint32_t K2LR; /!< CRYP key left register 2, Address offset: 0x30 /
stm32f439xx.h:917	__IO uint32_t K2RR; /!< CRYP key right register 2, Address offset: 0x34 /
stm32f439xx.h:918	__IO uint32_t K3LR; /!< CRYP key left register 3, Address offset: 0x38 /
stm32f439xx.h:919	__IO uint32_t K3RR; /!< CRYP key right register 3, Address offset: 0x3C /
stm32f439xx.h:920	__IO uint32_t IV0LR; /!< CRYP initialization vector left-word register 0, Address offset: 0x40 /
stm32f439xx.h:921	__IO uint32_t IV0RR; /!< CRYP initialization vector right-word register 0, Address offset: 0x44 /
stm32f439xx.h:922	__IO uint32_t IV1LR; /!< CRYP initialization vector left-word register 1, Address offset: 0x48 /
stm32f439xx.h:923	__IO uint32_t IV1RR; /!< CRYP initialization vector right-word register 1, Address offset: 0x4C /
stm32f439xx.h:924	__IO uint32_t CSGCMCCM0R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 /
stm32f439xx.h:925	__IO uint32_t CSGCMCCM1R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 /
stm32f439xx.h:926	__IO uint32_t CSGCMCCM2R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 /
stm32f439xx.h:927	__IO uint32_t CSGCMCCM3R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C /
stm32f439xx.h:928	__IO uint32_t CSGCMCCM4R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 /
stm32f439xx.h:929	__IO uint32_t CSGCMCCM5R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 /
stm32f439xx.h:930	__IO uint32_t CSGCMCCM6R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 /
stm32f439xx.h:931	__IO uint32_t CSGCMCCM7R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C /
stm32f439xx.h:932	__IO uint32_t CSGCM0R; /!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 /
stm32f439xx.h:933	__IO uint32_t CSGCM1R; /!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 /
stm32f439xx.h:934	__IO uint32_t CSGCM2R; /!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 /
stm32f439xx.h:935	__IO uint32_t CSGCM3R; /!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C /
stm32f439xx.h:936	__IO uint32_t CSGCM4R; /!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 /
stm32f439xx.h:937	__IO uint32_t CSGCM5R; /!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 /
stm32f439xx.h:938	__IO uint32_t CSGCM6R; /!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 /
stm32f439xx.h:939	__IO uint32_t CSGCM7R; /!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C /
stm32f439xx.h:948	__IO uint32_t CR; /!< HASH control register, Address offset: 0x00 /
stm32f439xx.h:949	__IO uint32_t DIN; /!< HASH data input register, Address offset: 0x04 /
stm32f439xx.h:950	__IO uint32_t STR; /!< HASH start register, Address offset: 0x08 /
stm32f439xx.h:951	__IO uint32_t HR[5]; /!< HASH digest registers, Address offset: 0x0C-0x1C /
stm32f439xx.h:952	__IO uint32_t IMR; /!< HASH interrupt enable register, Address offset: 0x20 /
stm32f439xx.h:953	__IO uint32_t SR; /!< HASH status register, Address offset: 0x24 /
stm32f439xx.h:955	__IO uint32_t CSR[54]; /!< HASH context swap registers, Address offset: 0x0F8-0x1CC /
stm32f439xx.h:964	__IO uint32_t HR[8]; /!< HASH digest registers, Address offset: 0x310-0x32C /
stm32f439xx.h:973	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f439xx.h:974	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f439xx.h:975	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f439xx.h:983	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f439xx.h:984	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f439xx.h:985	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f439xx.h:986	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f439xx.h:987	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f439xx.h:988	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f439xx.h:989	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f439xx.h:990	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f439xx.h:991	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f439xx.h:992	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f439xx.h:993	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f439xx.h:994	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f439xx.h:996	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f439xx.h:997	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f439xx.h:999	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f439xx.h:1000	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f439xx.h:1008	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f439xx.h:1009	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f439xx.h:1010	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f439xx.h:1012	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f439xx.h:1013	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f439xx.h:1014	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f439xx.h:1015	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f439xx.h:1018	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f439xx.h:1019	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f439xx.h:1020	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f439xx.h:1021	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f439xx.h:1022	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f439xx.h:1023	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f439xx.h:1025	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f439xx.h:1027	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f439xx.h:1035	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f439xx.h:1037	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f439xx.h:1039	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f439xx.h:1040	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f439xx.h:1041	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f439xx.h:1050	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f439xx.h:1052	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f439xx.h:1054	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f439xx.h:1055	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f439xx.h:1064	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f439xx.h:1065	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f439xx.h:1066	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f439xx.h:1068	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f439xx.h:1069	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f439xx.h:1070	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f439xx.h:1078	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f439xx.h:1079	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f439xx.h:1080	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f439xx.h:1081	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f439xx.h:1082	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f439xx.h:1083	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f446xx.h:183	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f446xx.h:184	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f446xx.h:185	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f446xx.h:186	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f446xx.h:187	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f446xx.h:188	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f446xx.h:189	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f446xx.h:190	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f446xx.h:191	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f446xx.h:192	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f446xx.h:193	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f446xx.h:194	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f446xx.h:195	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f446xx.h:196	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f446xx.h:197	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f446xx.h:198	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f446xx.h:199	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f446xx.h:200	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f446xx.h:201	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f446xx.h:202	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f446xx.h:207	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f446xx.h:208	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f446xx.h:209	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f446xx.h:220	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f446xx.h:221	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f446xx.h:222	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f446xx.h:223	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f446xx.h:232	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f446xx.h:233	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f446xx.h:234	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f446xx.h:235	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f446xx.h:244	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f446xx.h:245	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f446xx.h:254	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f446xx.h:255	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f446xx.h:256	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f446xx.h:257	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f446xx.h:258	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f446xx.h:259	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f446xx.h:260	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f446xx.h:261	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f446xx.h:266	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f446xx.h:267	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f446xx.h:269	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f446xx.h:271	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f446xx.h:273	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f446xx.h:285	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
stm32f446xx.h:286	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
stm32f446xx.h:287	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
stm32f446xx.h:288	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
stm32f446xx.h:289	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
stm32f446xx.h:290	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
stm32f446xx.h:298	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f446xx.h:299	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f446xx.h:302	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f446xx.h:311	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f446xx.h:312	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f446xx.h:313	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f446xx.h:314	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f446xx.h:315	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f446xx.h:316	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f446xx.h:317	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f446xx.h:318	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f446xx.h:319	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f446xx.h:320	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f446xx.h:321	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f446xx.h:322	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f446xx.h:323	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f446xx.h:324	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f446xx.h:333	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f446xx.h:334	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f446xx.h:335	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f446xx.h:336	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f446xx.h:345	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f446xx.h:346	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f446xx.h:347	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f446xx.h:348	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f446xx.h:349	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f446xx.h:350	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f446xx.h:351	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f446xx.h:352	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f446xx.h:353	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f446xx.h:354	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f446xx.h:355	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f446xx.h:364	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f446xx.h:365	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f446xx.h:366	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f446xx.h:367	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f446xx.h:368	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f446xx.h:369	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f446xx.h:374	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f446xx.h:375	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f446xx.h:376	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f446xx.h:377	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f446xx.h:386	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f446xx.h:387	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f446xx.h:388	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f446xx.h:389	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f446xx.h:390	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f446xx.h:391	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f446xx.h:400	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f446xx.h:401	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f446xx.h:402	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f446xx.h:403	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f446xx.h:404	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f446xx.h:405	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f446xx.h:406	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f446xx.h:415	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f446xx.h:424	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f446xx.h:433	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
stm32f446xx.h:434	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
stm32f446xx.h:435	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
stm32f446xx.h:436	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
stm32f446xx.h:438	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
stm32f446xx.h:447	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
stm32f446xx.h:448	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
stm32f446xx.h:449	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
stm32f446xx.h:450	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
stm32f446xx.h:451	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
stm32f446xx.h:460	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f446xx.h:461	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f446xx.h:462	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f446xx.h:463	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f446xx.h:464	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f446xx.h:465	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f446xx.h:466	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f446xx.h:467	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f446xx.h:468	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f446xx.h:477	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f446xx.h:478	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f446xx.h:479	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f446xx.h:481	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f446xx.h:483	__IO uint32_t CFGR; /!< SYSCFG Configuration register, Address offset: 0x2C /
stm32f446xx.h:492	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f446xx.h:493	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f446xx.h:494	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f446xx.h:495	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f446xx.h:496	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f446xx.h:497	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f446xx.h:498	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f446xx.h:499	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f446xx.h:500	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f446xx.h:501	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f446xx.h:510	__IO uint32_t CR1; /!< FMPI2C Control register 1, Address offset: 0x00 /
stm32f446xx.h:511	__IO uint32_t CR2; /!< FMPI2C Control register 2, Address offset: 0x04 /
stm32f446xx.h:512	__IO uint32_t OAR1; /!< FMPI2C Own address 1 register, Address offset: 0x08 /
stm32f446xx.h:513	__IO uint32_t OAR2; /!< FMPI2C Own address 2 register, Address offset: 0x0C /
stm32f446xx.h:514	__IO uint32_t TIMINGR; /!< FMPI2C Timing register, Address offset: 0x10 /
stm32f446xx.h:515	__IO uint32_t TIMEOUTR; /!< FMPI2C Timeout register, Address offset: 0x14 /
stm32f446xx.h:516	__IO uint32_t ISR; /!< FMPI2C Interrupt and status register, Address offset: 0x18 /
stm32f446xx.h:517	__IO uint32_t ICR; /!< FMPI2C Interrupt clear register, Address offset: 0x1C /
stm32f446xx.h:518	__IO uint32_t PECR; /!< FMPI2C PEC register, Address offset: 0x20 /
stm32f446xx.h:519	__IO uint32_t RXDR; /!< FMPI2C Receive data register, Address offset: 0x24 /
stm32f446xx.h:520	__IO uint32_t TXDR; /!< FMPI2C Transmit data register, Address offset: 0x28 /
stm32f446xx.h:529	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f446xx.h:530	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f446xx.h:531	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f446xx.h:532	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f446xx.h:542	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f446xx.h:543	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f446xx.h:552	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f446xx.h:553	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f446xx.h:554	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f446xx.h:555	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f446xx.h:556	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f446xx.h:557	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f446xx.h:558	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f446xx.h:560	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f446xx.h:561	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f446xx.h:563	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f446xx.h:564	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f446xx.h:565	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f446xx.h:567	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f446xx.h:568	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f446xx.h:570	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f446xx.h:571	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f446xx.h:572	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f446xx.h:574	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f446xx.h:575	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f446xx.h:577	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f446xx.h:578	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f446xx.h:580	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f446xx.h:581	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f446xx.h:582	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
stm32f446xx.h:583	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f446xx.h:584	__IO uint32_t CKGATENR; /!< RCC Clocks Gated ENable Register, Address offset: 0x90 /
stm32f446xx.h:585	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 /
stm32f446xx.h:594	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f446xx.h:595	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f446xx.h:596	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f446xx.h:597	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f446xx.h:598	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f446xx.h:599	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f446xx.h:600	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f446xx.h:601	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f446xx.h:602	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f446xx.h:603	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f446xx.h:604	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f446xx.h:605	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f446xx.h:606	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f446xx.h:607	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f446xx.h:608	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f446xx.h:609	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f446xx.h:610	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f446xx.h:611	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f446xx.h:612	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f446xx.h:614	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f446xx.h:615	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f446xx.h:616	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f446xx.h:617	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f446xx.h:618	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f446xx.h:619	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f446xx.h:620	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f446xx.h:621	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f446xx.h:622	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f446xx.h:623	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f446xx.h:624	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f446xx.h:625	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f446xx.h:626	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f446xx.h:627	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f446xx.h:628	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f446xx.h:629	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f446xx.h:630	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f446xx.h:631	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f446xx.h:632	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f446xx.h:633	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f446xx.h:642	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
stm32f446xx.h:647	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
stm32f446xx.h:648	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
stm32f446xx.h:649	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
stm32f446xx.h:650	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
stm32f446xx.h:651	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
stm32f446xx.h:652	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
stm32f446xx.h:653	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
stm32f446xx.h:654	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
stm32f446xx.h:663	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f446xx.h:664	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f446xx.h:665	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f446xx.h:666	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f446xx.h:667	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f446xx.h:668	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f446xx.h:669	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f446xx.h:670	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f446xx.h:671	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f446xx.h:672	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f446xx.h:673	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f446xx.h:674	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f446xx.h:675	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f446xx.h:676	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f446xx.h:677	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f446xx.h:678	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f446xx.h:680	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f446xx.h:682	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f446xx.h:691	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f446xx.h:692	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f446xx.h:693	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f446xx.h:694	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f446xx.h:695	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f446xx.h:696	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f446xx.h:697	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f446xx.h:698	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f446xx.h:699	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f446xx.h:708	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
stm32f446xx.h:709	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
stm32f446xx.h:710	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
stm32f446xx.h:711	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
stm32f446xx.h:712	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
stm32f446xx.h:713	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
stm32f446xx.h:714	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
stm32f446xx.h:715	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
stm32f446xx.h:716	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
stm32f446xx.h:717	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
stm32f446xx.h:718	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
stm32f446xx.h:719	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
stm32f446xx.h:720	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
stm32f446xx.h:729	__IO uint32_t CR; /!< Control register, Address offset: 0x00 /
stm32f446xx.h:730	__IO uint16_t IMR; /!< Interrupt mask register, Address offset: 0x04 /
stm32f446xx.h:732	__IO uint32_t SR; /!< Status register, Address offset: 0x08 /
stm32f446xx.h:733	__IO uint16_t IFCR; /!< Interrupt Flag Clear register, Address offset: 0x0C /
stm32f446xx.h:735	__IO uint32_t DR; /!< Data input register, Address offset: 0x10 /
stm32f446xx.h:736	__IO uint32_t CSR; /!< Channel Status register, Address offset: 0x14 /
stm32f446xx.h:737	__IO uint32_t DIR; /!< Debug Information register, Address offset: 0x18 /
stm32f446xx.h:747	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f446xx.h:748	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f446xx.h:749	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f446xx.h:750	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f446xx.h:751	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f446xx.h:752	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f446xx.h:753	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f446xx.h:754	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f446xx.h:755	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f446xx.h:756	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f446xx.h:757	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f446xx.h:758	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f446xx.h:759	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f446xx.h:760	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f446xx.h:761	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f446xx.h:762	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f446xx.h:763	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f446xx.h:764	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f446xx.h:765	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f446xx.h:766	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f446xx.h:767	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f446xx.h:776	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f446xx.h:777	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f446xx.h:778	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f446xx.h:779	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f446xx.h:780	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f446xx.h:781	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f446xx.h:782	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f446xx.h:791	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f446xx.h:792	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f446xx.h:793	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f446xx.h:800	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f446xx.h:801	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f446xx.h:802	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f446xx.h:803	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f446xx.h:804	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f446xx.h:805	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f446xx.h:806	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f446xx.h:807	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f446xx.h:808	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f446xx.h:809	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f446xx.h:810	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f446xx.h:811	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f446xx.h:813	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f446xx.h:814	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f446xx.h:816	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
stm32f446xx.h:818	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
stm32f446xx.h:820	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
stm32f446xx.h:822	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f446xx.h:823	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f446xx.h:831	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f446xx.h:832	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f446xx.h:833	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f446xx.h:835	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f446xx.h:836	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f446xx.h:837	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f446xx.h:838	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f446xx.h:841	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f446xx.h:842	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f446xx.h:843	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f446xx.h:844	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f446xx.h:845	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f446xx.h:846	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f446xx.h:848	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f446xx.h:850	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f446xx.h:858	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f446xx.h:860	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f446xx.h:862	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f446xx.h:863	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f446xx.h:864	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f446xx.h:873	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f446xx.h:875	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f446xx.h:877	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f446xx.h:878	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f446xx.h:887	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f446xx.h:888	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f446xx.h:889	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f446xx.h:891	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f446xx.h:892	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f446xx.h:893	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f446xx.h:901	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f446xx.h:902	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f446xx.h:903	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f446xx.h:904	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f446xx.h:905	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f446xx.h:906	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f469xx.h:189	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f469xx.h:190	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f469xx.h:191	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f469xx.h:192	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f469xx.h:193	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f469xx.h:194	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f469xx.h:195	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f469xx.h:196	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f469xx.h:197	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f469xx.h:198	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f469xx.h:199	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f469xx.h:200	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f469xx.h:201	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f469xx.h:202	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f469xx.h:203	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f469xx.h:204	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f469xx.h:205	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f469xx.h:206	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f469xx.h:207	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f469xx.h:208	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f469xx.h:213	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f469xx.h:214	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f469xx.h:215	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f469xx.h:226	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f469xx.h:227	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f469xx.h:228	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f469xx.h:229	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f469xx.h:238	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f469xx.h:239	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f469xx.h:240	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f469xx.h:241	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f469xx.h:250	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f469xx.h:251	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f469xx.h:260	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f469xx.h:261	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f469xx.h:262	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f469xx.h:263	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f469xx.h:264	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f469xx.h:265	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f469xx.h:266	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f469xx.h:267	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f469xx.h:272	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f469xx.h:273	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f469xx.h:275	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f469xx.h:277	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f469xx.h:279	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f469xx.h:290	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f469xx.h:291	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f469xx.h:294	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f469xx.h:303	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f469xx.h:304	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f469xx.h:305	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f469xx.h:306	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f469xx.h:307	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f469xx.h:308	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f469xx.h:309	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f469xx.h:310	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f469xx.h:311	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f469xx.h:312	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f469xx.h:313	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f469xx.h:314	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f469xx.h:315	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f469xx.h:316	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f469xx.h:325	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f469xx.h:326	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f469xx.h:327	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f469xx.h:328	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f469xx.h:337	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f469xx.h:338	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f469xx.h:339	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f469xx.h:340	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f469xx.h:341	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f469xx.h:342	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f469xx.h:343	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f469xx.h:344	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f469xx.h:345	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f469xx.h:346	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f469xx.h:347	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f469xx.h:356	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f469xx.h:357	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f469xx.h:358	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f469xx.h:359	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f469xx.h:360	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f469xx.h:361	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f469xx.h:366	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f469xx.h:367	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f469xx.h:368	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f469xx.h:369	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f469xx.h:378	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
stm32f469xx.h:379	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
stm32f469xx.h:380	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
stm32f469xx.h:381	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
stm32f469xx.h:382	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
stm32f469xx.h:383	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
stm32f469xx.h:384	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
stm32f469xx.h:385	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
stm32f469xx.h:386	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
stm32f469xx.h:387	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
stm32f469xx.h:388	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
stm32f469xx.h:389	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
stm32f469xx.h:390	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
stm32f469xx.h:391	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
stm32f469xx.h:392	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
stm32f469xx.h:393	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
stm32f469xx.h:394	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
stm32f469xx.h:395	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
stm32f469xx.h:396	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
stm32f469xx.h:397	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
stm32f469xx.h:399	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
stm32f469xx.h:400	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
stm32f469xx.h:409	__IO uint32_t VR; /!< DSI Host Version Register, Address offset: 0x00 /
stm32f469xx.h:410	__IO uint32_t CR; /!< DSI Host Control Register, Address offset: 0x04 /
stm32f469xx.h:411	__IO uint32_t CCR; /!< DSI HOST Clock Control Register, Address offset: 0x08 /
stm32f469xx.h:412	__IO uint32_t LVCIDR; /!< DSI Host LTDC VCID Register, Address offset: 0x0C /
stm32f469xx.h:413	__IO uint32_t LCOLCR; /!< DSI Host LTDC Color Coding Register, Address offset: 0x10 /
stm32f469xx.h:414	__IO uint32_t LPCR; /!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 /
stm32f469xx.h:415	__IO uint32_t LPMCR; /!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 /
stm32f469xx.h:417	__IO uint32_t PCR; /!< DSI Host Protocol Configuration Register, Address offset: 0x2C /
stm32f469xx.h:418	__IO uint32_t GVCIDR; /!< DSI Host Generic VCID Register, Address offset: 0x30 /
stm32f469xx.h:419	__IO uint32_t MCR; /!< DSI Host Mode Configuration Register, Address offset: 0x34 /
stm32f469xx.h:420	__IO uint32_t VMCR; /!< DSI Host Video Mode Configuration Register, Address offset: 0x38 /
stm32f469xx.h:421	__IO uint32_t VPCR; /!< DSI Host Video Packet Configuration Register, Address offset: 0x3C /
stm32f469xx.h:422	__IO uint32_t VCCR; /!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 /
stm32f469xx.h:423	__IO uint32_t VNPCR; /!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 /
stm32f469xx.h:424	__IO uint32_t VHSACR; /!< DSI Host Video HSA Configuration Register, Address offset: 0x48 /
stm32f469xx.h:425	__IO uint32_t VHBPCR; /!< DSI Host Video HBP Configuration Register, Address offset: 0x4C /
stm32f469xx.h:426	__IO uint32_t VLCR; /!< DSI Host Video Line Configuration Register, Address offset: 0x50 /
stm32f469xx.h:427	__IO uint32_t VVSACR; /!< DSI Host Video VSA Configuration Register, Address offset: 0x54 /
stm32f469xx.h:428	__IO uint32_t VVBPCR; /!< DSI Host Video VBP Configuration Register, Address offset: 0x58 /
stm32f469xx.h:429	__IO uint32_t VVFPCR; /!< DSI Host Video VFP Configuration Register, Address offset: 0x5C /
stm32f469xx.h:430	__IO uint32_t VVACR; /!< DSI Host Video VA Configuration Register, Address offset: 0x60 /
stm32f469xx.h:431	__IO uint32_t LCCR; /!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 /
stm32f469xx.h:432	__IO uint32_t CMCR; /!< DSI Host Command Mode Configuration Register, Address offset: 0x68 /
stm32f469xx.h:433	__IO uint32_t GHCR; /!< DSI Host Generic Header Configuration Register, Address offset: 0x6C /
stm32f469xx.h:434	__IO uint32_t GPDR; /!< DSI Host Generic Payload Data Register, Address offset: 0x70 /
stm32f469xx.h:435	__IO uint32_t GPSR; /!< DSI Host Generic Packet Status Register, Address offset: 0x74 /
stm32f469xx.h:436	__IO uint32_t TCCR[6]; /!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F /
stm32f469xx.h:437	__IO uint32_t TDCR; /!< DSI Host 3D Configuration Register, Address offset: 0x90 /
stm32f469xx.h:438	__IO uint32_t CLCR; /!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 /
stm32f469xx.h:439	__IO uint32_t CLTCR; /!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 /
stm32f469xx.h:440	__IO uint32_t DLTCR; /!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C /
stm32f469xx.h:441	__IO uint32_t PCTLR; /!< DSI Host PHY Control Register, Address offset: 0xA0 /
stm32f469xx.h:442	__IO uint32_t PCONFR; /!< DSI Host PHY Configuration Register, Address offset: 0xA4 /
stm32f469xx.h:443	__IO uint32_t PUCR; /!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 /
stm32f469xx.h:444	__IO uint32_t PTTCR; /!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC /
stm32f469xx.h:445	__IO uint32_t PSR; /!< DSI Host PHY Status Register, Address offset: 0xB0 /
stm32f469xx.h:447	__IO uint32_t ISR[2]; /!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 /
stm32f469xx.h:448	__IO uint32_t IER[2]; /!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB /
stm32f469xx.h:450	__IO uint32_t FIR[2]; /!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF /
stm32f469xx.h:452	__IO uint32_t VSCR; /!< DSI Host Video Shadow Control Register, Address offset: 0x100 /
stm32f469xx.h:454	__IO uint32_t LCVCIDR; /!< DSI Host LTDC Current VCID Register, Address offset: 0x10C /
stm32f469xx.h:455	__IO uint32_t LCCCR; /!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 /
stm32f469xx.h:457	__IO uint32_t LPMCCR; /!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 /
stm32f469xx.h:459	__IO uint32_t VMCCR; /!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 /
stm32f469xx.h:460	__IO uint32_t VPCCR; /!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C /
stm32f469xx.h:461	__IO uint32_t VCCCR; /!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 /
stm32f469xx.h:462	__IO uint32_t VNPCCR; /!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 /
stm32f469xx.h:463	__IO uint32_t VHSACCR; /!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 /
stm32f469xx.h:464	__IO uint32_t VHBPCCR; /!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C /
stm32f469xx.h:465	__IO uint32_t VLCCR; /!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 /
stm32f469xx.h:466	__IO uint32_t VVSACCR; /!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 /
stm32f469xx.h:467	__IO uint32_t VVBPCCR; /!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 /
stm32f469xx.h:468	__IO uint32_t VVFPCCR; /!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C /
stm32f469xx.h:469	__IO uint32_t VVACCR; /!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 /
stm32f469xx.h:471	__IO uint32_t TDCCR; /!< DSI Host 3D Current Configuration Register, Address offset: 0x190 /
stm32f469xx.h:473	__IO uint32_t WCFGR; /!< DSI Wrapper Configuration Register, Address offset: 0x400 /
stm32f469xx.h:474	__IO uint32_t WCR; /!< DSI Wrapper Control Register, Address offset: 0x404 /
stm32f469xx.h:475	__IO uint32_t WIER; /!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 /
stm32f469xx.h:476	__IO uint32_t WISR; /!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C /
stm32f469xx.h:477	__IO uint32_t WIFCR; /!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 /
stm32f469xx.h:479	__IO uint32_t WPCR[5]; /!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B /
stm32f469xx.h:481	__IO uint32_t WRPCR; /!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 /
stm32f469xx.h:490	__IO uint32_t MACCR;
stm32f469xx.h:491	__IO uint32_t MACFFR;
stm32f469xx.h:492	__IO uint32_t MACHTHR;
stm32f469xx.h:493	__IO uint32_t MACHTLR;
stm32f469xx.h:494	__IO uint32_t MACMIIAR;
stm32f469xx.h:495	__IO uint32_t MACMIIDR;
stm32f469xx.h:496	__IO uint32_t MACFCR;
stm32f469xx.h:497	__IO uint32_t MACVLANTR; /* 8 */
stm32f469xx.h:499	__IO uint32_t MACRWUFFR; /* 11 */
stm32f469xx.h:500	__IO uint32_t MACPMTCSR;
stm32f469xx.h:502	__IO uint32_t MACDBGR;
stm32f469xx.h:503	__IO uint32_t MACSR; /* 15 */
stm32f469xx.h:504	__IO uint32_t MACIMR;
stm32f469xx.h:505	__IO uint32_t MACA0HR;
stm32f469xx.h:506	__IO uint32_t MACA0LR;
stm32f469xx.h:507	__IO uint32_t MACA1HR;
stm32f469xx.h:508	__IO uint32_t MACA1LR;
stm32f469xx.h:509	__IO uint32_t MACA2HR;
stm32f469xx.h:510	__IO uint32_t MACA2LR;
stm32f469xx.h:511	__IO uint32_t MACA3HR;
stm32f469xx.h:512	__IO uint32_t MACA3LR; /* 24 */
stm32f469xx.h:514	__IO uint32_t MMCCR; /* 65 */
stm32f469xx.h:515	__IO uint32_t MMCRIR;
stm32f469xx.h:516	__IO uint32_t MMCTIR;
stm32f469xx.h:517	__IO uint32_t MMCRIMR;
stm32f469xx.h:518	__IO uint32_t MMCTIMR; /* 69 */
stm32f469xx.h:520	__IO uint32_t MMCTGFSCCR; /* 84 */
stm32f469xx.h:521	__IO uint32_t MMCTGFMSCCR;
stm32f469xx.h:523	__IO uint32_t MMCTGFCR;
stm32f469xx.h:525	__IO uint32_t MMCRFCECR;
stm32f469xx.h:526	__IO uint32_t MMCRFAECR;
stm32f469xx.h:528	__IO uint32_t MMCRGUFCR;
stm32f469xx.h:530	__IO uint32_t PTPTSCR;
stm32f469xx.h:531	__IO uint32_t PTPSSIR;
stm32f469xx.h:532	__IO uint32_t PTPTSHR;
stm32f469xx.h:533	__IO uint32_t PTPTSLR;
stm32f469xx.h:534	__IO uint32_t PTPTSHUR;
stm32f469xx.h:535	__IO uint32_t PTPTSLUR;
stm32f469xx.h:536	__IO uint32_t PTPTSAR;
stm32f469xx.h:537	__IO uint32_t PTPTTHR;
stm32f469xx.h:538	__IO uint32_t PTPTTLR;
stm32f469xx.h:539	__IO uint32_t RESERVED8;
stm32f469xx.h:540	__IO uint32_t PTPTSSR;
stm32f469xx.h:542	__IO uint32_t DMABMR;
stm32f469xx.h:543	__IO uint32_t DMATPDR;
stm32f469xx.h:544	__IO uint32_t DMARPDR;
stm32f469xx.h:545	__IO uint32_t DMARDLAR;
stm32f469xx.h:546	__IO uint32_t DMATDLAR;
stm32f469xx.h:547	__IO uint32_t DMASR;
stm32f469xx.h:548	__IO uint32_t DMAOMR;
stm32f469xx.h:549	__IO uint32_t DMAIER;
stm32f469xx.h:550	__IO uint32_t DMAMFBOCR;
stm32f469xx.h:551	__IO uint32_t DMARSWTR;
stm32f469xx.h:553	__IO uint32_t DMACHTDR;
stm32f469xx.h:554	__IO uint32_t DMACHRDR;
stm32f469xx.h:555	__IO uint32_t DMACHTBAR;
stm32f469xx.h:556	__IO uint32_t DMACHRBAR;
stm32f469xx.h:565	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f469xx.h:566	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f469xx.h:567	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f469xx.h:568	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f469xx.h:569	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f469xx.h:570	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f469xx.h:579	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f469xx.h:580	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f469xx.h:581	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f469xx.h:582	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f469xx.h:583	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f469xx.h:584	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f469xx.h:585	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f469xx.h:594	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f469xx.h:603	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f469xx.h:612	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
stm32f469xx.h:613	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
stm32f469xx.h:614	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
stm32f469xx.h:615	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
stm32f469xx.h:617	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
stm32f469xx.h:626	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
stm32f469xx.h:627	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
stm32f469xx.h:628	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
stm32f469xx.h:629	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
stm32f469xx.h:630	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
stm32f469xx.h:639	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f469xx.h:640	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f469xx.h:641	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f469xx.h:642	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f469xx.h:643	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f469xx.h:644	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f469xx.h:645	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f469xx.h:646	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f469xx.h:647	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f469xx.h:656	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f469xx.h:657	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f469xx.h:658	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f469xx.h:660	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f469xx.h:669	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f469xx.h:670	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f469xx.h:671	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f469xx.h:672	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f469xx.h:673	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f469xx.h:674	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f469xx.h:675	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f469xx.h:676	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f469xx.h:677	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f469xx.h:678	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f469xx.h:687	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f469xx.h:688	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f469xx.h:689	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f469xx.h:690	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f469xx.h:700	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
stm32f469xx.h:701	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
stm32f469xx.h:702	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
stm32f469xx.h:703	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
stm32f469xx.h:704	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
stm32f469xx.h:706	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
stm32f469xx.h:708	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
stm32f469xx.h:710	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
stm32f469xx.h:711	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
stm32f469xx.h:712	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
stm32f469xx.h:713	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
stm32f469xx.h:714	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
stm32f469xx.h:715	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
stm32f469xx.h:724	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
stm32f469xx.h:725	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
stm32f469xx.h:726	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
stm32f469xx.h:727	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
stm32f469xx.h:728	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
stm32f469xx.h:729	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
stm32f469xx.h:730	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
stm32f469xx.h:731	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
stm32f469xx.h:733	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
stm32f469xx.h:734	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
stm32f469xx.h:735	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
stm32f469xx.h:737	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144/
stm32f469xx.h:746	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f469xx.h:747	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f469xx.h:756	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f469xx.h:757	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f469xx.h:758	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f469xx.h:759	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f469xx.h:760	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f469xx.h:761	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f469xx.h:762	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f469xx.h:764	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f469xx.h:765	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f469xx.h:767	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f469xx.h:768	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f469xx.h:769	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f469xx.h:771	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f469xx.h:772	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f469xx.h:774	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f469xx.h:775	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f469xx.h:776	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f469xx.h:778	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f469xx.h:779	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f469xx.h:781	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f469xx.h:782	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f469xx.h:784	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f469xx.h:785	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f469xx.h:786	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
stm32f469xx.h:787	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f469xx.h:796	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f469xx.h:797	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f469xx.h:798	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f469xx.h:799	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f469xx.h:800	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f469xx.h:801	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f469xx.h:802	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f469xx.h:803	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f469xx.h:804	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f469xx.h:805	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f469xx.h:806	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f469xx.h:807	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f469xx.h:808	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f469xx.h:809	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f469xx.h:810	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f469xx.h:811	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f469xx.h:812	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f469xx.h:813	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f469xx.h:814	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f469xx.h:816	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f469xx.h:817	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f469xx.h:818	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f469xx.h:819	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f469xx.h:820	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f469xx.h:821	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f469xx.h:822	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f469xx.h:823	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f469xx.h:824	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f469xx.h:825	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f469xx.h:826	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f469xx.h:827	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f469xx.h:828	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f469xx.h:829	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f469xx.h:830	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f469xx.h:831	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f469xx.h:832	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f469xx.h:833	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f469xx.h:834	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f469xx.h:835	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f469xx.h:844	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
stm32f469xx.h:849	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
stm32f469xx.h:850	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
stm32f469xx.h:851	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
stm32f469xx.h:852	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
stm32f469xx.h:853	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
stm32f469xx.h:854	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
stm32f469xx.h:855	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
stm32f469xx.h:856	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
stm32f469xx.h:865	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f469xx.h:866	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f469xx.h:867	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f469xx.h:868	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f469xx.h:869	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f469xx.h:870	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f469xx.h:871	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f469xx.h:872	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f469xx.h:873	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f469xx.h:874	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f469xx.h:875	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f469xx.h:876	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f469xx.h:877	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f469xx.h:878	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f469xx.h:879	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f469xx.h:880	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f469xx.h:882	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f469xx.h:884	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f469xx.h:893	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f469xx.h:894	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f469xx.h:895	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f469xx.h:896	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f469xx.h:897	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f469xx.h:898	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f469xx.h:899	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f469xx.h:900	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f469xx.h:901	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f469xx.h:910	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
stm32f469xx.h:911	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
stm32f469xx.h:912	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
stm32f469xx.h:913	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
stm32f469xx.h:914	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
stm32f469xx.h:915	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
stm32f469xx.h:916	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
stm32f469xx.h:917	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
stm32f469xx.h:918	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
stm32f469xx.h:919	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
stm32f469xx.h:920	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
stm32f469xx.h:921	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
stm32f469xx.h:922	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
stm32f469xx.h:931	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f469xx.h:932	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f469xx.h:933	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f469xx.h:934	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f469xx.h:935	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f469xx.h:936	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f469xx.h:937	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f469xx.h:938	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f469xx.h:939	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f469xx.h:940	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f469xx.h:941	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f469xx.h:942	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f469xx.h:943	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f469xx.h:944	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f469xx.h:945	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f469xx.h:946	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f469xx.h:947	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f469xx.h:948	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f469xx.h:949	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f469xx.h:950	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f469xx.h:951	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f469xx.h:960	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f469xx.h:961	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f469xx.h:962	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f469xx.h:963	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f469xx.h:964	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f469xx.h:965	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f469xx.h:966	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f469xx.h:975	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f469xx.h:976	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f469xx.h:977	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f469xx.h:986	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f469xx.h:987	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f469xx.h:988	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f469xx.h:996	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f469xx.h:997	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f469xx.h:998	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f469xx.h:999	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f469xx.h:1000	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f469xx.h:1001	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f469xx.h:1002	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f469xx.h:1003	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f469xx.h:1004	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f469xx.h:1005	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f469xx.h:1006	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f469xx.h:1007	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f469xx.h:1009	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f469xx.h:1010	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f469xx.h:1012	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
stm32f469xx.h:1014	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
stm32f469xx.h:1016	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
stm32f469xx.h:1018	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f469xx.h:1019	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f469xx.h:1027	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f469xx.h:1028	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f469xx.h:1029	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f469xx.h:1031	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f469xx.h:1032	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f469xx.h:1033	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f469xx.h:1034	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f469xx.h:1037	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f469xx.h:1038	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f469xx.h:1039	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f469xx.h:1040	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f469xx.h:1041	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f469xx.h:1042	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f469xx.h:1044	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f469xx.h:1046	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f469xx.h:1054	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f469xx.h:1056	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f469xx.h:1058	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f469xx.h:1059	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f469xx.h:1060	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f469xx.h:1069	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f469xx.h:1071	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f469xx.h:1073	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f469xx.h:1074	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f469xx.h:1083	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f469xx.h:1084	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f469xx.h:1085	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f469xx.h:1087	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f469xx.h:1088	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f469xx.h:1089	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f469xx.h:1097	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f469xx.h:1098	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f469xx.h:1099	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f469xx.h:1100	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f469xx.h:1101	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f469xx.h:1102	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f479xx.h:190	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
stm32f479xx.h:191	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
stm32f479xx.h:192	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
stm32f479xx.h:193	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
stm32f479xx.h:194	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
stm32f479xx.h:195	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
stm32f479xx.h:196	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
stm32f479xx.h:197	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
stm32f479xx.h:198	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
stm32f479xx.h:199	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
stm32f479xx.h:200	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
stm32f479xx.h:201	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
stm32f479xx.h:202	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
stm32f479xx.h:203	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
stm32f479xx.h:204	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
stm32f479xx.h:205	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
stm32f479xx.h:206	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
stm32f479xx.h:207	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
stm32f479xx.h:208	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
stm32f479xx.h:209	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
stm32f479xx.h:214	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
stm32f479xx.h:215	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
stm32f479xx.h:216	__IO uint32_t CDR; /*!< ADC common regular data register for dual
stm32f479xx.h:227	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
stm32f479xx.h:228	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
stm32f479xx.h:229	__IO uint32_t TDLR; /!< CAN mailbox data low register /
stm32f479xx.h:230	__IO uint32_t TDHR; /!< CAN mailbox data high register /
stm32f479xx.h:239	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
stm32f479xx.h:240	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
stm32f479xx.h:241	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
stm32f479xx.h:242	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
stm32f479xx.h:251	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
stm32f479xx.h:252	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
stm32f479xx.h:261	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
stm32f479xx.h:262	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
stm32f479xx.h:263	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
stm32f479xx.h:264	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
stm32f479xx.h:265	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
stm32f479xx.h:266	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
stm32f479xx.h:267	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
stm32f479xx.h:268	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
stm32f479xx.h:273	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
stm32f479xx.h:274	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
stm32f479xx.h:276	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
stm32f479xx.h:278	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
stm32f479xx.h:280	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
stm32f479xx.h:291	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
stm32f479xx.h:292	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
stm32f479xx.h:295	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
stm32f479xx.h:304	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
stm32f479xx.h:305	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
stm32f479xx.h:306	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
stm32f479xx.h:307	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
stm32f479xx.h:308	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
stm32f479xx.h:309	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
stm32f479xx.h:310	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
stm32f479xx.h:311	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
stm32f479xx.h:312	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
stm32f479xx.h:313	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
stm32f479xx.h:314	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
stm32f479xx.h:315	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
stm32f479xx.h:316	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
stm32f479xx.h:317	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
stm32f479xx.h:326	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
stm32f479xx.h:327	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
stm32f479xx.h:328	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
stm32f479xx.h:329	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
stm32f479xx.h:338	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
stm32f479xx.h:339	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
stm32f479xx.h:340	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
stm32f479xx.h:341	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
stm32f479xx.h:342	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
stm32f479xx.h:343	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
stm32f479xx.h:344	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
stm32f479xx.h:345	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
stm32f479xx.h:346	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
stm32f479xx.h:347	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
stm32f479xx.h:348	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
stm32f479xx.h:357	__IO uint32_t CR; /!< DMA stream x configuration register /
stm32f479xx.h:358	__IO uint32_t NDTR; /!< DMA stream x number of data register /
stm32f479xx.h:359	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
stm32f479xx.h:360	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
stm32f479xx.h:361	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
stm32f479xx.h:362	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
stm32f479xx.h:367	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
stm32f479xx.h:368	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
stm32f479xx.h:369	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
stm32f479xx.h:370	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
stm32f479xx.h:379	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
stm32f479xx.h:380	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
stm32f479xx.h:381	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
stm32f479xx.h:382	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
stm32f479xx.h:383	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
stm32f479xx.h:384	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
stm32f479xx.h:385	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
stm32f479xx.h:386	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
stm32f479xx.h:387	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
stm32f479xx.h:388	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
stm32f479xx.h:389	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
stm32f479xx.h:390	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
stm32f479xx.h:391	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
stm32f479xx.h:392	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
stm32f479xx.h:393	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
stm32f479xx.h:394	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
stm32f479xx.h:395	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
stm32f479xx.h:396	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
stm32f479xx.h:397	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
stm32f479xx.h:398	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
stm32f479xx.h:400	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
stm32f479xx.h:401	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
stm32f479xx.h:410	__IO uint32_t VR; /!< DSI Host Version Register, Address offset: 0x00 /
stm32f479xx.h:411	__IO uint32_t CR; /!< DSI Host Control Register, Address offset: 0x04 /
stm32f479xx.h:412	__IO uint32_t CCR; /!< DSI HOST Clock Control Register, Address offset: 0x08 /
stm32f479xx.h:413	__IO uint32_t LVCIDR; /!< DSI Host LTDC VCID Register, Address offset: 0x0C /
stm32f479xx.h:414	__IO uint32_t LCOLCR; /!< DSI Host LTDC Color Coding Register, Address offset: 0x10 /
stm32f479xx.h:415	__IO uint32_t LPCR; /!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 /
stm32f479xx.h:416	__IO uint32_t LPMCR; /!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 /
stm32f479xx.h:418	__IO uint32_t PCR; /!< DSI Host Protocol Configuration Register, Address offset: 0x2C /
stm32f479xx.h:419	__IO uint32_t GVCIDR; /!< DSI Host Generic VCID Register, Address offset: 0x30 /
stm32f479xx.h:420	__IO uint32_t MCR; /!< DSI Host Mode Configuration Register, Address offset: 0x34 /
stm32f479xx.h:421	__IO uint32_t VMCR; /!< DSI Host Video Mode Configuration Register, Address offset: 0x38 /
stm32f479xx.h:422	__IO uint32_t VPCR; /!< DSI Host Video Packet Configuration Register, Address offset: 0x3C /
stm32f479xx.h:423	__IO uint32_t VCCR; /!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 /
stm32f479xx.h:424	__IO uint32_t VNPCR; /!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 /
stm32f479xx.h:425	__IO uint32_t VHSACR; /!< DSI Host Video HSA Configuration Register, Address offset: 0x48 /
stm32f479xx.h:426	__IO uint32_t VHBPCR; /!< DSI Host Video HBP Configuration Register, Address offset: 0x4C /
stm32f479xx.h:427	__IO uint32_t VLCR; /!< DSI Host Video Line Configuration Register, Address offset: 0x50 /
stm32f479xx.h:428	__IO uint32_t VVSACR; /!< DSI Host Video VSA Configuration Register, Address offset: 0x54 /
stm32f479xx.h:429	__IO uint32_t VVBPCR; /!< DSI Host Video VBP Configuration Register, Address offset: 0x58 /
stm32f479xx.h:430	__IO uint32_t VVFPCR; /!< DSI Host Video VFP Configuration Register, Address offset: 0x5C /
stm32f479xx.h:431	__IO uint32_t VVACR; /!< DSI Host Video VA Configuration Register, Address offset: 0x60 /
stm32f479xx.h:432	__IO uint32_t LCCR; /!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 /
stm32f479xx.h:433	__IO uint32_t CMCR; /!< DSI Host Command Mode Configuration Register, Address offset: 0x68 /
stm32f479xx.h:434	__IO uint32_t GHCR; /!< DSI Host Generic Header Configuration Register, Address offset: 0x6C /
stm32f479xx.h:435	__IO uint32_t GPDR; /!< DSI Host Generic Payload Data Register, Address offset: 0x70 /
stm32f479xx.h:436	__IO uint32_t GPSR; /!< DSI Host Generic Packet Status Register, Address offset: 0x74 /
stm32f479xx.h:437	__IO uint32_t TCCR[6]; /!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F /
stm32f479xx.h:438	__IO uint32_t TDCR; /!< DSI Host 3D Configuration Register, Address offset: 0x90 /
stm32f479xx.h:439	__IO uint32_t CLCR; /!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 /
stm32f479xx.h:440	__IO uint32_t CLTCR; /!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 /
stm32f479xx.h:441	__IO uint32_t DLTCR; /!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C /
stm32f479xx.h:442	__IO uint32_t PCTLR; /!< DSI Host PHY Control Register, Address offset: 0xA0 /
stm32f479xx.h:443	__IO uint32_t PCONFR; /!< DSI Host PHY Configuration Register, Address offset: 0xA4 /
stm32f479xx.h:444	__IO uint32_t PUCR; /!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 /
stm32f479xx.h:445	__IO uint32_t PTTCR; /!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC /
stm32f479xx.h:446	__IO uint32_t PSR; /!< DSI Host PHY Status Register, Address offset: 0xB0 /
stm32f479xx.h:448	__IO uint32_t ISR[2]; /!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 /
stm32f479xx.h:449	__IO uint32_t IER[2]; /!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB /
stm32f479xx.h:451	__IO uint32_t FIR[2]; /!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF /
stm32f479xx.h:453	__IO uint32_t VSCR; /!< DSI Host Video Shadow Control Register, Address offset: 0x100 /
stm32f479xx.h:455	__IO uint32_t LCVCIDR; /!< DSI Host LTDC Current VCID Register, Address offset: 0x10C /
stm32f479xx.h:456	__IO uint32_t LCCCR; /!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 /
stm32f479xx.h:458	__IO uint32_t LPMCCR; /!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 /
stm32f479xx.h:460	__IO uint32_t VMCCR; /!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 /
stm32f479xx.h:461	__IO uint32_t VPCCR; /!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C /
stm32f479xx.h:462	__IO uint32_t VCCCR; /!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 /
stm32f479xx.h:463	__IO uint32_t VNPCCR; /!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 /
stm32f479xx.h:464	__IO uint32_t VHSACCR; /!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 /
stm32f479xx.h:465	__IO uint32_t VHBPCCR; /!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C /
stm32f479xx.h:466	__IO uint32_t VLCCR; /!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 /
stm32f479xx.h:467	__IO uint32_t VVSACCR; /!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 /
stm32f479xx.h:468	__IO uint32_t VVBPCCR; /!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 /
stm32f479xx.h:469	__IO uint32_t VVFPCCR; /!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C /
stm32f479xx.h:470	__IO uint32_t VVACCR; /!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 /
stm32f479xx.h:472	__IO uint32_t TDCCR; /!< DSI Host 3D Current Configuration Register, Address offset: 0x190 /
stm32f479xx.h:474	__IO uint32_t WCFGR; /!< DSI Wrapper Configuration Register, Address offset: 0x400 /
stm32f479xx.h:475	__IO uint32_t WCR; /!< DSI Wrapper Control Register, Address offset: 0x404 /
stm32f479xx.h:476	__IO uint32_t WIER; /!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 /
stm32f479xx.h:477	__IO uint32_t WISR; /!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C /
stm32f479xx.h:478	__IO uint32_t WIFCR; /!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 /
stm32f479xx.h:480	__IO uint32_t WPCR[5]; /!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B /
stm32f479xx.h:482	__IO uint32_t WRPCR; /!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 /
stm32f479xx.h:491	__IO uint32_t MACCR;
stm32f479xx.h:492	__IO uint32_t MACFFR;
stm32f479xx.h:493	__IO uint32_t MACHTHR;
stm32f479xx.h:494	__IO uint32_t MACHTLR;
stm32f479xx.h:495	__IO uint32_t MACMIIAR;
stm32f479xx.h:496	__IO uint32_t MACMIIDR;
stm32f479xx.h:497	__IO uint32_t MACFCR;
stm32f479xx.h:498	__IO uint32_t MACVLANTR; /* 8 */
stm32f479xx.h:500	__IO uint32_t MACRWUFFR; /* 11 */
stm32f479xx.h:501	__IO uint32_t MACPMTCSR;
stm32f479xx.h:503	__IO uint32_t MACDBGR;
stm32f479xx.h:504	__IO uint32_t MACSR; /* 15 */
stm32f479xx.h:505	__IO uint32_t MACIMR;
stm32f479xx.h:506	__IO uint32_t MACA0HR;
stm32f479xx.h:507	__IO uint32_t MACA0LR;
stm32f479xx.h:508	__IO uint32_t MACA1HR;
stm32f479xx.h:509	__IO uint32_t MACA1LR;
stm32f479xx.h:510	__IO uint32_t MACA2HR;
stm32f479xx.h:511	__IO uint32_t MACA2LR;
stm32f479xx.h:512	__IO uint32_t MACA3HR;
stm32f479xx.h:513	__IO uint32_t MACA3LR; /* 24 */
stm32f479xx.h:515	__IO uint32_t MMCCR; /* 65 */
stm32f479xx.h:516	__IO uint32_t MMCRIR;
stm32f479xx.h:517	__IO uint32_t MMCTIR;
stm32f479xx.h:518	__IO uint32_t MMCRIMR;
stm32f479xx.h:519	__IO uint32_t MMCTIMR; /* 69 */
stm32f479xx.h:521	__IO uint32_t MMCTGFSCCR; /* 84 */
stm32f479xx.h:522	__IO uint32_t MMCTGFMSCCR;
stm32f479xx.h:524	__IO uint32_t MMCTGFCR;
stm32f479xx.h:526	__IO uint32_t MMCRFCECR;
stm32f479xx.h:527	__IO uint32_t MMCRFAECR;
stm32f479xx.h:529	__IO uint32_t MMCRGUFCR;
stm32f479xx.h:531	__IO uint32_t PTPTSCR;
stm32f479xx.h:532	__IO uint32_t PTPSSIR;
stm32f479xx.h:533	__IO uint32_t PTPTSHR;
stm32f479xx.h:534	__IO uint32_t PTPTSLR;
stm32f479xx.h:535	__IO uint32_t PTPTSHUR;
stm32f479xx.h:536	__IO uint32_t PTPTSLUR;
stm32f479xx.h:537	__IO uint32_t PTPTSAR;
stm32f479xx.h:538	__IO uint32_t PTPTTHR;
stm32f479xx.h:539	__IO uint32_t PTPTTLR;
stm32f479xx.h:540	__IO uint32_t RESERVED8;
stm32f479xx.h:541	__IO uint32_t PTPTSSR;
stm32f479xx.h:543	__IO uint32_t DMABMR;
stm32f479xx.h:544	__IO uint32_t DMATPDR;
stm32f479xx.h:545	__IO uint32_t DMARPDR;
stm32f479xx.h:546	__IO uint32_t DMARDLAR;
stm32f479xx.h:547	__IO uint32_t DMATDLAR;
stm32f479xx.h:548	__IO uint32_t DMASR;
stm32f479xx.h:549	__IO uint32_t DMAOMR;
stm32f479xx.h:550	__IO uint32_t DMAIER;
stm32f479xx.h:551	__IO uint32_t DMAMFBOCR;
stm32f479xx.h:552	__IO uint32_t DMARSWTR;
stm32f479xx.h:554	__IO uint32_t DMACHTDR;
stm32f479xx.h:555	__IO uint32_t DMACHRDR;
stm32f479xx.h:556	__IO uint32_t DMACHTBAR;
stm32f479xx.h:557	__IO uint32_t DMACHRBAR;
stm32f479xx.h:566	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
stm32f479xx.h:567	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
stm32f479xx.h:568	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
stm32f479xx.h:569	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
stm32f479xx.h:570	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
stm32f479xx.h:571	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
stm32f479xx.h:580	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
stm32f479xx.h:581	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
stm32f479xx.h:582	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
stm32f479xx.h:583	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
stm32f479xx.h:584	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
stm32f479xx.h:585	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
stm32f479xx.h:586	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
stm32f479xx.h:595	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
stm32f479xx.h:604	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
stm32f479xx.h:613	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
stm32f479xx.h:614	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
stm32f479xx.h:615	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
stm32f479xx.h:616	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
stm32f479xx.h:618	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
stm32f479xx.h:627	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
stm32f479xx.h:628	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
stm32f479xx.h:629	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
stm32f479xx.h:630	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
stm32f479xx.h:631	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
stm32f479xx.h:640	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
stm32f479xx.h:641	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
stm32f479xx.h:642	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
stm32f479xx.h:643	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
stm32f479xx.h:644	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
stm32f479xx.h:645	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
stm32f479xx.h:646	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
stm32f479xx.h:647	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
stm32f479xx.h:648	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
stm32f479xx.h:657	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
stm32f479xx.h:658	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
stm32f479xx.h:659	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
stm32f479xx.h:661	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
stm32f479xx.h:670	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
stm32f479xx.h:671	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
stm32f479xx.h:672	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
stm32f479xx.h:673	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
stm32f479xx.h:674	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
stm32f479xx.h:675	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
stm32f479xx.h:676	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
stm32f479xx.h:677	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
stm32f479xx.h:678	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
stm32f479xx.h:679	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
stm32f479xx.h:688	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
stm32f479xx.h:689	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
stm32f479xx.h:690	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
stm32f479xx.h:691	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
stm32f479xx.h:701	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
stm32f479xx.h:702	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
stm32f479xx.h:703	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
stm32f479xx.h:704	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
stm32f479xx.h:705	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
stm32f479xx.h:707	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
stm32f479xx.h:709	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
stm32f479xx.h:711	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
stm32f479xx.h:712	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
stm32f479xx.h:713	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
stm32f479xx.h:714	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
stm32f479xx.h:715	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
stm32f479xx.h:716	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
stm32f479xx.h:725	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
stm32f479xx.h:726	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
stm32f479xx.h:727	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
stm32f479xx.h:728	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
stm32f479xx.h:729	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
stm32f479xx.h:730	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
stm32f479xx.h:731	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
stm32f479xx.h:732	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
stm32f479xx.h:734	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
stm32f479xx.h:735	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
stm32f479xx.h:736	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
stm32f479xx.h:738	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144/
stm32f479xx.h:747	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
stm32f479xx.h:748	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
stm32f479xx.h:757	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
stm32f479xx.h:758	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
stm32f479xx.h:759	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
stm32f479xx.h:760	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
stm32f479xx.h:761	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
stm32f479xx.h:762	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
stm32f479xx.h:763	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
stm32f479xx.h:765	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
stm32f479xx.h:766	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
stm32f479xx.h:768	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
stm32f479xx.h:769	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
stm32f479xx.h:770	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
stm32f479xx.h:772	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
stm32f479xx.h:773	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
stm32f479xx.h:775	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
stm32f479xx.h:776	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
stm32f479xx.h:777	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
stm32f479xx.h:779	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
stm32f479xx.h:780	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
stm32f479xx.h:782	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
stm32f479xx.h:783	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
stm32f479xx.h:785	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
stm32f479xx.h:786	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
stm32f479xx.h:787	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
stm32f479xx.h:788	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
stm32f479xx.h:797	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
stm32f479xx.h:798	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
stm32f479xx.h:799	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
stm32f479xx.h:800	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
stm32f479xx.h:801	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
stm32f479xx.h:802	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
stm32f479xx.h:803	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
stm32f479xx.h:804	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
stm32f479xx.h:805	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
stm32f479xx.h:806	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
stm32f479xx.h:807	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
stm32f479xx.h:808	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
stm32f479xx.h:809	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
stm32f479xx.h:810	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
stm32f479xx.h:811	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
stm32f479xx.h:812	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
stm32f479xx.h:813	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
stm32f479xx.h:814	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
stm32f479xx.h:815	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
stm32f479xx.h:817	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
stm32f479xx.h:818	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
stm32f479xx.h:819	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
stm32f479xx.h:820	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
stm32f479xx.h:821	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
stm32f479xx.h:822	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
stm32f479xx.h:823	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
stm32f479xx.h:824	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
stm32f479xx.h:825	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
stm32f479xx.h:826	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
stm32f479xx.h:827	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
stm32f479xx.h:828	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
stm32f479xx.h:829	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
stm32f479xx.h:830	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
stm32f479xx.h:831	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
stm32f479xx.h:832	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
stm32f479xx.h:833	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
stm32f479xx.h:834	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
stm32f479xx.h:835	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
stm32f479xx.h:836	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
stm32f479xx.h:845	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
stm32f479xx.h:850	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
stm32f479xx.h:851	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
stm32f479xx.h:852	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
stm32f479xx.h:853	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
stm32f479xx.h:854	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
stm32f479xx.h:855	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
stm32f479xx.h:856	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
stm32f479xx.h:857	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
stm32f479xx.h:866	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
stm32f479xx.h:867	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
stm32f479xx.h:868	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
stm32f479xx.h:869	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
stm32f479xx.h:870	__IO const uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
stm32f479xx.h:871	__IO const uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
stm32f479xx.h:872	__IO const uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
stm32f479xx.h:873	__IO const uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
stm32f479xx.h:874	__IO const uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
stm32f479xx.h:875	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
stm32f479xx.h:876	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
stm32f479xx.h:877	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
stm32f479xx.h:878	__IO const uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
stm32f479xx.h:879	__IO const uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
stm32f479xx.h:880	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
stm32f479xx.h:881	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
stm32f479xx.h:883	__IO const uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
stm32f479xx.h:885	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
stm32f479xx.h:894	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
stm32f479xx.h:895	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
stm32f479xx.h:896	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
stm32f479xx.h:897	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
stm32f479xx.h:898	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
stm32f479xx.h:899	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
stm32f479xx.h:900	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
stm32f479xx.h:901	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
stm32f479xx.h:902	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
stm32f479xx.h:911	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
stm32f479xx.h:912	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
stm32f479xx.h:913	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
stm32f479xx.h:914	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
stm32f479xx.h:915	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
stm32f479xx.h:916	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
stm32f479xx.h:917	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
stm32f479xx.h:918	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
stm32f479xx.h:919	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
stm32f479xx.h:920	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
stm32f479xx.h:921	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
stm32f479xx.h:922	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
stm32f479xx.h:923	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
stm32f479xx.h:932	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
stm32f479xx.h:933	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
stm32f479xx.h:934	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
stm32f479xx.h:935	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
stm32f479xx.h:936	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
stm32f479xx.h:937	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
stm32f479xx.h:938	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
stm32f479xx.h:939	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
stm32f479xx.h:940	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
stm32f479xx.h:941	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
stm32f479xx.h:942	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
stm32f479xx.h:943	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
stm32f479xx.h:944	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
stm32f479xx.h:945	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
stm32f479xx.h:946	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
stm32f479xx.h:947	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
stm32f479xx.h:948	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
stm32f479xx.h:949	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
stm32f479xx.h:950	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
stm32f479xx.h:951	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
stm32f479xx.h:952	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
stm32f479xx.h:961	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
stm32f479xx.h:962	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
stm32f479xx.h:963	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
stm32f479xx.h:964	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
stm32f479xx.h:965	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
stm32f479xx.h:966	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
stm32f479xx.h:967	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
stm32f479xx.h:976	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
stm32f479xx.h:977	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
stm32f479xx.h:978	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
stm32f479xx.h:987	__IO uint32_t CR; /!< CRYP control register, Address offset: 0x00 /
stm32f479xx.h:988	__IO uint32_t SR; /!< CRYP status register, Address offset: 0x04 /
stm32f479xx.h:989	__IO uint32_t DIN; /!< CRYP data input register, Address offset: 0x08 /
stm32f479xx.h:990	__IO uint32_t DOUT; /!< CRYP data output register, Address offset: 0x0C /
stm32f479xx.h:991	__IO uint32_t DMACR; /!< CRYP DMA control register, Address offset: 0x10 /
stm32f479xx.h:992	__IO uint32_t IMSCR; /!< CRYP interrupt mask set/clear register, Address offset: 0x14 /
stm32f479xx.h:993	__IO uint32_t RISR; /!< CRYP raw interrupt status register, Address offset: 0x18 /
stm32f479xx.h:994	__IO uint32_t MISR; /!< CRYP masked interrupt status register, Address offset: 0x1C /
stm32f479xx.h:995	__IO uint32_t K0LR; /!< CRYP key left register 0, Address offset: 0x20 /
stm32f479xx.h:996	__IO uint32_t K0RR; /!< CRYP key right register 0, Address offset: 0x24 /
stm32f479xx.h:997	__IO uint32_t K1LR; /!< CRYP key left register 1, Address offset: 0x28 /
stm32f479xx.h:998	__IO uint32_t K1RR; /!< CRYP key right register 1, Address offset: 0x2C /
stm32f479xx.h:999	__IO uint32_t K2LR; /!< CRYP key left register 2, Address offset: 0x30 /
stm32f479xx.h:1000	__IO uint32_t K2RR; /!< CRYP key right register 2, Address offset: 0x34 /
stm32f479xx.h:1001	__IO uint32_t K3LR; /!< CRYP key left register 3, Address offset: 0x38 /
stm32f479xx.h:1002	__IO uint32_t K3RR; /!< CRYP key right register 3, Address offset: 0x3C /
stm32f479xx.h:1003	__IO uint32_t IV0LR; /!< CRYP initialization vector left-word register 0, Address offset: 0x40 /
stm32f479xx.h:1004	__IO uint32_t IV0RR; /!< CRYP initialization vector right-word register 0, Address offset: 0x44 /
stm32f479xx.h:1005	__IO uint32_t IV1LR; /!< CRYP initialization vector left-word register 1, Address offset: 0x48 /
stm32f479xx.h:1006	__IO uint32_t IV1RR; /!< CRYP initialization vector right-word register 1, Address offset: 0x4C /
stm32f479xx.h:1007	__IO uint32_t CSGCMCCM0R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 /
stm32f479xx.h:1008	__IO uint32_t CSGCMCCM1R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 /
stm32f479xx.h:1009	__IO uint32_t CSGCMCCM2R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 /
stm32f479xx.h:1010	__IO uint32_t CSGCMCCM3R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C /
stm32f479xx.h:1011	__IO uint32_t CSGCMCCM4R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 /
stm32f479xx.h:1012	__IO uint32_t CSGCMCCM5R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 /
stm32f479xx.h:1013	__IO uint32_t CSGCMCCM6R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 /
stm32f479xx.h:1014	__IO uint32_t CSGCMCCM7R; /!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C /
stm32f479xx.h:1015	__IO uint32_t CSGCM0R; /!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 /
stm32f479xx.h:1016	__IO uint32_t CSGCM1R; /!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 /
stm32f479xx.h:1017	__IO uint32_t CSGCM2R; /!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 /
stm32f479xx.h:1018	__IO uint32_t CSGCM3R; /!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C /
stm32f479xx.h:1019	__IO uint32_t CSGCM4R; /!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 /
stm32f479xx.h:1020	__IO uint32_t CSGCM5R; /!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 /
stm32f479xx.h:1021	__IO uint32_t CSGCM6R; /!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 /
stm32f479xx.h:1022	__IO uint32_t CSGCM7R; /!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C /
stm32f479xx.h:1031	__IO uint32_t CR; /!< HASH control register, Address offset: 0x00 /
stm32f479xx.h:1032	__IO uint32_t DIN; /!< HASH data input register, Address offset: 0x04 /
stm32f479xx.h:1033	__IO uint32_t STR; /!< HASH start register, Address offset: 0x08 /
stm32f479xx.h:1034	__IO uint32_t HR[5]; /!< HASH digest registers, Address offset: 0x0C-0x1C /
stm32f479xx.h:1035	__IO uint32_t IMR; /!< HASH interrupt enable register, Address offset: 0x20 /
stm32f479xx.h:1036	__IO uint32_t SR; /!< HASH status register, Address offset: 0x24 /
stm32f479xx.h:1038	__IO uint32_t CSR[54]; /!< HASH context swap registers, Address offset: 0x0F8-0x1CC /
stm32f479xx.h:1047	__IO uint32_t HR[8]; /!< HASH digest registers, Address offset: 0x310-0x32C /
stm32f479xx.h:1056	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
stm32f479xx.h:1057	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
stm32f479xx.h:1058	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
stm32f479xx.h:1066	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
stm32f479xx.h:1067	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
stm32f479xx.h:1068	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
stm32f479xx.h:1069	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
stm32f479xx.h:1070	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
stm32f479xx.h:1071	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
stm32f479xx.h:1072	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
stm32f479xx.h:1073	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
stm32f479xx.h:1074	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
stm32f479xx.h:1075	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
stm32f479xx.h:1076	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
stm32f479xx.h:1077	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
stm32f479xx.h:1079	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
stm32f479xx.h:1080	__IO uint32_t CID; /!< User ID Register 03Ch /
stm32f479xx.h:1082	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
stm32f479xx.h:1084	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
stm32f479xx.h:1086	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
stm32f479xx.h:1088	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
stm32f479xx.h:1089	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
stm32f479xx.h:1097	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
stm32f479xx.h:1098	__IO uint32_t DCTL; /!< dev Control Register 804h /
stm32f479xx.h:1099	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
stm32f479xx.h:1101	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
stm32f479xx.h:1102	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
stm32f479xx.h:1103	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
stm32f479xx.h:1104	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
stm32f479xx.h:1107	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
stm32f479xx.h:1108	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
stm32f479xx.h:1109	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
stm32f479xx.h:1110	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
stm32f479xx.h:1111	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
stm32f479xx.h:1112	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
stm32f479xx.h:1114	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
stm32f479xx.h:1116	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
stm32f479xx.h:1124	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
stm32f479xx.h:1126	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
stm32f479xx.h:1128	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
stm32f479xx.h:1129	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
stm32f479xx.h:1130	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
stm32f479xx.h:1139	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
stm32f479xx.h:1141	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
stm32f479xx.h:1143	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
stm32f479xx.h:1144	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
stm32f479xx.h:1153	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
stm32f479xx.h:1154	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
stm32f479xx.h:1155	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
stm32f479xx.h:1157	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
stm32f479xx.h:1158	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
stm32f479xx.h:1159	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
stm32f479xx.h:1167	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
stm32f479xx.h:1168	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
stm32f479xx.h:1169	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
stm32f479xx.h:1170	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
stm32f479xx.h:1171	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
stm32f479xx.h:1172	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
stm32f4xx.h:233	val = __LDREXW((__IO uint32_t *)&(REG)) \| (BIT); \
stm32f4xx.h:234	} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
stm32f4xx.h:242	val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
stm32f4xx.h:243	} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
stm32f4xx.h:251	val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) \| (SETMASK); \
stm32f4xx.h:252	} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \