I’ve created a custom Visual Studio VisualGDB project that can JTAG single-step apps on a soft FPGA RISC-V CPU, specifically Luke Wren’s Hazard3 (the same CPU used on the Raspberry Pi RP2350). Project and code files are here in the ulx3s-dev branch of my fork:

https://github.com/gojimmypi/Hazard3/tree/ulx3s-dev/example_soc/synth/hazard3-fw

Only the Debug settings for VisualGDB project have been configured.

Assumes the repo was cloned from the C:\workspace\ directory, which will be /mnt/c/workspace/Hazard3 in WSL.

Uses all open source tools in WSL: yosys, nextpnr, verilator, etc. in WSL

Also assumes RISC-V toolchain installed in WSL for “Debug Settings – Debugger Path”:

/opt/riscv/bin/riscv32-unknown-elf-gdb

The exercise is specifically for HDMI Doom on the ULX3S and ULX4M, both with the Lattice ECP5 FPGA.

See “Additional GDB Commands” for the shared hazard3-start from thehazard3-debug.gdb file.

To start debugging, do NOT use “Debug – Start Debugging” with F5 (it won’t work).

Instead use “Debug – Start Debugging with GDB”. Your OpenOCD should already be running:

C:\workspace\hazard3\example_soc> path_to_your\openocd -d2 -f ulx3s-openocd.cfg

The ULX3S can act as its own JTAG when using libusbK drivers, the ULX4M uses the Tigard JTAG.

The “File Explorer” extension from Mads Kristensen will be helpful:

https://marketplace.visualstudio.com/items?itemName=MadsKristensen.WorkflowBrowser

as well as my Verilog Language Extension:

https://marketplace.visualstudio.com/items?itemName=gojimmypi.gojimmypi-verilog-language-extension

Readme files contain more details; feel free to reach out here or GitHub issues with questions.

Enjoy!