Problem: ESP32 Wroom with OpenOCD

[ericl]

Hello,

 

I’m using VisualGBD with an ESP32 Wroom and an Olimex ARM-USB-OCD-H.

So far it was working fine, I was able to flash and debug, but since yesterday I got an error while trying to flash.

The Ouput is below (seems CPU1 is not halted). Any idea?

 

 

Open On-Chip Debugger 0.9.0 (2017-05-09)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport “jtag”. To override use ‘transport select <transport>’.
adapter speed: 3000 kHz
Info : clock speed 3000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).
Info : esp32.cpu0: Core was reset (pwrstat=0x5F, after clear 0x0F).
Info : accepting ‘gdb’ connection on tcp/3333
Interrupt suppression during single-stepping is now enabled
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

esp32.cpu0: target state: halted
Target did not halt within 5000 msec

Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

esp32.cpu0: target state: halted
Target did not halt within 5000 msec

Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

esp32.cpu0: target state: halted
Open On-Chip Debugger 0.9.0 (2017-05-09)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport “jtag”. To override use ‘transport select <transport>’.
adapter speed: 3000 kHz
Info : clock speed 3000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).
Info : esp32.cpu0: Core was reset (pwrstat=0x5F, after clear 0x0F).
Info : accepting ‘gdb’ connection on tcp/3333
Interrupt suppression during single-stepping is now enabled
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

esp32.cpu0: target state: halted
Target did not halt within 5000 msec

Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

esp32.cpu0: target state: halted
Target did not halt within 5000 msec

Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

esp32.cpu0: target state: halted
Target did not halt within 5000 msec

Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : dropped ‘gdb’ connection

[vard]

Not sure if you’ve read this, some good information here: LIMITATIONS OF THE ESP32 DEBUGGING

[ericl]

Thanks for the info. I tried doing the procedure when the flash is not programmed. But at step 2 I cannot get the memory programmed. When it is said to do “Start JTAG debugging”, I do “Start debugging with GDB” but I get the same error: Warn : esp32.cpu1: target not halted.

Am I missing something?

[support]

Hi,

Just to double-check, are you using the latest esp32-gcc5.2.0.exe toolchain? A recent update to the ESP-IDF was interfering with the FLASH programming and it was only fixed in the 5.2.0 toolchain.

[satau]

I’m having what appears to be the same problem. I have not succeeded in flashing the ESP32 at all. VisualGDB-5.2r9. I have manually installed the esp32-gcc5.2.0.exe toolchain and recompiled the project, this did not help. I’m using the TUMPA JTAG interface. Any suggestions?

Open On-Chip Debugger 0.9.0 (2017-05-09)
Licensed under GNU GPL v2
For bug reports, read http://openocd.org/doc/doxygen/bugs.html
none separate
Info : auto-selecting first available session transport "jtag". To override use 'transport select <tra
nsport>'.
adapter speed: 3000 kHz
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : clock speed 3000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0
x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0
x1)
Info : esp32.cpu0: Target halted, pc=0x40090DF8
Error: The 'mww' command must be used after 'init'.
in procedure 'init' 
in procedure 'ocd_bouncer' 
in procedure 'flash' 
in procedure 'ocd_bouncer'

Info : accepting 'gdb' connection on tcp/3333
Interrupt suppression during single-stepping is now enabled
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0
x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0
x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure 'reset' 
in procedure 'ocd_bouncer' 
in procedure 'ocd_process_reset' 
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 248
in procedure 'esp32.cpu0' called at file "embedded:startup.tcl", line 349
in procedure 'ocd_bouncer'

esp32.cpu0: target state: halted
Target did not halt within 5000 msec

[support]

Hi,

This could be caused by the ESP32 configuration, or by incompatibility with TUMPA (we do not officially support it and have not heard of anyone successfully using it). The easiest way to get it to work would be to get the same hardware as shown in our tutorials and ensure your wiring 100% matches the one shown there. Once you get it to work, it would be easier to switch the debug adapter (or the ESP32 board) and quickly pinpoint what exactly is causing the problem.

[ASH74]

I ran into a similar issue with one of my dev-c boards that had image configured to run FreeRTOS on the first core only.

This is the output from openocd when I try to download & debug my code where the previous image was configured to run on the first core only.

Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’

I have a parallel install of the esp-idf via MSYS2 where I was able to flash one of the examples to the board that did not have “Run FreeRTOS only on first core” set and then I was able to debug my code in VisualGDB.

It was this thread that got me past this issue https://www.esp32.com/viewtopic.php?t=1253. I’m not sure if this is the same issue for you but I can recreate the openocd output above by having an image that runs only on the first core and then try to debug my code in VisualGDB.

[satau]

Thanks for the reply. I have switched out the ESP32 DevKitC board for a brand new one – I’m seeing the same issue. Unfortunately I don’t have another JTAG interface, and it could be a costly exercise to purchase and try multiple interfaces until it (hopefully) works. Can you link me a list of supported models?

The original poster is using an Olimex interface and seeing a similar error –  ‘cpu1 not halted’. So although this doesn’t rule out a TIAO TUMPA specific issue, I’m hoping that someone who has seen this problem before can jump in and help out.

More detailed logs from the OpenOCD window are below:

mon reset halt
&"mon reset halt\n"
@"JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\n"
@"JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\n"
@"esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).\n"
@"esp32.cpu0: Target halted, pc=0x40000400\n"
@"esp32.cpu1: target not halted\n"
@"in procedure 'reset' \n"
@"in procedure 'ocd_bouncer' \n"
@"in procedure 'ocd_process_reset' \n"
@"in procedure 'ocd_process_reset_inner' called at file \"embedded:startup.tcl\", line 248\n"
@"in procedure 'esp32.cpu0' called at file \"embedded:startup.tcl\", line 349\n"
@"in procedure 'ocd_bouncer'\n"
@"\n"
@"esp32.cpu0: target state: halted\n"
^done
restore C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin binary 0x40090000 0 0xe14
&"restore C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin binary 0x40090000 0 0xe14\n"
~"Restoring binary file C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin into memory (0x40090000 to 0x40090e14)\n"
^done
mon esp108 run_alg 0x400902d0 0x40090df8 20000 a1=0x3ffd0404 a10=0 a11=4096 a12=0 a0 pc
&"mon esp108 run_alg 0x400902d0 0x40090df8 20000 a1=0x3ffd0404 a10=0 a11=4096 a12=0 a0 pc\n"
@"Target did not halt within 20000 msec\n"
@"\n"
@"esp32.cpu0: Target halted, pc=0x40090DF8\n"
@"esp32.cpu0: target state: halted\n"
^done
mon reset halt
&"mon reset halt\n"
@"JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\n"
@"JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\n"
@"esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).\n"
@"esp32.cpu0: Target halted, pc=0x40000400\n"
@"esp32.cpu1: target not halted\n"
@"in procedure 'reset' \n"
@"in procedure 'ocd_bouncer' \n"
@"in procedure 'ocd_process_reset' \n"
@"in procedure 'ocd_process_reset_inner' called at file \"embedded:startup.tcl\", line 248\n"
@"in procedure 'esp32.cpu0' called at file \"embedded:startup.tcl\", line 349\n"
@"in procedure 'ocd_bouncer'\n"
@"\n"
@"esp32.cpu0: target state: halted\n"
^done
restore C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin binary 0x40090000 0 0xe14
&"restore C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin binary 0x40090000 0 0xe14\n"
~"Restoring binary file C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin into memory (0x40090000 to 0x40090e14)\n"
^done
mon esp108 run_alg 0x400902d0 0x40090df8 20000 a1=0x3ffd0404 a10=0 a11=4096 a12=0 a0 pc
&"mon esp108 run_alg 0x400902d0 0x40090df8 20000 a1=0x3ffd0404 a10=0 a11=4096 a12=0 a0 pc\n"
@"Target did not halt within 20000 msec\n"
@"\n"
@"esp32.cpu0: Target halted, pc=0x40090DF8\n"
@"esp32.cpu0: target state: halted\n"
^done
mon reset halt
&"mon reset halt\n"
@"JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\n"
@"JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\n"
@"esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).\n"
@"esp32.cpu0: Target halted, pc=0x40000400\n"
@"esp32.cpu1: target not halted\n"
@"in procedure 'reset' \n"
@"in procedure 'ocd_bouncer' \n"
@"in procedure 'ocd_process_reset' \n"
@"in procedure 'ocd_process_reset_inner' called at file \"embedded:startup.tcl\", line 248\n"
@"in procedure 'esp32.cpu0' called at file \"embedded:startup.tcl\", line 349\n"
@"in procedure 'ocd_bouncer'\n"
@"\n"
@"esp32.cpu0: target state: halted\n"
^done
restore C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin binary 0x40090000 0 0xe14
&"restore C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin binary 0x40090000 0 0xe14\n"
~"Restoring binary file C:/SysGCC/esp32/esp32-bsp/sysprogs/flashprog/ESP32FlashProg.bin into memory (0x40090000 to 0x40090e14)\n"
^done
mon esp108 run_alg 0x400902d0 0x40090df8 20000 a1=0x3ffd0404 a10=0 a11=4096 a12=0 a0 pc
&"mon esp108 run_alg 0x400902d0 0x40090df8 20000 a1=0x3ffd0404 a10=0 a11=4096 a12=0 a0 pc\n"
@"Target did not halt within 20000 msec\n"
@"\n"
@"esp32.cpu0: Target halted, pc=0x40090DF8\n"
@"esp32.cpu0: target state: halted\n"
^done

• This reply was modified 7 years, 5 months ago by satau.

[satau]

ASH74: I was able to flash one of the examples to the board that did not have “Run FreeRTOS only on first core” set and then I was able to debug my code in VisualGDB.

Awesome. I’ll give that a try and see if it helps. Thanks for sharing!

[satau]

I can confirm that everything is working fine after flashing a program that enables dual core mode. Thankyou ASH74!

Mods – It may be worth noting the following:

1. If ESP32 is running in single core mode, cpu1 will fail to halt when attempting to program/debug via JTAG using VisualGDB.
2. The TIAO/TUMPA JTAG interface appears to be working fine using the VisualGDB bundled drivers – flashes ok and is hitting breakpoints when running code.

[support]

Hi,

Thanks for confirming this, we will note down that TUMPA is compatible with ESP32.

Regarding single-core mode, you can actually try editing the <SysGCC>\esp32\esp32-bsp\OpenOCD\share\openocd\scripts\target\esp32.cfg file (uncomment the set ESP32_ONLYCPU 1 line), although we have not fully tested this mode and it may result in strange bugs.

[ASH74]

Satau,
this is good news that it fixed your issue, I spent a few hours trying to figure it out, one board was ok, the second one did not work.

Cheers!

 

 

[Author]

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