VisualHDL Design Visualizer

[Anonymous]

Hi!

I tried VisualHDL today, very quickly and find the idea very interesting, as it adresses a large number of weaknesses of “traditional” hdls. I started (of course) with the provided examples. I encounter an error when trying to Visualize the design (due to unresolved templates, I assume).

“No root entity was found in the project. Define one using the generate_vhdl statement.”

How do I do that?

Cheers,
Dan

[support]

OK, which example are you trying and what entity are you trying to visualize? Are you using “Project->Visualize” command, or “Visualize entity” command from the context menu? If you modified the example, ensure that one of your source files contains something like that:

//The following line will take effect when building simulation model
simulate_entity(SimulatedClockProvider<20ns, LEDBlinkDemo>);

//When using VisualHDL with Xilinx tools, VisualHDL will build the
//FPGA bitstream file automatically based on the following line:
synthesize_hardware<"xc3s700an-fgg484-4"> LEDBlinkDemo(
clk=”E12″,
LEDs=”W21,Y22,V20,V19,U19,U20,T19,R20″
//The post_route_sim statement is optional and is only used for generating
//post-route simulation models.
) post_route_sim(SimulatedClockProvider<20ns, LEDBlinkDemo>);

This essentially means that if you’re building a simulator configuration (selected on top of the project file list), the root entity will be the one specified by simulate_entity. Similar for FPGA builds.

Don’t believe the message about “generate_vhdl”, it was not updated since the build when generate_vhdl split into simulate_entity for simulator builds and synthesize_hardware for FPGA builds. Will fix the msg in future versions.

[Anonymous]

Thanks for the quick reply.

I had used the PMinMax example. The problem was that I had switched in Project Explorer from Behavioral Simulation to FPGA BitStream. Then the error message appears.

Another quick question: is it possible to mix existing VHDL entities and packages with THDL++? E.g., can I add a “use” statement in THDL++ to call functions from an existing VHDL package? Or, can I instantiate VHDL components (say, from the Xilinx Core Generator) within a THDL++ project?

Cheers,
Dan

[support]

You use the following syntax:

import_entity rom1(“rom1.vhd”);

From now on you can use the “rom1” entity as if it was implemented in THDL++.
Note that this feature is experimental and will most likely not work with complex entities (e.g. having generic-dependent ports). However, it works for Xilinx generated cores.

[Anonymous]

Thanks again. I will try it out.

Cheers,
Dan

[Author]

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