STM32F722RE Not Connecting

[eddieA]

Not sure why, but I cant connect to my target with VisualStudio and VisualGDB , STM Programmer works, and ST Link Utility Work, and also Keil are flashing fine. I am configuring everything as I normally do, I have attatched images to show my debugger settings and also the messages I get when pressing the “Test” button

 

this is the stub:

 

C:\Users\amaya\AppData\Local\VisualGDB\EmbeddedDebugPackages\com.sysprogs.arm.openocd\bin\openocd.exe -c “gdb_port 54933” -c “telnet_port 54932” -c “debug_level 3” -f interface/stlink-v2.cfg -f C:/Users/amaya/AppData/Local/Temp/tmp1448.tmp -c init -c “reset init” -c “echo VisualGDB_OpenOCD_Ready”
Open On-Chip Debugger 0.10.0 (2020-12-28) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 16 2 options.c:63 configuration_output_handler(): debug_level: 3
User : 17 2 options.c:63 configuration_output_handler():
Debug: 18 2 configuration.c:97 find_file(): found interface/stlink-v2.cfg
Debug: 19 3 command.c:146 script_debug(): command – echo WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg
User : 21 3 command.c:769 jim_echo(): WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg
Debug: 22 3 configuration.c:97 find_file(): found interface/stlink.cfg
Debug: 23 3 command.c:146 script_debug(): command – adapter driver hla
Debug: 25 3 command.c:146 script_debug(): command – hla_layout stlink
Debug: 27 4 hla_interface.c:242 hl_interface_handle_layout_command(): hl_interface_handle_layout_command
Debug: 28 4 command.c:146 script_debug(): command – hla_device_desc ST-LINK
Debug: 30 4 hla_interface.c:216 hl_interface_handle_device_desc_command(): hl_interface_handle_device_desc_command
Debug: 31 4 command.c:146 script_debug(): command – hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
Debug: 33 4 configuration.c:97 find_file(): found C:/Users/amaya/AppData/Local/Temp/tmp1448.tmp
Debug: 34 5 configuration.c:97 find_file(): found target/swj-dp.tcl
Debug: 35 5 command.c:146 script_debug(): command – transport select
Info : 36 5 transport.c:275 jim_transport_select(): auto-selecting first available session transport “hla_swd”. To override use ‘transport select <transport>’.
Debug: 37 5 hla_transport.c:205 hl_swd_transport_select(): hl_swd_transport_select
Debug: 38 5 configuration.c:97 find_file(): found mem_helper.tcl
Debug: 39 6 command.c:146 script_debug(): command – add_usage_text mrw address
Debug: 41 6 command.c:1115 help_add_command(): added ‘mrw’ help text
Debug: 42 6 command.c:146 script_debug(): command – add_help_text mrw Returns value of word in memory.
Debug: 44 6 command.c:1128 help_add_command(): added ‘mrw’ help text
Debug: 45 6 command.c:146 script_debug(): command – add_usage_text mrh address
Debug: 47 6 command.c:1115 help_add_command(): added ‘mrh’ help text
Debug: 48 6 command.c:146 script_debug(): command – add_help_text mrh Returns value of halfword in memory.
Debug: 50 6 command.c:1128 help_add_command(): added ‘mrh’ help text
Debug: 51 7 command.c:146 script_debug(): command – add_usage_text mrb address
Debug: 53 7 command.c:1115 help_add_command(): added ‘mrb’ help text
Debug: 54 7 command.c:146 script_debug(): command – add_help_text mrb Returns value of byte in memory.
Debug: 56 7 command.c:1128 help_add_command(): added ‘mrb’ help text
Debug: 57 7 command.c:146 script_debug(): command – add_usage_text mmw address setbits clearbits
Debug: 59 7 command.c:1115 help_add_command(): added ‘mmw’ help text
Debug: 60 7 command.c:146 script_debug(): command – add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 62 7 command.c:1128 help_add_command(): added ‘mmw’ help text
Debug: 63 8 command.c:146 script_debug(): command – transport select
Debug: 64 8 command.c:146 script_debug(): command – transport select
Debug: 65 8 command.c:146 script_debug(): command – transport select
Debug: 66 8 command.c:146 script_debug(): command – swd newdap stm32f7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x5ba02477
Debug: 67 8 hla_tcl.c:110 jim_hl_newtap_cmd(): Creating New Tap, Chip: stm32f7x, Tap: cpu, Dotted: stm32f7x.cpu, 8 params
Debug: 68 8 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irlen
Debug: 69 8 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -ircapture
Debug: 70 9 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irmask
Debug: 71 9 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -expected-id
Debug: 72 9 core.c:1484 jtag_tap_init(): Created Tap: stm32f7x.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0
Debug: 73 9 command.c:146 script_debug(): command – dap create stm32f7x.dap -chain-position stm32f7x.cpu
Debug: 74 9 command.c:146 script_debug(): command – transport select
Debug: 75 9 command.c:146 script_debug(): command – target create stm32f7x.cpu cortex_m -endian little -dap stm32f7x.dap
Info : 76 9 target.c:5746 target_create(): The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Debug: 77 10 hla_target.c:203 adapter_target_create(): adapter_target_create
Debug: 78 10 hla_target.c:173 adapter_init_arch_info(): adapter_init_arch_info
Debug: 79 10 command.c:375 register_command(): command ‘rtt’ is already registered in ‘<global>’ context
Debug: 80 10 command.c:146 script_debug(): command – stm32f7x.cpu configure -work-area-phys 0x20000000 -work-area-size 0x20000 -work-area-backup 0
Debug: 81 10 target.c:2151 target_free_all_working_areas_restore(): freeing all working areas
Debug: 82 10 target.c:2151 target_free_all_working_areas_restore(): freeing all working areas
Debug: 83 11 target.c:2151 target_free_all_working_areas_restore(): freeing all working areas
Debug: 84 11 command.c:146 script_debug(): command – flash bank stm32f7x.flash stm32f2x 0 0 0 0 stm32f7x.cpu
Debug: 86 11 tcl.c:1319 handle_flash_bank_command(): ‘stm32f2x’ driver usage field missing
Debug: 87 11 command.c:146 script_debug(): command – flash bank stm32f7x.otp stm32f2x 0x1ff0f000 0 0 0 stm32f7x.cpu
Debug: 89 11 command.c:375 register_command(): command ‘stm32f2x’ is already registered in ‘<global>’ context
Debug: 90 11 command.c:375 register_command(): command ‘lock’ is already registered in ‘stm32f2x’ context
Debug: 91 12 command.c:375 register_command(): command ‘unlock’ is already registered in ‘stm32f2x’ context
Debug: 92 12 command.c:375 register_command(): command ‘mass_erase’ is already registered in ‘stm32f2x’ context
Debug: 93 12 command.c:375 register_command(): command ‘options_read’ is already registered in ‘stm32f2x’ context
Debug: 94 12 command.c:375 register_command(): command ‘options_write’ is already registered in ‘stm32f2x’ context
Debug: 95 12 command.c:375 register_command(): command ‘optcr2_write’ is already registered in ‘stm32f2x’ context
Debug: 96 12 command.c:375 register_command(): command ‘otp’ is already registered in ‘stm32f2x’ context
Debug: 97 12 tcl.c:1319 handle_flash_bank_command(): ‘stm32f2x’ driver usage field missing
Debug: 98 13 command.c:146 script_debug(): command – flash bank stm32f7x.itcm-flash.alias virtual 0x00200000 0 0 0 stm32f7x.cpu stm32f7x.flash
Debug: 100 13 tcl.c:1319 handle_flash_bank_command(): ‘virtual’ driver usage field missing
Debug: 101 13 command.c:146 script_debug(): command – adapter speed 2000
Debug: 103 13 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 104 13 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 105 13 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 106 13 command.c:146 script_debug(): command – adapter srst delay 100
Debug: 108 13 command.c:146 script_debug(): command – transport select
Debug: 109 13 command.c:146 script_debug(): command – reset_config trst_and_srst srst_nogate connect_assert_srst
Debug: 111 13 command.c:146 script_debug(): command – transport select
Debug: 112 13 command.c:146 script_debug(): command – stm32f7x.cpu configure -event examine-end
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 113 14 command.c:146 script_debug(): command – stm32f7x.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0

Debug: 114 14 command.c:146 script_debug(): command – stm32f7x.cpu configure -event reset-init
# If the HSE was previously enabled and the external clock source
# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
# properly switched back to HSI. This situation persists even over a system
# reset, including a pin reset via SRST. However, activating the clock
# security system will detect the problem and clear HSERDY to 0, which in
# turn allows the PLL to switch back to HSI properly. Since we just came
# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
# have happened; in that case, activate the clock security system to clear
# HSERDY.
if {[mrw 0x40023800] & 0x00020000} {
mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
sleep 10 ;# Wait for CSS to fire, if it wants to
mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC
sleep 1 ;# Wait for CSSF to clear
}

# If the clock security system fired, it will pend an NMI. A pending NMI
# will cause a bad time for any subsequent executing code, such as a
# programming algorithm.
if {[mrw 0xE000ED04] & 0x80000000} {
# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI canΓÇÖt be
# cleared by any normal means (such as ICSR or NVIC). It can only be
# cleared by entering the NMI handler or by resetting the processor.
echo “[target current]: Clock security system generated NMI. Clearing.”

# Keep the old DEMCR value.
set old [mrw 0xE000EDFC]

# Enable vector catch on reset.
mww 0xE000EDFC 0x01000001

# Issue local reset via AIRCR.
mww 0xE000ED0C 0x05FA0001

# Restore old DEMCR value.
mww 0xE000EDFC $old
}

# Configure PLL to boost clock to HSI x 10 (160 MHz)
mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
sleep 10 ;# Wait for PLL to lock
mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL

# Boost SWD frequency
# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
# suffers from DAP WAITs
if {[using_jtag]} {
[[target current] cget -dap] memaccess 16
} {
adapter speed 8000
}

Debug: 115 16 command.c:146 script_debug(): command – stm32f7x.cpu configure -event reset-start
# Reduce speed since CPU speed will slow down to 16MHz with the reset
adapter speed 2000

Debug: 116 16 command.c:146 script_debug(): command – init
Debug: 118 16 command.c:146 script_debug(): command – target init
Debug: 120 16 command.c:146 script_debug(): command – target names
Debug: 121 16 command.c:146 script_debug(): command – stm32f7x.cpu cget -event gdb-flash-erase-start
Debug: 122 16 command.c:146 script_debug(): command – stm32f7x.cpu configure -event gdb-flash-erase-start reset init
Debug: 123 16 command.c:146 script_debug(): command – stm32f7x.cpu cget -event gdb-flash-write-end
Debug: 124 16 command.c:146 script_debug(): command – stm32f7x.cpu configure -event gdb-flash-write-end reset halt
Debug: 125 17 command.c:146 script_debug(): command – stm32f7x.cpu cget -event gdb-attach
Debug: 126 17 command.c:146 script_debug(): command – stm32f7x.cpu configure -event gdb-attach halt 1000
Debug: 127 17 target.c:1618 handle_target_init_command(): Initializing targets…
Debug: 128 17 hla_target.c:193 adapter_init_target(): adapter_init_target
Debug: 129 17 semihosting_common.c:97 semihosting_common_init():
Debug: 130 17 hla_interface.c:109 hl_interface_init(): hl_interface_init
Debug: 131 17 hla_layout.c:95 hl_layout_init(): hl_layout_init
Debug: 132 17 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 133 17 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 134 17 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 135 18 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 136 18 core.c:1565 adapter_init(): clock speed 2000 kHz
Debug: 137 18 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 138 18 command.c:146 script_debug(): command – transport init
Debug: 140 18 transport.c:229 handle_transport_init(): handle_transport_init
Debug: 141 18 hla_transport.c:156 hl_transport_init(): hl_transport_init
Debug: 142 18 hla_transport.c:173 hl_transport_init(): current transport hla_swd
Debug: 143 18 hla_interface.c:42 hl_interface_open(): hl_interface_open
Debug: 144 18 hla_layout.c:40 hl_layout_open(): hl_layout_open
Debug: 145 19 stlink_usb.c:2819 stlink_usb_open(): stlink_usb_open
Debug: 146 19 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x3744 serial:
Debug: 147 19 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x3748 serial:
Debug: 148 19 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x374b serial:
Debug: 149 19 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x374d serial:
Debug: 150 19 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x374e serial:
Debug: 151 19 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x374f serial:
Debug: 152 20 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x3752 serial:
Debug: 153 20 stlink_usb.c:2831 stlink_usb_open(): transport: 4 vid: 0x0483 pid: 0x3753 serial:
Info : 154 30 stlink_usb.c:1098 stlink_usb_version(): STLINK V2J32S7 (API v2) VID:PID 0483:3748
Debug: 155 30 stlink_usb.c:1323 stlink_usb_exit_mode(): MODE: 0x01
Info : 156 30 stlink_usb.c:1134 stlink_usb_check_voltage(): Target voltage: 3.201047
Debug: 157 30 stlink_usb.c:1391 stlink_usb_init_mode(): MODE: 0x01
Debug: 158 31 stlink_usb.c:2606 stlink_dump_speed_map(): Supported clock speeds are:
Debug: 159 31 stlink_usb.c:2609 stlink_dump_speed_map(): 4000 kHz
Debug: 160 31 stlink_usb.c:2609 stlink_dump_speed_map(): 1800 kHz
Debug: 161 31 stlink_usb.c:2609 stlink_dump_speed_map(): 1200 kHz
Debug: 162 31 stlink_usb.c:2609 stlink_dump_speed_map(): 950 kHz
Debug: 163 31 stlink_usb.c:2609 stlink_dump_speed_map(): 480 kHz
Debug: 164 31 stlink_usb.c:2609 stlink_dump_speed_map(): 240 kHz
Debug: 165 31 stlink_usb.c:2609 stlink_dump_speed_map(): 125 kHz
Debug: 166 31 stlink_usb.c:2609 stlink_dump_speed_map(): 100 kHz
Debug: 167 31 stlink_usb.c:2609 stlink_dump_speed_map(): 50 kHz
Debug: 168 31 stlink_usb.c:2609 stlink_dump_speed_map(): 25 kHz
Debug: 169 31 stlink_usb.c:2609 stlink_dump_speed_map(): 15 kHz
Debug: 170 31 stlink_usb.c:2609 stlink_dump_speed_map(): 5 kHz
Debug: 171 33 stlink_usb.c:1450 stlink_usb_init_mode(): MODE: 0x02
Debug: 172 33 stlink_usb.c:3238 stlink_usb_open_ap(): AP 0 enabled
Debug: 173 33 stlink_usb.c:2990 stlink_usb_open(): Using TAR autoincrement: 1024
Debug: 174 34 core.c:636 adapter_system_reset(): SRST line asserted
Debug: 175 34 hla_interface.c:67 hl_interface_init_target(): hl_interface_init_target
Debug: 176 34 stlink_usb.c:1683 stlink_usb_idcode(): IDCODE: 0x5BA02477
Debug: 177 34 command.c:146 script_debug(): command – dap init
Debug: 179 34 arm_dap.c:106 dap_init_all(): Initializing all DAPs …
Debug: 180 34 openocd.c:160 handle_init_command(): Examining targets…
Debug: 181 34 target.c:1804 target_call_event_callbacks(): target event 19 (examine-start) for core stm32f7x.cpu
Debug: 182 35 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1
Debug: 183 35 target.c:2566 target_read_u32(): address: 0xe000ed00, value: 0x411fc271
Debug: 184 35 cortex_m.c:2056 cortex_m_examine(): Cortex-M7 r1p1 processor detected
Debug: 185 35 cortex_m.c:2068 cortex_m_examine(): cpuid: 0x411fc271
Debug: 186 35 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000ef40 4 1
Debug: 187 36 target.c:2566 target_read_u32(): address: 0xe000ef40, value: 0x10110021
Debug: 188 36 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000ef44 4 1
Debug: 189 36 target.c:2566 target_read_u32(): address: 0xe000ef44, value: 0x11000011
Debug: 190 37 cortex_m.c:2088 cortex_m_examine(): Cortex-M7 floating point feature FPv5_SP found
Debug: 191 37 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000edf0 4 1
Debug: 192 37 target.c:2566 target_read_u32(): address: 0xe000edf0, value: 0x01010001
Debug: 193 37 target.c:2654 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 194 37 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1
Debug: 195 38 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1
Debug: 196 38 target.c:2566 target_read_u32(): address: 0xe0002000, value: 0x10000080
Debug: 197 38 target.c:2654 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 198 39 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1
Debug: 199 39 target.c:2654 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 200 39 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1
Debug: 201 40 target.c:2654 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 202 40 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1
Debug: 203 40 target.c:2654 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 204 40 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1
Debug: 205 41 target.c:2654 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 206 41 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1
Debug: 207 41 target.c:2654 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 208 42 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1
Debug: 209 42 target.c:2654 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 210 42 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1
Debug: 211 43 target.c:2654 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 212 43 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1
Debug: 213 43 cortex_m.c:2169 cortex_m_examine(): FPB fpcr 0x10000080, numcode 8, numlit 0
Debug: 214 43 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1
Debug: 215 44 target.c:2566 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 216 44 cortex_m.c:1886 cortex_m_dwt_setup(): DWT_CTRL: 0x40000000
Debug: 217 44 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0001fbc 4 1
Debug: 218 45 target.c:2566 target_read_u32(): address: 0xe0001fbc, value: 0x00000000
Debug: 219 45 cortex_m.c:1893 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0
Debug: 220 45 target.c:2654 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 221 45 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1
Debug: 222 46 target.c:2654 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 223 46 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1
Debug: 224 46 target.c:2654 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 225 46 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1
Debug: 226 47 target.c:2654 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 227 47 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1
Debug: 228 47 cortex_m.c:1940 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 229 47 cortex_m.c:2179 cortex_m_examine(): stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints
Debug: 230 48 target.c:1804 target_call_event_callbacks(): target event 21 (examine-end) for core stm32f7x.cpu
Debug: 231 48 target.c:4849 target_handle_event(): target(0): stm32f7x.cpu (hla_target) event: 21 (examine-end) action:
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 232 48 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 233 49 command.c:146 script_debug(): command – mww 0xE0042004 7
Debug: 235 49 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 236 50 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 237 50 command.c:146 script_debug(): command – mww 0xE0042008 6144
Debug: 239 50 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 240 51 command.c:146 script_debug(): command – flash init
Debug: 242 51 tcl.c:1385 handle_flash_init_command(): Initializing flash devices…
Debug: 243 51 command.c:146 script_debug(): command – nand init
Debug: 245 52 tcl.c:498 handle_nand_init_command(): Initializing NAND devices…
Debug: 246 52 command.c:146 script_debug(): command – pld init
Debug: 248 52 pld.c:206 handle_pld_init_command(): Initializing PLDs…
Info : 249 52 gdb_server.c:3523 gdb_target_start(): starting gdb server for stm32f7x.cpu on 54933
Info : 250 53 server.c:311 add_service(): Listening on port 54933 for gdb connections
Debug: 251 53 command.c:146 script_debug(): command – reset init
Debug: 253 53 target.c:1823 target_call_reset_callbacks(): target reset 3 (init)
Debug: 254 54 command.c:146 script_debug(): command – target names
Debug: 255 54 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event reset-start
Debug: 256 54 target.c:4849 target_handle_event(): target(0): stm32f7x.cpu (hla_target) event: 9 (reset-start) action:
# Reduce speed since CPU speed will slow down to 16MHz with the reset
adapter speed 2000

Debug: 257 54 command.c:146 script_debug(): command – adapter speed 2000
Debug: 259 54 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 260 54 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 261 54 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 262 55 stlink_usb.c:2549 stlink_match_speed_map(): Unable to match requested speed 2000 kHz, using 1800 kHz
Debug: 263 55 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 264 55 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 265 55 stlink_usb.c:2549 stlink_match_speed_map(): Unable to match requested speed 2000 kHz, using 1800 kHz
Debug: 266 55 command.c:146 script_debug(): command – transport select
Debug: 267 55 command.c:146 script_debug(): command – transport select
Debug: 268 55 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event examine-start
Debug: 269 55 command.c:146 script_debug(): command – stm32f7x.cpu arp_examine allow-defer
Debug: 270 55 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event examine-end
Debug: 271 56 target.c:4849 target_handle_event(): target(0): stm32f7x.cpu (hla_target) event: 21 (examine-end) action:
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 272 56 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 273 56 command.c:146 script_debug(): command – mww 0xE0042004 7
Debug: 275 57 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 276 57 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 277 58 command.c:146 script_debug(): command – mww 0xE0042008 6144
Debug: 279 58 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 280 58 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event reset-assert-pre
Debug: 281 58 command.c:146 script_debug(): command – transport select
Debug: 282 58 command.c:146 script_debug(): command – stm32f7x.cpu arp_reset assert 1
Debug: 283 59 target.c:2151 target_free_all_working_areas_restore(): freeing all working areas
Debug: 284 59 hla_target.c:344 hl_assert_reset(): hl_assert_reset
Debug: 285 60 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event reset-assert-post
Debug: 286 60 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event reset-deassert-pre
Debug: 287 61 command.c:146 script_debug(): command – transport select
Debug: 288 61 command.c:146 script_debug(): command – stm32f7x.cpu arp_reset deassert 1
Debug: 289 61 target.c:2151 target_free_all_working_areas_restore(): freeing all working areas
Debug: 290 61 hla_target.c:403 hl_deassert_reset(): hl_deassert_reset
Debug: 291 61 core.c:640 adapter_system_reset(): SRST line released
Debug: 292 220 command.c:146 script_debug(): command – stm32f7x.cpu invoke-event reset-deassert-post
Debug: 293 220 command.c:146 script_debug(): command – transport select
Debug: 294 220 command.c:146 script_debug(): command – stm32f7x.cpu was_examined
Debug: 295 220 command.c:146 script_debug(): command – stm32f7x.cpu arp_waitstate halted 1000
Debug: 296 220 target.c:3220 target_wait_state(): waiting for target halted…
Error: 298 1221 target.c:3228 target_wait_state(): timed out while waiting for target halted
Debug: 299 1221 command.c:146 script_debug(): command – stm32f7x.cpu curstate
Debug: 300 1221 command.c:628 run_command(): Command ‘reset’ failed with error code -4
User : 301 1221 command.c:694 command_run_line(): TARGET: stm32f7x.cpu – Not halted
Debug: 302 1221 target.c:2151 target_free_all_working_areas_restore(): freeing all working areas
Debug: 303 1221 hla_interface.c:117 hl_interface_quit(): hl_interface_quit
Debug: 304 1222 stlink_usb.c:1323 stlink_usb_exit_mode(): MODE: 0x02

• This topic was modified 3 years, 9 months ago by eddieA.

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[support]

Sorry, this looks like an issue in OpenOCD executable and not something specific to VisualGDB. Our best advice would be to try programming this device using the Eclipse-based STM32CubeIDE that also uses OpenOCD. If the STM32CubeIDE works, please try using the OpenOCD script from it with VisualGDB – you should get the same results since the underlying mechanism will be the same.

If OpenOCD doesn’t work there either, please consider using Segger J-Link. It comes with a very well-tested and fully supported replacement for OpenOCD and typically just works out-of-the-box.

[eddieA]

Turns out this was a capacitor issue. I missed a capacitor on the vCap of the F7 which is critical to the internal voltage regulator used for voltage scaling at really high system clock frequencies. So I also kept getting an “under voltage” error, anyways, I added the cap and visualGDB along with openOCD worked like a charm per usual. thanks for the reply though .

[Author]

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