[engineering-spirit]

so the buildin jtag is not supported?
Or is there a way to use it.

I cant vind any option to use it in the debug configuration.

[engineering-spirit]

C:\Users\pvisser\AppData\Local\VisualGDB\EmbeddedDebugPackages\com.sysprogs.esp32.core\bin\openocd.exe -c “gdb_port 64499” -c “telnet_port 64497” -f interface/esp_usb_jtag.cfg -c “adapter_khz 3000” -f target/esp32s3.cfg -c “echo VisualGDB_OpenOCD_Ready”
Open On-Chip Debugger 0.10.0 (2022-05-03)
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect ‘jtag’
Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Info : esp_usb_jtag: capabilities descriptor set to 0x2000
adapter speed: 40000 kHz

DEPRECATED! use ‘adapter speed’ not ‘adapter_khz’
adapter speed: 3000 kHz

Warn : Transport “jtag” was already selected
VisualGDB_OpenOCD_Ready
Info : Listening on port 6666 for tcl connections
Info : Listening on port 64497 for telnet connections
Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND
Error: esp_usb_jtag: could not find or open device!

Error: No JTAG interface configured yet. Issue ‘init’ command in startup scripts before communicating with targets.
Error: Failed to clear OCDDCR_ENABLEOCD!
Error: No JTAG interface configured yet. Issue ‘init’ command in startup scripts before communicating with targets.
Error: Failed to clear OCDDCR_ENABLEOCD!

[engineering-spirit]

i found my problem the 2nd stage bootloader was to big.

It was overridden by the  partition table.

[engineering-spirit]

when i try to do that i get a boot loop.

So i was hoping that there was a walktrough

 

<!–StartFragment –>
<div>ets Jun 8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:4
load:0x3fff0034,len:9512
load:0x40078000,len:20900
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:4
load:0x3fff0034,len:9512
load:0x40078000,len:20900
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 188777542, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:4
load:0x3fff0034,len:9512
load:0x40078000,len:20900
load:0xffffffff,len:-1</div>
<!–EndFragment –>

• This reply was modified 3 years, 9 months ago by engineering-spirit.

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