[david_home]

Thanks for quick turnaround.  It’s working great now.

Cheers

David

[david_home]

Hi Support, Good news!  I have managed to increase the setup time and hold time so I don’t see any clashes with the clock rising edge.  However, it is still only decoding the first frame.  Can you tell me why the other frames have not been decoded?

I’ve attached the data file.

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[david_home]

Fair enough.  It was worth a try :).  I keep trying to increase the setup time after clock stretching.

Cheers

David

[david_home]

Thank you for looking at this issue for me.  I noticed after the clock stretching the SDA and SCL toggling at the same time too.  I was hoping it was just the resolution of the graph, but by your reckoning they changed on the same sample point.  I measured 300ns between the SDA going low and the SDC going high.  I assume that time is too short to separate the two signal changes, so it would appear to A2G that the peripheral is violating the setup time.  With that accepted, is there anyway you can just take the ‘new’ value of SDA on the rising edge of SCL?

The slaves are actually  STM32F0’s so I’ll see if there is a way of extending the time between SDA going low and the SCL going high.  Unfortunately, the timing register looks quite complicated.

Thanks for the updated software.  I haven’t tried it yet, but I’ll let you know how it goes.

Cheers

David

[david_home]

I won’t let me upload the .dsf (for security reasons).  I’ll try zipping it first

 

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