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Satau,
this is good news that it fixed your issue, I spent a few hours trying to figure it out, one board was ok, the second one did not work.Cheers!
I ran into a similar issue with one of my dev-c boards that had image configured to run FreeRTOS on the first core only.
This is the output from openocd when I try to download & debug my code where the previous image was configured to run on the first core only.
Info : esp32.cpu0: Target halted, pc=0x40090DF8
esp32.cpu0: target state: halted
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
Warn : esp32.cpu1: target not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘esp32.cpu0’ called at file “embedded:startup.tcl”, line 349
in procedure ‘ocd_bouncer’I have a parallel install of the esp-idf via MSYS2 where I was able to flash one of the examples to the board that did not have “Run FreeRTOS only on first core” set and then I was able to debug my code in VisualGDB.
It was this thread that got me past this issue https://www.esp32.com/viewtopic.php?t=1253. I’m not sure if this is the same issue for you but I can recreate the openocd output above by having an image that runs only on the first core and then try to debug my code in VisualGDB.
