Topic: Openocd 0.11 fails to program/debug STM32

Tagged: OpenOCD 0.11 problem bug issue

This topic has 5 replies, 2 voices, and was last updated 3 years, 3 months ago by support.

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July 26, 2021 at 03:16 #30993

MrZANE
Participant

Hello.

After updating OpenOCD to 0.11 it stops being able to connect to and program my STM32 devboard with builtin STLink 2.1. Reverting back to 0.10 fixes the problem.
Here are the logs from when trying to debug using interface/stlink interface (I’ve also tried the interface/stlink-v2 and stlink-v2.1 interfaces. Same issue):

C:\Users\xxxxxxxxx\AppData\Local\VisualGDB\EmbeddedDebugPackages\com.sysprogs.arm.openocd\bin\openocd.exe -c “gdb_port 1056” -c “telnet_port 1050” -f interface/stlink.cfg -c “transport select hla_swd” -f target/stm32l4x.cfg -c “echo VisualGDB_OpenOCD_Ready”
Open On-Chip Debugger 0.11.0 (2021-06-25) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
hla_swd
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : DEPRECATED target event trace-config
VisualGDB_OpenOCD_Ready
Info : Listening on port 6666 for tcl connections
Info : Listening on port 1050 for telnet connections
Info : clock speed 500 kHz
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : STLINK V2J38M27 (API v2) VID:PID 0483:3752
Info : Target voltage: 3.266974
Info : stm32l4x.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : starting gdb server for stm32l4x.cpu on 1056
Info : Listening on port 1056 for gdb connections
Info : accepting ‘gdb’ connection on tcp/1056

If I do test settings from debug settings I get this:
VisualGDB version: 5.6.5.4229
—————— System.IO.IOException ——————
System.IO.IOException: Unable to read data from the transport connection: En befintlig anslutning tvingades att stänga av fjärrvärddatorn. —> System.Net.Sockets.SocketException: En befintlig anslutning tvingades att stänga av fjärrvärddatorn
at System.Net.Sockets.Socket.Receive(Byte[] buffer, Int32 offset, Int32 size, SocketFlags socketFlags)
at System.Net.Sockets.NetworkStream.Read(Byte[] buffer, Int32 offset, Int32 size)
— End of inner exception stack trace —
at System.Net.Sockets.NetworkStream.Read(Byte[] buffer, Int32 offset, Int32 size)
at System.IO.Stream.ReadByte()
at VisualGDB.Common_GUI.WPF.DebugMethodTestWindow.TestThreadBody()
trace=[System.Net.Sockets.NetworkStream.Read:236, System.IO.Stream.ReadByte:7, VisualGDB.Common_GUI.WPF.DebugMethodTestWindow.TestThreadBody:491]
—————— Inner exception ——————
—————— System.Net.Sockets.SocketException ——————
System.Net.Sockets.SocketException (0x80004005): En befintlig anslutning tvingades att stänga av fjärrvärddatorn
at System.Net.Sockets.Socket.Receive(Byte[] buffer, Int32 offset, Int32 size, SocketFlags socketFlags)
at System.Net.Sockets.NetworkStream.Read(Byte[] buffer, Int32 offset, Int32 size)
trace=[System.Net.Sockets.Socket.Receive:23, System.Net.Sockets.NetworkStream.Read:118]

Same with with extra debug info from OpenOCD if you need it:

C:\Users\Jimmy\AppData\Local\VisualGDB\EmbeddedDebugPackages\com.sysprogs.arm.openocd\bin\openocd.exe -c “gdb_port 1037” -c “telnet_port 1035” -c “debug_level 3” -f interface/stlink.cfg -c “transport select hla_swd” -f target/stm32l4x.cfg -c “echo VisualGDB_OpenOCD_Ready”
Open On-Chip Debugger 0.11.0 (2021-06-25) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 4 3 options.c:63 configuration_output_handler(): debug_level: 3
User : 5 3 options.c:63 configuration_output_handler():
Debug: 6 3 command.c:201 script_debug(): command – ocd_find interface/stlink.cfg
Debug: 7 3 configuration.c:99 find_file(): found interface/stlink.cfg
Debug: 8 4 command.c:201 script_debug(): command – adapter driver hla
Debug: 9 4 command.c:201 script_debug(): command – adapter driver hla
Debug: 10 4 command.c:201 script_debug(): command – hla_layout stlink
Debug: 11 4 hla_interface.c:242 hl_interface_handle_layout_command(): hl_interface_handle_layout_command
Debug: 12 5 command.c:201 script_debug(): command – hla_device_desc ST-LINK
Debug: 13 5 hla_interface.c:216 hl_interface_handle_device_desc_command(): hl_interface_handle_device_desc_command
Debug: 14 5 command.c:201 script_debug(): command – hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
Debug: 15 5 command.c:201 script_debug(): command – transport select hla_swd
Debug: 16 6 command.c:201 script_debug(): command – transport select hla_swd
Debug: 17 6 hla_transport.c:205 hl_swd_transport_select(): hl_swd_transport_select
User : 18 6 options.c:63 configuration_output_handler(): hla_swdUser : 19 6 options.c:63 configuration_output_handler():
Debug: 20 6 command.c:201 script_debug(): command – ocd_find target/stm32l4x.cfg
Debug: 21 6 configuration.c:99 find_file(): found target/stm32l4x.cfg
Debug: 22 7 command.c:201 script_debug(): command – ocd_find target/swj-dp.tcl
Debug: 23 7 configuration.c:99 find_file(): found target/swj-dp.tcl
Debug: 24 7 command.c:201 script_debug(): command – transport select
Debug: 25 7 command.c:201 script_debug(): command – transport select
Debug: 26 7 command.c:201 script_debug(): command – ocd_find mem_helper.tcl
Debug: 27 7 configuration.c:99 find_file(): found mem_helper.tcl
Debug: 28 8 command.c:201 script_debug(): command – add_usage_text mrw address
Debug: 29 8 command.c:201 script_debug(): command – add_help_text mrw Returns value of word in memory.
Debug: 30 8 command.c:201 script_debug(): command – add_usage_text mrh address
Debug: 31 8 command.c:201 script_debug(): command – add_help_text mrh Returns value of halfword in memory.
Debug: 32 8 command.c:201 script_debug(): command – add_usage_text mrb address
Debug: 33 9 command.c:201 script_debug(): command – add_help_text mrb Returns value of byte in memory.
Debug: 34 9 command.c:201 script_debug(): command – add_usage_text mmw address setbits clearbits
Debug: 35 9 command.c:201 script_debug(): command – add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 36 9 command.c:201 script_debug(): command – transport select
Debug: 37 9 command.c:201 script_debug(): command – transport select
Debug: 38 9 command.c:201 script_debug(): command – transport select
Debug: 39 9 command.c:201 script_debug(): command – transport select
Debug: 40 10 command.c:201 script_debug(): command – transport select
Debug: 41 10 command.c:201 script_debug(): command – transport select
Debug: 42 10 command.c:201 script_debug(): command – swd newdap stm32l4x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x2ba01477
Debug: 43 10 command.c:201 script_debug(): command – swd newdap stm32l4x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x2ba01477
Debug: 44 10 hla_tcl.c:110 jim_hl_newtap_cmd(): Creating New Tap, Chip: stm32l4x, Tap: cpu, Dotted: stm32l4x.cpu, 8 params
Debug: 45 11 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irlen
Debug: 46 11 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -ircapture
Debug: 47 11 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irmask
Debug: 48 11 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -expected-id
Debug: 49 11 core.c:1480 jtag_tap_init(): Created Tap: stm32l4x.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0
Debug: 50 11 command.c:201 script_debug(): command – dap create stm32l4x.dap -chain-position stm32l4x.cpu
Debug: 51 12 command.c:201 script_debug(): command – dap create stm32l4x.dap -chain-position stm32l4x.cpu
Debug: 52 12 command.c:201 script_debug(): command – transport select
Debug: 53 12 command.c:201 script_debug(): command – transport select
Debug: 54 12 command.c:201 script_debug(): command – target create stm32l4x.cpu cortex_m -endian little -dap stm32l4x.dap
Debug: 55 12 command.c:201 script_debug(): command – target create stm32l4x.cpu cortex_m -endian little -dap stm32l4x.dap
Info : 56 12 target.c:5823 target_create(): The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Debug: 57 13 hla_target.c:203 adapter_target_create(): adapter_target_create
Debug: 58 13 hla_target.c:173 adapter_init_arch_info(): adapter_init_arch_info
Debug: 59 13 command.c:335 register_command(): command ‘rtt’ is already registered
Debug: 60 13 command.c:335 register_command(): command ‘tpiu’ is already registered
Debug: 61 13 command.c:201 script_debug(): command – stm32l4x.cpu configure -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0
Debug: 62 14 command.c:201 script_debug(): command – stm32l4x.cpu configure -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0
Debug: 63 14 target.c:2189 target_free_all_working_areas_restore(): freeing all working areas
Debug: 64 14 target.c:2189 target_free_all_working_areas_restore(): freeing all working areas
Debug: 65 14 target.c:2189 target_free_all_working_areas_restore(): freeing all working areas
Debug: 66 14 command.c:201 script_debug(): command – flash bank stm32l4x.flash stm32l4x 0x08000000 0 0 0 stm32l4x.cpu
Debug: 67 15 command.c:201 script_debug(): command – flash bank stm32l4x.flash stm32l4x 0x08000000 0 0 0 stm32l4x.cpu
Debug: 68 15 tcl.c:1317 handle_flash_bank_command(): ‘stm32l4x’ driver usage field missing
Debug: 69 16 command.c:201 script_debug(): command – flash bank stm32l4x.otp stm32l4x 0x1fff7000 0 0 0 stm32l4x.cpu
Debug: 70 16 command.c:201 script_debug(): command – flash bank stm32l4x.otp stm32l4x 0x1fff7000 0 0 0 stm32l4x.cpu
Debug: 71 16 command.c:335 register_command(): command ‘stm32l4x’ is already registered
Debug: 72 17 command.c:335 register_command(): command ‘stm32l4x lock’ is already registered
Debug: 73 18 command.c:335 register_command(): command ‘stm32l4x unlock’ is already registered
Debug: 74 19 command.c:335 register_command(): command ‘stm32l4x mass_erase’ is already registered
Debug: 75 19 command.c:335 register_command(): command ‘stm32l4x option_read’ is already registered
Debug: 76 19 command.c:335 register_command(): command ‘stm32l4x option_write’ is already registered
Debug: 77 19 command.c:335 register_command(): command ‘stm32l4x wrp_info’ is already registered
Debug: 78 19 command.c:335 register_command(): command ‘stm32l4x option_load’ is already registered
Debug: 79 20 command.c:335 register_command(): command ‘stm32l4x otp’ is already registered
Debug: 80 20 tcl.c:1317 handle_flash_bank_command(): ‘stm32l4x’ driver usage field missing
Debug: 81 20 command.c:201 script_debug(): command – adapter speed 500
Debug: 82 20 command.c:201 script_debug(): command – adapter speed 500
Debug: 83 20 core.c:1818 jtag_config_khz(): handle jtag khz
Debug: 84 20 core.c:1781 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 85 20 core.c:1781 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 86 21 command.c:201 script_debug(): command – adapter srst delay 100
Debug: 87 21 command.c:201 script_debug(): command – adapter srst delay 100
Debug: 88 21 command.c:201 script_debug(): command – adapter srst delay 100
Debug: 89 21 command.c:201 script_debug(): command – transport select
Debug: 90 21 command.c:201 script_debug(): command – transport select
Debug: 91 21 command.c:201 script_debug(): command – reset_config srst_nogate
Debug: 92 22 command.c:201 script_debug(): command – transport select
Debug: 93 22 command.c:201 script_debug(): command – transport select
Debug: 94 22 command.c:201 script_debug(): command – stm32l4x.cpu configure -event reset-init
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
# Use MSI 24 MHz clock, compliant even with VOS == 2.
# 3 WS compliant with VOS == 2 and 24 MHz.
mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
# Boost JTAG frequency
adapter speed 4000

Debug: 95 23 command.c:201 script_debug(): command – stm32l4x.cpu configure -event reset-init
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
# Use MSI 24 MHz clock, compliant even with VOS == 2.
# 3 WS compliant with VOS == 2 and 24 MHz.
mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
# Boost JTAG frequency
adapter speed 4000

Debug: 96 24 command.c:201 script_debug(): command – stm32l4x.cpu configure -event reset-start
# Reset clock is MSI (4 MHz)
adapter speed 500

Debug: 97 24 command.c:201 script_debug(): command – stm32l4x.cpu configure -event reset-start
# Reset clock is MSI (4 MHz)
adapter speed 500

Debug: 98 24 command.c:201 script_debug(): command – stm32l4x.cpu configure -event examine-end
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 99 25 command.c:201 script_debug(): command – stm32l4x.cpu configure -event examine-end
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 100 25 command.c:201 script_debug(): command – stm32l4x.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0

Debug: 101 26 command.c:201 script_debug(): command – stm32l4x.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0

Info : 102 26 target.c:5073 target_configure(): DEPRECATED target event trace-config
Debug: 103 26 command.c:201 script_debug(): command – echo VisualGDB_OpenOCD_Ready
User : 104 26 command.c:729 jim_echo(): VisualGDB_OpenOCD_Ready
Info : 105 27 server.c:311 add_service(): Listening on port 6666 for tcl connections
Info : 106 28 server.c:311 add_service(): Listening on port 1035 for telnet connections
Debug: 107 28 command.c:201 script_debug(): command – init
Debug: 108 28 command.c:201 script_debug(): command – target init
Debug: 109 28 command.c:201 script_debug(): command – target init
Debug: 110 28 command.c:201 script_debug(): command – target names
Debug: 111 28 command.c:201 script_debug(): command – target names
Debug: 112 28 command.c:201 script_debug(): command – stm32l4x.cpu cget -event gdb-flash-erase-start
Debug: 113 28 command.c:201 script_debug(): command – stm32l4x.cpu cget -event gdb-flash-erase-start
Debug: 114 29 command.c:201 script_debug(): command – stm32l4x.cpu configure -event gdb-flash-erase-start reset init
Debug: 115 29 command.c:201 script_debug(): command – stm32l4x.cpu configure -event gdb-flash-erase-start reset init
Debug: 116 29 command.c:201 script_debug(): command – stm32l4x.cpu cget -event gdb-flash-write-end
Debug: 117 29 command.c:201 script_debug(): command – stm32l4x.cpu cget -event gdb-flash-write-end
Debug: 118 30 command.c:201 script_debug(): command – stm32l4x.cpu configure -event gdb-flash-write-end reset halt
Debug: 119 30 command.c:201 script_debug(): command – stm32l4x.cpu configure -event gdb-flash-write-end reset halt
Debug: 120 30 command.c:201 script_debug(): command – stm32l4x.cpu cget -event gdb-attach
Debug: 121 30 command.c:201 script_debug(): command – stm32l4x.cpu cget -event gdb-attach
Debug: 122 30 command.c:201 script_debug(): command – stm32l4x.cpu configure -event gdb-attach halt 1000
Debug: 123 30 command.c:201 script_debug(): command – stm32l4x.cpu configure -event gdb-attach halt 1000
Debug: 124 31 target.c:1656 handle_target_init_command(): Initializing targets…
Debug: 125 31 hla_target.c:193 adapter_init_target(): adapter_init_target
Debug: 126 31 semihosting_common.c:99 semihosting_common_init():
Debug: 127 32 hla_interface.c:109 hl_interface_init(): hl_interface_init
Debug: 128 32 hla_layout.c:95 hl_layout_init(): hl_layout_init
Debug: 129 32 core.c:1781 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 130 32 core.c:1785 adapter_khz_to_speed(): have interface set up
Debug: 131 32 core.c:1781 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 132 33 core.c:1785 adapter_khz_to_speed(): have interface set up
Info : 133 34 core.c:1561 adapter_init(): clock speed 500 kHz
Debug: 134 34 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 135 34 command.c:201 script_debug(): command – transport init
Debug: 136 34 command.c:201 script_debug(): command – transport init
Debug: 137 35 transport.c:230 handle_transport_init(): handle_transport_init
Debug: 138 35 hla_transport.c:156 hl_transport_init(): hl_transport_init
Debug: 139 36 hla_transport.c:173 hl_transport_init(): current transport hla_swd
Debug: 140 36 hla_interface.c:42 hl_interface_open(): hl_interface_open
Debug: 141 36 hla_layout.c:40 hl_layout_open(): hl_layout_open
Debug: 142 36 stlink_usb.c:3420 stlink_open(): stlink_open
Debug: 143 37 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3744 serial:
Debug: 144 38 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3748 serial:
Debug: 145 38 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374b serial:
Debug: 146 38 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374d serial:
Debug: 147 38 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374e serial:
Debug: 148 38 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374f serial:
Debug: 149 39 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3752 serial:
Debug: 150 39 stlink_usb.c:3432 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3753 serial:
Error: 151 183 libusb_helper.c:186 jtag_libusb_open(): libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : 152 184 stlink_usb.c:1318 stlink_usb_version(): STLINK V2J38M27 (API v2) VID:PID 0483:3752
Debug: 153 184 stlink_usb.c:1543 stlink_usb_exit_mode(): MODE: 0x02
Info : 154 185 stlink_usb.c:1354 stlink_usb_check_voltage(): Target voltage: 3.265392
Debug: 155 186 stlink_usb.c:1611 stlink_usb_init_mode(): MODE: 0x01
Debug: 156 186 stlink_usb.c:2826 stlink_dump_speed_map(): Supported clock speeds are:
Debug: 157 186 stlink_usb.c:2829 stlink_dump_speed_map(): 4000 kHz
Debug: 158 186 stlink_usb.c:2829 stlink_dump_speed_map(): 1800 kHz
Debug: 159 186 stlink_usb.c:2829 stlink_dump_speed_map(): 1200 kHz
Debug: 160 186 stlink_usb.c:2829 stlink_dump_speed_map(): 950 kHz
Debug: 161 186 stlink_usb.c:2829 stlink_dump_speed_map(): 480 kHz
Debug: 162 186 stlink_usb.c:2829 stlink_dump_speed_map(): 240 kHz
Debug: 163 188 stlink_usb.c:2829 stlink_dump_speed_map(): 125 kHz
Debug: 164 189 stlink_usb.c:2829 stlink_dump_speed_map(): 100 kHz
Debug: 165 189 stlink_usb.c:2829 stlink_dump_speed_map(): 50 kHz
Debug: 166 190 stlink_usb.c:2829 stlink_dump_speed_map(): 25 kHz
Debug: 167 190 stlink_usb.c:2829 stlink_dump_speed_map(): 15 kHz
Debug: 168 190 stlink_usb.c:2829 stlink_dump_speed_map(): 5 kHz
Debug: 169 196 stlink_usb.c:1670 stlink_usb_init_mode(): MODE: 0x02
Debug: 170 197 stlink_usb.c:3765 stlink_usb_open_ap(): AP 0 enabled
Debug: 171 198 stlink_usb.c:3508 stlink_open(): Using TAR autoincrement: 4096
Debug: 172 198 core.c:643 adapter_system_reset(): SRST line released
Debug: 173 361 hla_interface.c:67 hl_interface_init_target(): hl_interface_init_target
Debug: 174 361 stlink_usb.c:1903 stlink_usb_idcode(): IDCODE: 0x2BA01477
Debug: 175 361 command.c:201 script_debug(): command – dap init
Debug: 176 362 command.c:201 script_debug(): command – dap init
Debug: 177 362 arm_dap.c:106 dap_init_all(): Initializing all DAPs …
Debug: 178 362 openocd.c:160 handle_init_command(): Examining targets…
Debug: 179 362 target.c:1842 target_call_event_callbacks(): target event 19 (examine-start) for core stm32l4x.cpu
Debug: 180 362 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1
Debug: 181 363 target.c:2610 target_read_u32(): address: 0xe000ed00, value: 0x410fc241
Debug: 182 363 cortex_m.c:2309 cortex_m_examine(): Cortex-M4 r0p1 processor detected
Debug: 183 363 cortex_m.c:2321 cortex_m_examine(): cpuid: 0x410fc241
Debug: 184 363 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000ef40 4 1
Debug: 185 364 target.c:2610 target_read_u32(): address: 0xe000ef40, value: 0x10110021
Debug: 186 364 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000ef44 4 1
Debug: 187 365 target.c:2610 target_read_u32(): address: 0xe000ef44, value: 0x11000011
Debug: 188 366 cortex_m.c:2329 cortex_m_examine(): Cortex-M4 floating point feature FPv4_SP found
Debug: 189 368 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000edf0 4 1
Debug: 190 369 target.c:2610 target_read_u32(): address: 0xe000edf0, value: 0x00030003
Debug: 191 369 target.c:2698 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 192 370 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1
Debug: 193 371 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1
Debug: 194 374 target.c:2610 target_read_u32(): address: 0xe0002000, value: 0x00000260
Debug: 195 374 target.c:2698 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 196 374 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1
Debug: 197 375 target.c:2698 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 198 375 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1
Debug: 199 376 target.c:2698 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 200 376 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1
Debug: 201 377 target.c:2698 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 202 377 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1
Debug: 203 378 target.c:2698 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 204 378 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1
Debug: 205 379 target.c:2698 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 206 379 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1
Debug: 207 380 target.c:2698 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 208 380 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1
Debug: 209 381 target.c:2698 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 210 381 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1
Debug: 211 382 cortex_m.c:2409 cortex_m_examine(): FPB fpcr 0x260, numcode 6, numlit 2
Debug: 212 382 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1
Debug: 213 383 target.c:2610 target_read_u32(): address: 0xe0001000, value: 0x40000001
Debug: 214 383 cortex_m.c:2142 cortex_m_dwt_setup(): DWT_CTRL: 0x40000001
Debug: 215 383 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0001fbc 4 1
Debug: 216 393 target.c:2610 target_read_u32(): address: 0xe0001fbc, value: 0x00000000
Debug: 217 393 cortex_m.c:2149 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0
Debug: 218 393 target.c:2698 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 219 393 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1
Debug: 220 394 target.c:2698 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 221 394 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1
Debug: 222 395 target.c:2698 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 223 395 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1
Debug: 224 396 target.c:2698 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 225 396 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1
Debug: 226 397 cortex_m.c:2196 cortex_m_dwt_setup(): DWT dwtcr 0x40000001, comp 4, watch/trigger
Info : 227 397 cortex_m.c:2419 cortex_m_examine(): stm32l4x.cpu: hardware has 6 breakpoints, 4 watchpoints
Debug: 228 397 target.c:1842 target_call_event_callbacks(): target event 21 (examine-end) for core stm32l4x.cpu
Debug: 229 398 target.c:4893 target_handle_event(): target(0): stm32l4x.cpu (hla_target) event: 21 (examine-end) action:
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 230 398 command.c:201 script_debug(): command – mem2array value 32 0xE0042004 1
Debug: 231 399 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 232 400 target.c:2610 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 233 401 armv7m.c:377 armv7m_read_core_reg(): read r0 value 0x00000001
Debug: 234 403 armv7m.c:377 armv7m_read_core_reg(): read r1 value 0x0000003e
Debug: 235 404 armv7m.c:377 armv7m_read_core_reg(): read r2 value 0x200004bc
Debug: 236 405 armv7m.c:377 armv7m_read_core_reg(): read r3 value 0x00000000
Debug: 237 407 armv7m.c:377 armv7m_read_core_reg(): read r4 value 0x00000000
Debug: 238 408 armv7m.c:377 armv7m_read_core_reg(): read r5 value 0x00000000
Debug: 239 409 armv7m.c:377 armv7m_read_core_reg(): read r6 value 0x00000000
Debug: 240 411 armv7m.c:377 armv7m_read_core_reg(): read r7 value 0x2000fff0
Debug: 241 412 armv7m.c:377 armv7m_read_core_reg(): read r8 value 0x00000000
Debug: 242 414 armv7m.c:377 armv7m_read_core_reg(): read r9 value 0x00000000
Debug: 243 415 armv7m.c:377 armv7m_read_core_reg(): read r10 value 0x00000000
Debug: 244 417 armv7m.c:377 armv7m_read_core_reg(): read r11 value 0x00000000
Debug: 245 418 armv7m.c:377 armv7m_read_core_reg(): read r12 value 0x00000018
Debug: 246 419 armv7m.c:377 armv7m_read_core_reg(): read sp value 0x2000fff0
Debug: 247 421 armv7m.c:377 armv7m_read_core_reg(): read lr value 0x08005c6b
Debug: 248 422 armv7m.c:377 armv7m_read_core_reg(): read pc value 0x08000d06
Debug: 249 423 armv7m.c:377 armv7m_read_core_reg(): read xPSR value 0x61000000
Debug: 250 424 armv7m.c:377 armv7m_read_core_reg(): read msp value 0x2000fff0
Debug: 251 426 armv7m.c:377 armv7m_read_core_reg(): read psp value 0x00000000
Debug: 252 427 armv7m.c:377 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl value 0x00000000
Debug: 253 429 armv7m.c:375 armv7m_read_core_reg(): read d0 value 0x0000000000000000
Debug: 254 432 armv7m.c:375 armv7m_read_core_reg(): read d1 value 0x0000000000000000
Debug: 255 435 armv7m.c:375 armv7m_read_core_reg(): read d2 value 0x0000000000000000
Debug: 256 440 armv7m.c:375 armv7m_read_core_reg(): read d3 value 0x0000000000000000
Debug: 257 443 armv7m.c:375 armv7m_read_core_reg(): read d4 value 0x0000000000000000
Debug: 258 445 armv7m.c:375 armv7m_read_core_reg(): read d5 value 0x0000000000000000
Debug: 259 448 armv7m.c:375 armv7m_read_core_reg(): read d6 value 0x0000000000000000
Debug: 260 450 armv7m.c:375 armv7m_read_core_reg(): read d7 value 0x0000000000000000
Debug: 261 453 armv7m.c:375 armv7m_read_core_reg(): read d8 value 0x0000000000000000
Debug: 262 455 armv7m.c:375 armv7m_read_core_reg(): read d9 value 0x0000000000000000
Debug: 263 457 armv7m.c:375 armv7m_read_core_reg(): read d10 value 0x0000000000000000
Debug: 264 460 armv7m.c:375 armv7m_read_core_reg(): read d11 value 0x0000000000000000
Debug: 265 462 armv7m.c:375 armv7m_read_core_reg(): read d12 value 0x0000000000000000
Debug: 266 465 armv7m.c:375 armv7m_read_core_reg(): read d13 value 0x0000000000000000
Debug: 267 467 armv7m.c:375 armv7m_read_core_reg(): read d14 value 0x0000000000000000
Debug: 268 470 armv7m.c:375 armv7m_read_core_reg(): read d15 value 0x0000000000000000
Debug: 269 471 armv7m.c:377 armv7m_read_core_reg(): read fpscr value 0x00000000
Debug: 270 472 hla_target.c:286 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x08000d06, target->state: halted
Debug: 271 472 target.c:1842 target_call_event_callbacks(): target event 0 (gdb-halt) for core stm32l4x.cpu
Debug: 272 472 target.c:1842 target_call_event_callbacks(): target event 1 (halted) for core stm32l4x.cpu
Debug: 273 473 hla_target.c:331 adapter_poll(): halted: PC: 0x08000d06
Debug: 274 473 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 275 474 command.c:201 script_debug(): command – mww 0xE0042004 7
Debug: 276 474 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 277 475 command.c:201 script_debug(): command – mem2array value 32 0xE0042008 1
Debug: 278 476 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 279 477 command.c:201 script_debug(): command – mww 0xE0042008 6144
Debug: 280 478 hla_target.c:617 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 281 478 command.c:201 script_debug(): command – flash init
Debug: 282 479 command.c:201 script_debug(): command – flash init
Debug: 283 479 tcl.c:1383 handle_flash_init_command(): Initializing flash devices…
Debug: 284 479 command.c:201 script_debug(): command – nand init
Debug: 285 480 command.c:201 script_debug(): command – nand init
Debug: 286 480 tcl.c:498 handle_nand_init_command(): Initializing NAND devices…
Debug: 287 480 command.c:201 script_debug(): command – pld init
Debug: 288 480 command.c:201 script_debug(): command – pld init
Debug: 289 481 pld.c:206 handle_pld_init_command(): Initializing PLDs…
Debug: 290 481 command.c:201 script_debug(): command – tpiu init
Debug: 291 481 command.c:201 script_debug(): command – tpiu init
Info : 292 482 gdb_server.c:3544 gdb_target_start(): starting gdb server for stm32l4x.cpu on 1037
Info : 293 482 server.c:311 add_service(): Listening on port 1037 for gdb connections
Info : 294 2442 server.c:101 add_connection(): accepting ‘gdb’ connection on tcp/1037
Debug: 295 2442 breakpoints.c:383 breakpoint_clear_target_internal(): Delete all breakpoints for target: stm32l4x.cpu
Debug: 296 2442 breakpoints.c:523 watchpoint_clear_target(): Delete all watchpoints for target: stm32l4x.cpu
Debug: 297 2443 target.c:1842 target_call_event_callbacks(): target event 22 (gdb-attach) for core stm32l4x.cpu
Debug: 298 2443 target.c:4893 target_handle_event(): target(0): stm32l4x.cpu (hla_target) event: 22 (gdb-attach) action: halt 1000
Debug: 299 2443 command.c:201 script_debug(): command – halt 1000
Debug: 300 2444 target.c:3283 handle_halt_command(): –
Debug: 301 2444 hla_target.c:418 adapter_halt(): adapter_halt
Debug: 302 2444 hla_target.c:421 adapter_halt(): target was already halted
Debug: 303 2445 hla_target.c:602 adapter_read_memory(): adapter_read_memory 0xe0042000 4 1
Debug: 304 2446 target.c:2610 target_read_u32(): address: 0xe0042000, value: 0x10016435

July 26, 2021 at 06:13 #30995

MrZANE
Participant

Forgot to mention VisualGDB version. It’s 5.6 Beta 4, build 4229

July 29, 2021 at 14:28 #31018

MrZANE
Participant

Any comments/tips on this issue?

July 29, 2021 at 20:26 #31019

support
Keymaster

Hi,

OpenOCD support for specific devices is usually contributed by the device vendors or someone from the OpenOCD community. We periodically release builds based on the latest OpenOCD source, however we do not maintain device-specific parts of it.

The OpenOCD code base is evolving very fast, so there is a high chance the issue is already fixed in the latest OpenOCD build released today. Please try installing it via VisualGDB Package Manager.

Alternatively, please consider using Segger J-Link with the J-Link software. The J-Link software is a proprietary replacement to OpenOCD that is maintained and tested by Segger, and it usually works more reliably than open-source tools. VisualGDB is integrated with both tools equally well, so you can chose the best one for your setup based on your requirements.

August 2, 2021 at 01:02 #31042

MrZANE
Participant

Hi,

I realize that. The thing is that the output openocd output looks OK (At least the short one, haven’t read through the long output).
I though there might be something wrong with the visualgdb parser thinking there is an error when there isn’t.
Also the openocd is installed with your package-manager so I was thinking/hopping that it should be tested to work with one of the most popular CPU families (STM32).

I might be wrong in my assumptions though.
Would be nice if you could just test the latest openocd released in the package-manager with a STM32 CPU to see where the problem is and either fix it if it’s on your side and otherwise add a note in the PM about not working with stm32

Kind regards

August 2, 2021 at 06:26 #31043

support
Keymaster

No problem. Please feel free to run OpenOCD with gdb manually. If you can confirm that the debugging works outside VisualGDB, but doesn’t work with VisualGDB, we can definitely fix it.

Regarding the tests, we indeed run a few very basic tests on a few devices before releasing each OpenOCD package, but it doesn’t include programming FLASH memory on STM32L4.

In general, we provide the package mechanism so that our users would not need to locate the relevant code and build if from scratch. They are built automatically on our side with a few very basic tests, and are provided free of charge. Unfortunately, it not viable to extend our technical support to a huge code base maintained by thousands of external developers without directly charging for the time needed to investigate and fix these issues.

As mentioned before, please consider using VisualGDB with the J-Link software. It is maintained and tested by Segger and generally works more reliable than free OpenOCD.
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