HAL
TIM_HandleTypeDef::ChannelNState is only used within HAL.
 
Symbols
loading...
Files
loading...
CodeScopeSTM32 Libraries and SamplesHALTIM_HandleTypeDef::ChannelNState

TIM_HandleTypeDef::ChannelNState field

TIM complementary channel operation state

Syntax

__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4];

References

LocationReferrerText
stm32f4xx_hal_tim.h:348
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
stm32f4xx_hal_tim.c:313HAL_TIM_Base_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:353HAL_TIM_Base_DeInit()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:697HAL_TIM_OC_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:737HAL_TIM_OC_DeInit()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:1362HAL_TIM_PWM_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1402HAL_TIM_PWM_DeInit()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2026HAL_TIM_IC_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2066HAL_TIM_IC_DeInit()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2122HAL_TIM_IC_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
stm32f4xx_hal_tim.c:2136HAL_TIM_IC_Start()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2183HAL_TIM_IC_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2206HAL_TIM_IC_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
stm32f4xx_hal_tim.c:2220HAL_TIM_IC_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2344HAL_TIM_IC_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2370HAL_TIM_IC_Start_DMA()
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
stm32f4xx_hal_tim.c:2392HAL_TIM_IC_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2580HAL_TIM_IC_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2683HAL_TIM_OnePulse_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2684HAL_TIM_OnePulse_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2725HAL_TIM_OnePulse_DeInit()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2726HAL_TIM_OnePulse_DeInit()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2781HAL_TIM_OnePulse_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:2782HAL_TIM_OnePulse_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:2799HAL_TIM_OnePulse_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2800HAL_TIM_OnePulse_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2860HAL_TIM_OnePulse_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2861HAL_TIM_OnePulse_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2881HAL_TIM_OnePulse_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:2882HAL_TIM_OnePulse_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:2899HAL_TIM_OnePulse_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2900HAL_TIM_OnePulse_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2971HAL_TIM_OnePulse_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2972HAL_TIM_OnePulse_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3119HAL_TIM_Encoder_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3120HAL_TIM_Encoder_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3162HAL_TIM_Encoder_DeInit()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:3163HAL_TIM_Encoder_DeInit()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:3218HAL_TIM_Encoder_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3219HAL_TIM_Encoder_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3235HAL_TIM_Encoder_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3248HAL_TIM_Encoder_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3264HAL_TIM_Encoder_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3265HAL_TIM_Encoder_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3344HAL_TIM_Encoder_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3350HAL_TIM_Encoder_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3351HAL_TIM_Encoder_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3372HAL_TIM_Encoder_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3373HAL_TIM_Encoder_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3389HAL_TIM_Encoder_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3402HAL_TIM_Encoder_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3418HAL_TIM_Encoder_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3419HAL_TIM_Encoder_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3506HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3512HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3513HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3538HAL_TIM_Encoder_Start_DMA()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3539HAL_TIM_Encoder_Start_DMA()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3562HAL_TIM_Encoder_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3587HAL_TIM_Encoder_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3617HAL_TIM_Encoder_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3618HAL_TIM_Encoder_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3788HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3794HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3795HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6611TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6621TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6631TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6641TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:226HAL_TIMEx_HallSensor_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:227HAL_TIMEx_HallSensor_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:268HAL_TIMEx_HallSensor_DeInit()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim_ex.c:269HAL_TIMEx_HallSensor_DeInit()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim_ex.c:320HAL_TIMEx_HallSensor_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:321HAL_TIMEx_HallSensor_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:338HAL_TIMEx_HallSensor_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:339HAL_TIMEx_HallSensor_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:385HAL_TIMEx_HallSensor_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:386HAL_TIMEx_HallSensor_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:402HAL_TIMEx_HallSensor_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:403HAL_TIMEx_HallSensor_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:420HAL_TIMEx_HallSensor_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:421HAL_TIMEx_HallSensor_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:473HAL_TIMEx_HallSensor_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:474HAL_TIMEx_HallSensor_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:491HAL_TIMEx_HallSensor_Start_DMA()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:512HAL_TIMEx_HallSensor_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:584HAL_TIMEx_HallSensor_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:633HAL_TIMEx_OCN_Start()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:639HAL_TIMEx_OCN_Start()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:691HAL_TIMEx_OCN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:717HAL_TIMEx_OCN_Start_IT()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:723HAL_TIMEx_OCN_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:850HAL_TIMEx_OCN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:880HAL_TIMEx_OCN_Start_DMA()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
stm32f4xx_hal_tim_ex.c:884HAL_TIMEx_OCN_Start_DMA()
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:892HAL_TIMEx_OCN_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1058HAL_TIMEx_OCN_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1106HAL_TIMEx_PWMN_Start()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1112HAL_TIMEx_PWMN_Start()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1163HAL_TIMEx_PWMN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1189HAL_TIMEx_PWMN_Start_IT()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1195HAL_TIMEx_PWMN_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1321HAL_TIMEx_PWMN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1351HAL_TIMEx_PWMN_Start_DMA()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
stm32f4xx_hal_tim_ex.c:1355HAL_TIMEx_PWMN_Start_DMA()
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1363HAL_TIMEx_PWMN_Start_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1529HAL_TIMEx_PWMN_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1575HAL_TIMEx_OnePulseN_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:1576HAL_TIMEx_OnePulseN_Start()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:1593HAL_TIMEx_OnePulseN_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1594HAL_TIMEx_OnePulseN_Start()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1639HAL_TIMEx_OnePulseN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1640HAL_TIMEx_OnePulseN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1663HAL_TIMEx_OnePulseN_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:1664HAL_TIMEx_OnePulseN_Start_IT()
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:1681HAL_TIMEx_OnePulseN_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1682HAL_TIMEx_OnePulseN_Start_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1739HAL_TIMEx_OnePulseN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1740HAL_TIMEx_OnePulseN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2231HAL_TIMEx_GetChannelNState()
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
stm32f4xx_hal_tim_ex.c:2302TIM_DMADelayPulseNCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2311TIM_DMADelayPulseNCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2320TIM_DMADelayPulseNCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2349TIM_DMAErrorCCxN()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2354TIM_DMAErrorCCxN()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2359TIM_DMAErrorCCxN()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

Data Use

Type of TIM_HandleTypeDef::ChannelNState
TIM_HandleTypeDef::ChannelNState
all items filtered out