HAL
HAL_TIM_ChannelStateTypeDef::HAL_TIM_CHANNEL_STATE_READY is only used within HAL.
 
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CodeScopeSTM32 Libraries and SamplesHALHAL_TIM_ChannelStateTypeDef::HAL_TIM_CHANNEL_STATE_READY

HAL_TIM_ChannelStateTypeDef::HAL_TIM_CHANNEL_STATE_READY

Syntax

HAL_TIM_CHANNEL_STATE_READY = 0x01U;

References

LocationReferrerText
stm32f4xx_hal_tim.h:305
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
stm32f4xx_hal_tim.c:312HAL_TIM_Base_Init()
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:313HAL_TIM_Base_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:696HAL_TIM_OC_Init()
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:697HAL_TIM_OC_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:797HAL_TIM_OC_Start()
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:861HAL_TIM_OC_Stop()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:887HAL_TIM_OC_Start_IT()
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:1028HAL_TIM_OC_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1062HAL_TIM_OC_Start_DMA()
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:1273HAL_TIM_OC_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1361HAL_TIM_PWM_Init()
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1362HAL_TIM_PWM_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1462HAL_TIM_PWM_Start()
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:1526HAL_TIM_PWM_Stop()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1552HAL_TIM_PWM_Start_IT()
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:1693HAL_TIM_PWM_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:1727HAL_TIM_PWM_Start_DMA()
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:1937HAL_TIM_PWM_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2025HAL_TIM_IC_Init()
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2026HAL_TIM_IC_Init()
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2128HAL_TIM_IC_Start()
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2129HAL_TIM_IC_Start()
|| (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:2182HAL_TIM_IC_Stop()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2183HAL_TIM_IC_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2212HAL_TIM_IC_Start_IT()
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2213HAL_TIM_IC_Start_IT()
|| (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:2343HAL_TIM_IC_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2344HAL_TIM_IC_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2382HAL_TIM_IC_Start_DMA()
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2383HAL_TIM_IC_Start_DMA()
&& (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:2579HAL_TIM_IC_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2580HAL_TIM_IC_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2681HAL_TIM_OnePulse_Init()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2682HAL_TIM_OnePulse_Init()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2683HAL_TIM_OnePulse_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2684HAL_TIM_OnePulse_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2788HAL_TIM_OnePulse_Start()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2789HAL_TIM_OnePulse_Start()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2790HAL_TIM_OnePulse_Start()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2791HAL_TIM_OnePulse_Start()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:2858HAL_TIM_OnePulse_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2859HAL_TIM_OnePulse_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2860HAL_TIM_OnePulse_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2861HAL_TIM_OnePulse_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2888HAL_TIM_OnePulse_Start_IT()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2889HAL_TIM_OnePulse_Start_IT()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2890HAL_TIM_OnePulse_Start_IT()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:2891HAL_TIM_OnePulse_Start_IT()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:2969HAL_TIM_OnePulse_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2970HAL_TIM_OnePulse_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2971HAL_TIM_OnePulse_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2972HAL_TIM_OnePulse_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3117HAL_TIM_Encoder_Init()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3118HAL_TIM_Encoder_Init()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3119HAL_TIM_Encoder_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3120HAL_TIM_Encoder_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3227HAL_TIM_Encoder_Start()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3228HAL_TIM_Encoder_Start()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3240HAL_TIM_Encoder_Start()
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3241HAL_TIM_Encoder_Start()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3253HAL_TIM_Encoder_Start()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3254HAL_TIM_Encoder_Start()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3255HAL_TIM_Encoder_Start()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3256HAL_TIM_Encoder_Start()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3343HAL_TIM_Encoder_Stop()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3344HAL_TIM_Encoder_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3348HAL_TIM_Encoder_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3349HAL_TIM_Encoder_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3350HAL_TIM_Encoder_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3351HAL_TIM_Encoder_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3381HAL_TIM_Encoder_Start_IT()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3382HAL_TIM_Encoder_Start_IT()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3394HAL_TIM_Encoder_Start_IT()
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3395HAL_TIM_Encoder_Start_IT()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3407HAL_TIM_Encoder_Start_IT()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3408HAL_TIM_Encoder_Start_IT()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3409HAL_TIM_Encoder_Start_IT()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3410HAL_TIM_Encoder_Start_IT()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3505HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3506HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3510HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3511HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3512HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3513HAL_TIM_Encoder_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3552HAL_TIM_Encoder_Start_DMA()
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3553HAL_TIM_Encoder_Start_DMA()
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3577HAL_TIM_Encoder_Start_DMA()
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3578HAL_TIM_Encoder_Start_DMA()
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3604HAL_TIM_Encoder_Start_DMA()
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3605HAL_TIM_Encoder_Start_DMA()
&& (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3606HAL_TIM_Encoder_Start_DMA()
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim.c:3607HAL_TIM_Encoder_Start_DMA()
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim.c:3787HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3788HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3792HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3793HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3794HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3795HAL_TIM_Encoder_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6466TIM_DMAError()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6471TIM_DMAError()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6476TIM_DMAError()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6481TIM_DMAError()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6512TIM_DMADelayPulseCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6521TIM_DMADelayPulseCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6530TIM_DMADelayPulseCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6539TIM_DMADelayPulseCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6610TIM_DMACaptureCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6611TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6620TIM_DMACaptureCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6621TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6630TIM_DMACaptureCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6631TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6640TIM_DMACaptureCplt()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6641TIM_DMACaptureCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:224HAL_TIMEx_HallSensor_Init()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:225HAL_TIMEx_HallSensor_Init()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:226HAL_TIMEx_HallSensor_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:227HAL_TIMEx_HallSensor_Init()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:327HAL_TIMEx_HallSensor_Start()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:328HAL_TIMEx_HallSensor_Start()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:329HAL_TIMEx_HallSensor_Start()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:330HAL_TIMEx_HallSensor_Start()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim_ex.c:383HAL_TIMEx_HallSensor_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:384HAL_TIMEx_HallSensor_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:385HAL_TIMEx_HallSensor_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:386HAL_TIMEx_HallSensor_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:409HAL_TIMEx_HallSensor_Start_IT()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:410HAL_TIMEx_HallSensor_Start_IT()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:411HAL_TIMEx_HallSensor_Start_IT()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:412HAL_TIMEx_HallSensor_Start_IT()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim_ex.c:471HAL_TIMEx_HallSensor_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:472HAL_TIMEx_HallSensor_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:473HAL_TIMEx_HallSensor_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:474HAL_TIMEx_HallSensor_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:502HAL_TIMEx_HallSensor_Start_DMA()
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:503HAL_TIMEx_HallSensor_Start_DMA()
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim_ex.c:583HAL_TIMEx_HallSensor_Stop_DMA()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:584HAL_TIMEx_HallSensor_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:633HAL_TIMEx_OCN_Start()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:691HAL_TIMEx_OCN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:717HAL_TIMEx_OCN_Start_IT()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:850HAL_TIMEx_OCN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:884HAL_TIMEx_OCN_Start_DMA()
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1058HAL_TIMEx_OCN_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1106HAL_TIMEx_PWMN_Start()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1163HAL_TIMEx_PWMN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1189HAL_TIMEx_PWMN_Start_IT()
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1321HAL_TIMEx_PWMN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1355HAL_TIMEx_PWMN_Start_DMA()
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1529HAL_TIMEx_PWMN_Stop_DMA()
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1582HAL_TIMEx_OnePulseN_Start()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1583HAL_TIMEx_OnePulseN_Start()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1584HAL_TIMEx_OnePulseN_Start()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1585HAL_TIMEx_OnePulseN_Start()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim_ex.c:1637HAL_TIMEx_OnePulseN_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1638HAL_TIMEx_OnePulseN_Stop()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1639HAL_TIMEx_OnePulseN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1640HAL_TIMEx_OnePulseN_Stop()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1670HAL_TIMEx_OnePulseN_Start_IT()
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1671HAL_TIMEx_OnePulseN_Start_IT()
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1672HAL_TIMEx_OnePulseN_Start_IT()
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
stm32f4xx_hal_tim_ex.c:1673HAL_TIMEx_OnePulseN_Start_IT()
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
stm32f4xx_hal_tim_ex.c:1737HAL_TIMEx_OnePulseN_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1738HAL_TIMEx_OnePulseN_Stop_IT()
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1739HAL_TIMEx_OnePulseN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1740HAL_TIMEx_OnePulseN_Stop_IT()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2302TIM_DMADelayPulseNCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2311TIM_DMADelayPulseNCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2320TIM_DMADelayPulseNCplt()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2349TIM_DMAErrorCCxN()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2354TIM_DMAErrorCCxN()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2359TIM_DMAErrorCCxN()
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

Data Use

Functions using HAL_TIM_ChannelStateTypeDef::HAL_TIM_CHANNEL_STATE_READY
HAL_TIM_ChannelStateTypeDef::HAL_TIM_CHANNEL_STATE_READY
all items filtered out