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CodeScopeSTM32 Libraries and SamplesHALTIM_CHANNEL_1

TIM_CHANNEL_1 macro

Capture/compare channel 1 identifier

Syntax

#define TIM_CHANNEL_1 0x00000000U

Examples

TIM_CHANNEL_1 is referenced by 112 libraries and example projects.

References

LocationText
stm32f4xx_hal_tim.h:738
#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
stm32f4xx_hal_tim.c:897
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:980
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:1080
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:1221
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:1562
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:1645
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:1745
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:1885
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:2224
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:2301
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:2405
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:2536
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:2681
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2683
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2723
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2725
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2779
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:2781
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:2797
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2799
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2811
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:2845
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:2858
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2860
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2879
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:2881
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:2897
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2899
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2917
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:2956
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:2969
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2971
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3117
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3119
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3160
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:3162
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:3216
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3218
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3225
if (Channel == TIM_CHANNEL_1)
stm32f4xx_hal_tim.c:3234
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3235
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3262
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3264
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3272
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:3274
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3286
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3317
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:3319
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3331
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3341
if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
stm32f4xx_hal_tim.c:3348
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3350
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3370
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3372
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3379
if (Channel == TIM_CHANNEL_1)
stm32f4xx_hal_tim.c:3388
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3389
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3416
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3418
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3427
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:3429
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3443
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3475
if (Channel == TIM_CHANNEL_1)
stm32f4xx_hal_tim.c:3477
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3491
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3503
if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
stm32f4xx_hal_tim.c:3510
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3512
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3536
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3538
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim.c:3545
if (Channel == TIM_CHANNEL_1)
stm32f4xx_hal_tim.c:3561
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3562
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3615
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3617
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3629
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:3649
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3722
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3753
if (Channel == TIM_CHANNEL_1)
stm32f4xx_hal_tim.c:3755
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3771
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3785
if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
stm32f4xx_hal_tim.c:3792
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3794
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:4057
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:4134
if (Channel == TIM_CHANNEL_1)
stm32f4xx_hal_tim.c:4236
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:4360
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:4385
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:5229
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:5579
case TIM_CHANNEL_1:
stm32f4xx_hal_tim.c:6466
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6512
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6610
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6611
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6861
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
stm32f4xx_hal_tim.h:1395
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
stm32f4xx_hal_tim.h:1647
#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
stm32f4xx_hal_tim.h:1653
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
stm32f4xx_hal_tim.h:1831
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
stm32f4xx_hal_tim.h:1837
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
stm32f4xx_hal_tim.h:1850
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
stm32f4xx_hal_tim.h:1856
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
stm32f4xx_hal_tim_ex.c:224
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:226
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:266
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim_ex.c:268
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim_ex.c:318
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:320
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:336
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:338
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:344
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim_ex.c:377
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim_ex.c:383
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:385
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:400
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:402
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:418
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:420
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:429
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim_ex.c:462
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim_ex.c:471
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:473
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:490
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:491
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:511
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:512
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:523
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
stm32f4xx_hal_tim_ex.c:571
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
stm32f4xx_hal_tim_ex.c:583
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:584
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:727
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:805
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:902
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:1017
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:1199
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:1276
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:1373
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:1488
case TIM_CHANNEL_1:
stm32f4xx_hal_tim_ex.c:1572
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1573
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:1575
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:1591
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1593
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1621
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1637
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1639
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1660
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1661
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:1663
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
stm32f4xx_hal_tim_ex.c:1679
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1681
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1715
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1737
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1739
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2302
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2349
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);