HAL + 0/102 examples
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TIM
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TIM
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TIM
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TIM
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CodeScopeSTM32 Libraries and SamplesHALTIM_CHANNEL_2

TIM_CHANNEL_2 macro

Capture/compare channel 2 identifier

Syntax

#define TIM_CHANNEL_2 0x00000004U

Examples

TIM_CHANNEL_2 is referenced by 102 libraries and example projects.

References

LocationText
stm32f4xx_hal_tim.h:739
#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
stm32f4xx_hal_tim.c:904
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:987
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:1102
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:1229
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:1569
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:1652
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:1767
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:1893
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:2231
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:2308
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:2426
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:2544
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:2682
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2684
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2724
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2726
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:2780
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:2782
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:2798
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2800
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2812
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:2846
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:2859
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2861
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2880
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:2882
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:2898
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2900
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:2918
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:2957
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:2970
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:2972
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3118
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3120
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3161
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:3163
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim.c:3217
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3219
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3238
else if (Channel == TIM_CHANNEL_2)
stm32f4xx_hal_tim.c:3247
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3248
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3263
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3265
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3278
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:3280
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3287
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3323
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:3325
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3332
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3341
if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
stm32f4xx_hal_tim.c:3349
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3351
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3371
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3373
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3392
else if (Channel == TIM_CHANNEL_2)
stm32f4xx_hal_tim.c:3401
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3402
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3417
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3419
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3434
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:3436
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3444
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3482
else if (Channel == TIM_CHANNEL_2)
stm32f4xx_hal_tim.c:3484
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3492
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3503
if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
stm32f4xx_hal_tim.c:3511
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3513
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3537
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3539
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim.c:3570
else if (Channel == TIM_CHANNEL_2)
stm32f4xx_hal_tim.c:3586
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3587
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3616
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3618
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim.c:3657
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:3676
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3723
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
stm32f4xx_hal_tim.c:3761
else if (Channel == TIM_CHANNEL_2)
stm32f4xx_hal_tim.c:3763
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3772
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
stm32f4xx_hal_tim.c:3785
if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
stm32f4xx_hal_tim.c:3793
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:3795
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:4067
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:4148
else if (Channel == TIM_CHANNEL_2)
stm32f4xx_hal_tim.c:4253
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:4368
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:4405
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:5243
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:5589
case TIM_CHANNEL_2:
stm32f4xx_hal_tim.c:6471
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6521
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6620
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6621
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim.c:6938
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
stm32f4xx_hal_tim.h:1396
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
stm32f4xx_hal_tim.h:1648
((__CHANNEL__) == TIM_CHANNEL_2) || \
stm32f4xx_hal_tim.h:1654
((__CHANNEL__) == TIM_CHANNEL_2))
stm32f4xx_hal_tim.h:1832
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
stm32f4xx_hal_tim.h:1838
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
stm32f4xx_hal_tim.h:1851
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
stm32f4xx_hal_tim.h:1857
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
stm32f4xx_hal_tim_ex.c:225
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:227
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:267
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim_ex.c:269
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
stm32f4xx_hal_tim_ex.c:319
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:321
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:337
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:339
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:384
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:386
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:401
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:403
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:419
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:421
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:472
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:474
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:734
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:812
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:923
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:1025
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:1206
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:1283
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:1394
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:1496
case TIM_CHANNEL_2:
stm32f4xx_hal_tim_ex.c:1572
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1574
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:1576
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:1592
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1594
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1621
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1638
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1640
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1660
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1662
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:1664
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
stm32f4xx_hal_tim_ex.c:1680
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1682
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
stm32f4xx_hal_tim_ex.c:1715
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
stm32f4xx_hal_tim_ex.c:1738
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:1740
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2311
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
stm32f4xx_hal_tim_ex.c:2354
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);