__HAL_RCC_PLLI2S_CONFIG macro

This macro must be used only when the PLLI2S is disabled. PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API). You have to set the PLLI2SM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 1 MHz to limit PLLI2S jitter. You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz. the PLLI2SP parameter is only available with STM32F446xx Devices You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.