OpenOCD
BIT is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDBIT

BIT macro

Syntax

#define BIT(nr) (1UL << (nr))

Arguments

nr

References

LocationText
bits.h:19
#define BIT(nr) (1UL << (nr))
arc.h:37
#define SET_CORE_FORCE_HALT BIT(1)
arc.h:38
#define SET_CORE_HALT_BIT BIT(0) /* STATUS32[0] = H field */
arc.h:39
#define SET_CORE_ENABLE_INTERRUPTS BIT(31)
arc.h:41
#define SET_CORE_AE_BIT BIT(5)
arc.h:43
#define SET_CORE_SINGLE_INSTR_STEP BIT(11)
arc.h:45
#define AUX_STATUS32_REG_HALT_BIT BIT(0)
arc.h:46
#define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */
arc.h:111
#define DC_IVDC_INVALIDATE BIT(0)
arc.h:113
#define DC_CTRL_IM BIT(6)
arc.h:117
#define L2_CTRL_IM BIT(6)
arc.h:118
#define L2_CTRL_BS BIT(8) /* Busy flag */
arc.h:120
#define L2_FLUSH_FL BIT(0)
arc.h:122
#define L2_INV_IV BIT(0)
arm_adi_v5.c:910
ap->csw_size_supported_mask = BIT(CSW_32BIT);
arm_adi_v5.c:911
ap->csw_size_probed_mask = BIT(CSW_32BIT);
arm_adi_v5.c:915
ap->csw_size_probed_mask |= BIT(CSW_64BIT) | BIT(CSW_128BIT) | BIT(CSW_256BIT);
arm_adi_v5.h:79
#define DP_BASEPTR0_VALID BIT(0)
arm_adi_v5.h:206
#define MEM_AP_REG_CFG_BE BIT(0)
arm_adi_v5.h:207
#define MEM_AP_REG_CFG_LA BIT(1)
arm_adi_v5.h:208
#define MEM_AP_REG_CFG_LD BIT(2)
arm_coresight.h:38
#define ARM_CS_PIDR_JEDEC BIT(19)
arm_coresight.h:63
#define ARM_CS_C9_DEVARCH_PRESENT BIT(20)
arm_coresight.h:76
#define ARM_CS_C9_DEVID_SYSMEM_MASK BIT(4)
arm_coresight.h:93
#define ARM_CS_C1_MEMTYPE_SYSMEM_MASK BIT(0)
arm_coresight.h:97
#define ARM_CS_ROMENTRY_PRESENT BIT(0)
arm_jtag.h:35
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (new_instr & (BIT(tap->ir_length) - 1)))
arm_tpiu_swo.c:64
#define TPIU_DEVID_NOSUPPORT_SYNC BIT(9)
arm_tpiu_swo.c:65
#define TPIU_DEVID_SUPPORT_MANCHESTER BIT(10)
arm_tpiu_swo.c:66
#define TPIU_DEVID_SUPPORT_UART BIT(11)
arm_tpiu_swo.c:712
if (!(value & BIT(obj->port_width - 1))) {
arm_tpiu_swo.c:783
retval = wrap_write_u32(target, obj->ap, obj->spot.base + TPIU_CSPSR_OFFSET, BIT(obj->port_width - 1));
arm_tpiu_swo.c:799
value |= BIT(1);
arm_tpiu_swo.c:801
value &= ~BIT(1);
armv8_dpm.h:91
#define ECR_RCE BIT(1)
armv8_dpm.h:94
#define ESR_RC BIT(1)
chromium-ec.c:168
if (tasks_enabled & BIT(t))
chromium-ec.c:266
if (!(tasks_enabled & BIT(t)))
chromium-ec.c:320
tasks_ready & BIT(t) ? "Ready" : "Waiting", t,
cmsis_dap.c:93
#define INFO_CAPS_SWD BIT(0)
cmsis_dap.c:94
#define INFO_CAPS_JTAG BIT(1)
cmsis_dap.c:95
#define INFO_CAPS_SWO_UART BIT(2)
cmsis_dap.c:96
#define INFO_CAPS_SWO_MANCHESTER BIT(3)
cmsis_dap.c:198
#define DAP_SWO_STATUS_CAPTURE_MASK BIT(0)
cmsis_dap.c:1173
if (caps & BIT(i))
cortex_a.c:1739
byte_address_select = BIT(watchpoint->address & 0x3);
cortex_m.c:2371
if (dwt_function & BIT(24)) {
cortex_m.h:27
#define ITM_TCR_ITMENA_BIT BIT(0)
cortex_m.h:28
#define ITM_TCR_BUSY_BIT BIT(23)
cortex_m.h:67
#define CORTEX_M_F_HAS_FPV4 BIT(0)
cortex_m.h:68
#define CORTEX_M_F_HAS_FPV5 BIT(1)
cortex_m.h:69
#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
cortex_m.h:88
#define DCRSR_WNR BIT(16)
cortex_m.h:130
#define C_DEBUGEN BIT(0)
cortex_m.h:131
#define C_HALT BIT(1)
cortex_m.h:132
#define C_STEP BIT(2)
cortex_m.h:133
#define C_MASKINTS BIT(3)
cortex_m.h:134
#define S_REGRDY BIT(16)
cortex_m.h:135
#define S_HALT BIT(17)
cortex_m.h:136
#define S_SLEEP BIT(18)
cortex_m.h:137
#define S_LOCKUP BIT(19)
cortex_m.h:138
#define S_RETIRE_ST BIT(24)
cortex_m.h:139
#define S_RESET_ST BIT(25)
cortex_m.h:142
#define TRCENA BIT(24)
cortex_m.h:143
#define VC_HARDERR BIT(10)
cortex_m.h:144
#define VC_INTERR BIT(9)
cortex_m.h:145
#define VC_BUSERR BIT(8)
cortex_m.h:146
#define VC_STATERR BIT(7)
cortex_m.h:147
#define VC_CHKERR BIT(6)
cortex_m.h:148
#define VC_NOCPERR BIT(5)
cortex_m.h:149
#define VC_MMERR BIT(4)
cortex_m.h:150
#define VC_CORERESET BIT(0)
cortex_m.h:154
#define DSCSR_CDS BIT(16)
cortex_m.h:175
#define AIRCR_SYSRESETREQ BIT(2)
cortex_m.h:177
#define AIRCR_VECTRESET BIT(0)
eCos.c:76
SLEEPING = BIT(0),
eCos.c:77
COUNTSLEEP = BIT(1),
eCos.c:78
SUSPENDED = BIT(2),
eCos.c:79
CREATING = BIT(3),
eCos.c:80
EXITED = BIT(4),
eneispif.c:25
#define ISPISTS_BUSY BIT(0)
esp32_apptrace.c:39
#define ESP32_APPTRACE_USER_BLOCK_LEN(_v_) ((_v_) & ~BIT(15))
esp32s2.c:48
#define ESP32_S2_SWD_AUTO_FEED_EN_M BIT(31)
esp32s2.c:262
BIT(ESP32_S2_SW_SYS_RST_S));
esp32s3.c:54
#define ESP32_S3_SWD_AUTO_FEED_EN_M BIT(31)
esp_xtensa_apptrace.c:37
#define XTENSA_APPTRACE_HOST_DATA BIT(22)
esp_xtensa_apptrace.c:38
#define XTENSA_APPTRACE_HOST_CONNECT BIT(23)
esp_xtensa_apptrace.c:77
max_trace_block_sz = BIT(((trace_status.stat >> 8) & 0x1f) - 2) * 4;
gowin.c:35
#define STAUS_MASK_MEMORY_ERASE BIT(5)
gowin.c:36
#define STAUS_MASK_SYSTEM_EDIT_MODE BIT(7)
gowin.c:119
bit_file->crc_en = (value & BIT(23)) ? 1 : 0;
ipdbg.c:442
hub->dn_xoff |= BIT(hub->last_dn_tool);
ipdbg.c:581
while (((hub->dn_xoff & BIT(tool)) == 0) && !ipdbg_fifo_is_empty(&connection->dn_fifo)) {
ipdbg.c:582
if (hub->flow_control_enabled & BIT(tool))
ipdbg.c:1000
new_hub->valid_mask = BIT(data_register_length - 1);
ipdbg.c:1001
new_hub->xoff_mask = BIT(data_register_length - 2);
mips32.c:302
bool fpu_in_64bit = ((cp0_status & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
mips32.c:305
bool fp_enabled = ((cp0_status & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
mips32.c:1061
fpu_in_64bit = (status_value & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0;
mips32.c:1062
fp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0;
mips32.c:1384
uint32_t vz_present = (config3 & BIT(23));
mips32.c:2037
uint32_t vzase = (config3 & BIT(23));
mips32.c:2044
uint32_t mtase = (config3 & BIT(2));
mips32.c:2072
uint32_t msa = (config3 & BIT(28));
mips32.c:2077
uint32_t mvh = (config5 & BIT(5));
mips32.c:2081
uint32_t cdmm = (config3 & BIT(3));
mips32.c:2296
if (dcr & BIT(dcr_features[i].bit))
mips32.h:50
#define MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT)
mips32.h:56
#define MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT)
mips32.h:59
#define MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT)
mips32.h:62
#define MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT)
mips32.h:208
#define EJTAG_QUIRK_PAD_DRET BIT(0)
mips32_pracc.c:879
bool fpu_in_64bit = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
mips32_pracc.c:880
bool fp_enabled = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
mips32_pracc.c:1100
fp_enabled = (mips32->core_regs.cp0[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0;
mips_ejtag.h:126
#define EJTAG_DCR_ENM BIT(29)
mips_ejtag.h:127
#define EJTAG_DCR_FDC BIT(18)
mips_ejtag.h:128
#define EJTAG_DCR_DB BIT(17)
mips_ejtag.h:129
#define EJTAG_DCR_IB BIT(16)
mips_ejtag.h:130
#define EJTAG_DCR_INTE BIT(4)
mips_ejtag.h:131
#define EJTAG_DCR_MP BIT(2)
nrf5.c:78
NRF5_FEATURE_SERIES_51 = BIT(0),
nrf5.c:79
NRF5_FEATURE_SERIES_52 = BIT(1),
nrf5.c:80
NRF5_FEATURE_BPROT = BIT(2),
nrf5.c:81
NRF5_FEATURE_ACL_PROT = BIT(3),
nrf5.c:82
NRF5_FEATURE_SERIES_53 = BIT(4),
nrf5.c:83
NRF5_FEATURE_SERIES_91 = BIT(5),
nrf5.c:84
NRF5_FEATURE_ERASE_BY_FLASH_WR = BIT(6),
qn908x.c:95
#define QN908X_FMC_INI_RD_EN_INI_RD_EN_MASK BIT(0)
qn908x.c:97
#define QN908X_FMC_STATUS1_FSH_ERA_BUSY_L_MASK BIT(9)
qn908x.c:98
#define QN908X_FMC_STATUS1_FSH_WR_BUSY_L_MASK BIT(10)
qn908x.c:99
#define QN908X_FMC_STATUS1_FSH_ERA_BUSY_H_MASK BIT(12)
qn908x.c:100
#define QN908X_FMC_STATUS1_FSH_WR_BUSY_H_MASK BIT(13)
qn908x.c:101
#define QN908X_FMC_STATUS1_INI_RD_DONE_MASK BIT(15)
qn908x.c:102
#define QN908X_FMC_STATUS1_FSH_STA_MASK BIT(26)
qn908x.c:111
#define QN908X_FMC_INT_STAT_AHBL_INT_MASK BIT(0)
qn908x.c:112
#define QN908X_FMC_INT_STAT_LOCKL_INT_MASK BIT(1)
qn908x.c:116
#define QN908X_FMC_INT_STAT_WRITE_FAIL_L_INT_MASK BIT(5)
qn908x.c:117
#define QN908X_FMC_INT_STAT_ERASE_FAIL_L_INT_MASK BIT(6)
qn908x.c:124
#define QN908X_FMC_INT_STAT_ERASE_FAIL_H_INT_MASK BIT(14)
qn908x.c:126
#define QN908X_FMC_SMART_CTRL_PRGML_EN_MASK BIT(0)
qn908x.c:127
#define QN908X_FMC_SMART_CTRL_PRGMH_EN_MASK BIT(1)
qn908x.c:128
#define QN908X_FMC_SMART_CTRL_SMART_WRITEL_EN_MASK BIT(2)
qn908x.c:129
#define QN908X_FMC_SMART_CTRL_SMART_WRITEH_EN_MASK BIT(3)
qn908x.c:130
#define QN908X_FMC_SMART_CTRL_SMART_ERASEL_EN_MASK BIT(4)
qn908x.c:131
#define QN908X_FMC_SMART_CTRL_SMART_ERASEH_EN_MASK BIT(5)
qn908x.c:157
#define QN908X_FMC_LOCK_STAT_8_MASS_ERASE_LOCK_EN BIT(0)
qn908x.c:160
#define QN908X_FMC_LOCK_STAT_8_PROTECT_ANY (BIT(1) | BIT(2))
qn908x.c:165
#define QN908X_FLASH_LOCK_ENABLE_MASS_ERASE BIT(0)
qn908x.c:189
#define QN908X_SYSCON_CLK_EN_CLK_DP_EN_MASK BIT(21)
qn908x.c:191
#define SYSCON_XTAL_CTRL_XTAL_DIV_MASK BIT(31)
qn908x.c:195
#define SYSCON_CLK_CTRL_CLK_XTAL_SEL_MASK BIT(19)
qn908x.c:196
#define SYSCON_CLK_CTRL_CLK_OSC32M_DIV_MASK BIT(20)
qn908x.c:560
BIT(ctrl_erase_en_shift) | (page_idx << ctrl_page_idx_shift));
renesas_rpchf.c:24
#define RPC_CMNCR_MD BIT(31)
renesas_rpchf.c:46
#define RPC_DRCR_RCF BIT(9)
renesas_rpchf.c:47
#define RPC_DRCR_RBE BIT(8)
renesas_rpchf.c:71
#define RPC_DRENR_CDE BIT(14)
renesas_rpchf.c:72
#define RPC_DRENR_OCDE BIT(12)
renesas_rpchf.c:78
#define RPC_SMCR_SPIRE BIT(2)
renesas_rpchf.c:79
#define RPC_SMCR_SPIWE BIT(1)
renesas_rpchf.c:80
#define RPC_SMCR_SPIE BIT(0)
renesas_rpchf.c:99
#define RPC_SMENR_DME BIT(15)
renesas_rpchf.c:100
#define RPC_SMENR_CDE BIT(14)
renesas_rpchf.c:101
#define RPC_SMENR_OCDE BIT(12)
renesas_rpchf.c:112
#define RPC_CMNSR_TEND BIT(0)
renesas_rpchf.c:119
#define RPC_DRDRENR_ADDRE BIT(8)
renesas_rpchf.c:121
#define RPC_DRDRENR_DRDRE BIT(0)
renesas_rpchf.c:128
#define RPC_SMDRENR_ADDRE BIT(8)
renesas_rpchf.c:130
#define RPC_SMDRENR_SPIDRE BIT(0)
renesas_rpchf.c:133
#define RPC_PHYCNT_CAL BIT(31)
renesas_rpchf.c:138
#define RPC_PHYCNT_WBUF2 BIT(4)
renesas_rpchf.c:139
#define RPC_PHYCNT_WBUF BIT(2)
riscv.c:558
!!(r->misa & BIT('U' - 'A')));
riscv.c:560
!!(r->misa & BIT('S' - 'A')));
riscv.c:562
!!(r->misa & BIT('H' - 'A')));
riscv.c:3204
return r->misa & BIT(num);
rsl10.c:55
#define RSL10_FLASH_REG_NVR_CTRL_NVR1_W_ENABLE BIT(1)
rsl10.c:56
#define RSL10_FLASH_REG_NVR_CTRL_NVR2_W_ENABLE BIT(2)
rsl10.c:57
#define RSL10_FLASH_REG_NVR_CTRL_NVR3_W_ENABLE BIT(3)
rsl10.c:62
#define RSL10_FLASH_REG_STATUS_NVR1_W_UNLOCKED BIT(4)
rsl10.c:63
#define RSL10_FLASH_REG_STATUS_NVR2_W_UNLOCKED BIT(5)
rsl10.c:64
#define RSL10_FLASH_REG_STATUS_NVR3_W_UNLOCKED BIT(6)
rtkernel.c:22
#define ST_DEAD BIT(0) /* Task is waiting to be deleted */
rtkernel.c:23
#define ST_WAIT BIT(1) /* Task is blocked: */
rtkernel.c:24
#define ST_SEM BIT(2) /* on semaphore */
rtkernel.c:25
#define ST_MTX BIT(3) /* on mutex */
rtkernel.c:26
#define ST_SIG BIT(4) /* on signal */
rtkernel.c:27
#define ST_DLY BIT(5) /* on timer */
rtkernel.c:28
#define ST_FLAG BIT(6) /* on flag */
rtkernel.c:29
#define ST_FLAG_ALL BIT(7) /* on flag and flag mode is "ALL" */
rtkernel.c:30
#define ST_MBOX BIT(8) /* on mailbox */
rtkernel.c:31
#define ST_STP BIT(9) /* self stopped */
rtkernel.c:32
#define ST_SUSPEND BIT(10) /* Task is suspended */
rtkernel.c:33
#define ST_TT BIT(11) /* Time triggered task */
rtkernel.c:34
#define ST_TT_YIELD BIT(12) /* Time triggered task that yields */
sh_qspi.c:37
#define SPCMD_SCKDEN BIT(15)
sh_qspi.c:38
#define SPCMD_SLNDEN BIT(14)
sh_qspi.c:39
#define SPCMD_SPNDEN BIT(13)
sh_qspi.c:40
#define SPCMD_SSLKP BIT(7)
sh_qspi.c:41
#define SPCMD_BRDV0 BIT(2)
sh_qspi.c:47
#define SPBFCR_TXRST BIT(7)
sh_qspi.c:48
#define SPBFCR_RXRST BIT(6)
stlink_usb.c:506
#define STLINK_F_HAS_TRACE BIT(0) /* v2>=j13 || v3 */
stlink_usb.c:507
#define STLINK_F_HAS_GETLASTRWSTATUS2 BIT(1) /* v2>=j15 || v3 */
stlink_usb.c:508
#define STLINK_F_HAS_SWD_SET_FREQ BIT(2) /* v2>=j22 */
stlink_usb.c:509
#define STLINK_F_HAS_JTAG_SET_FREQ BIT(3) /* v2>=j24 */
stlink_usb.c:510
#define STLINK_F_QUIRK_JTAG_DP_READ BIT(4) /* v2>=j24 && v2<j32 */
stlink_usb.c:511
#define STLINK_F_HAS_DAP_REG BIT(5) /* v2>=j24 || v3 */
stlink_usb.c:512
#define STLINK_F_HAS_MEM_16BIT BIT(6) /* v2>=j26 || v3 */
stlink_usb.c:513
#define STLINK_F_HAS_AP_INIT BIT(7) /* v2>=j28 || v3 */
stlink_usb.c:514
#define STLINK_F_FIX_CLOSE_AP BIT(8) /* v2>=j29 || v3 */
stlink_usb.c:515
#define STLINK_F_HAS_DPBANKSEL BIT(9) /* v2>=j32 || v3>=j2 */
stlink_usb.c:516
#define STLINK_F_HAS_RW8_512BYTES BIT(10) /* v3>=j6 */
stm32l4x.c:138
#define F_HAS_DUAL_BANK BIT(0)
stm32l4x.c:141
#define F_USE_ALL_WRPXX BIT(1)
stm32l4x.c:143
#define F_HAS_TZ BIT(2)
stm32l4x.c:145
#define F_HAS_L5_FLASH_REGS BIT(3)
stm32l4x.c:148
#define F_QUAD_WORD_PROG BIT(4)
stm32l4x.h:17
#ifndef BIT
stm32l4x.h:22
#define FLASH_PG BIT(0)
stm32l4x.h:23
#define FLASH_PER BIT(1)
stm32l4x.h:24
#define FLASH_MER1 BIT(2)
stm32l4x.h:26
#define FLASH_BKER BIT(11)
stm32l4x.h:27
#define FLASH_BKER_G0 BIT(13)
stm32l4x.h:28
#define FLASH_MER2 BIT(15)
stm32l4x.h:29
#define FLASH_STRT BIT(16)
stm32l4x.h:30
#define FLASH_OPTSTRT BIT(17)
stm32l4x.h:33
#define FLASH_OBL_LAUNCH BIT(27)
stm32l4x.h:34
#define FLASH_OPTLOCK BIT(30)
stm32l4x.h:35
#define FLASH_LOCK BIT(31)
stm32l4x.h:38
#define FLASH_BSY BIT(16)
stm32l4x.h:39
#define FLASH_BSY2 BIT(17)
stm32l4x.h:42
#define FLASH_PGSERR BIT(7) /* Programming sequence error */
stm32l4x.h:43
#define FLASH_SIZERR BIT(6) /* Size error */
stm32l4x.h:44
#define FLASH_PGAERR BIT(5) /* Programming alignment error */
stm32l4x.h:45
#define FLASH_WRPERR BIT(4) /* Write protection error */
stm32l4x.h:46
#define FLASH_PROGERR BIT(3) /* Programming error */
stm32l4x.h:47
#define FLASH_OPERR BIT(1) /* Operation error */
stm32l4x.h:62
#define FLASH_G0_DUAL_BANK BIT(21)
stm32l4x.h:63
#define FLASH_G4_DUAL_BANK BIT(22)
stm32l4x.h:64
#define FLASH_L4_DUAL_BANK BIT(21)
stm32l4x.h:65
#define FLASH_L4R_DBANK BIT(22)
stm32l4x.h:66
#define FLASH_LRR_DB1M BIT(21)
stm32l4x.h:67
#define FLASH_L5_DBANK BIT(22)
stm32l4x.h:68
#define FLASH_L5_DB256 BIT(21)
stm32l4x.h:69
#define FLASH_U5_DUALBANK BIT(21)
stm32l4x.h:70
#define FLASH_TZEN BIT(31)
stmqspi.c:249
if ((spi_sr & BIT(SPI_BUSY)) == 0) {
stmqspi.c:251
return target_write_u32(target, io_base + SPI_FCR, BIT(SPI_TCF));
stmqspi.c:273
return target_write_u32(target, io_base + SPI_CR, cr | BIT(SPI_ABORT));
stmqspi.c:344
((stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 2 * count : count) - 1);
stmqspi.c:370
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
stmqspi.c:371
!= BIT(SPI_FSEL_FLASH)) {
stmqspi.c:379
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
stmqspi.c:464
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
stmqspi.c:465
!= BIT(SPI_FSEL_FLASH))
stmqspi.c:474
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0)
stmqspi.c:557
if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
stmqspi.c:558
!= BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
stmqspi.c:568
if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
stmqspi.c:601
if (word == BIT(result))
stmqspi.c:629
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:725
fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
stmqspi.c:728
if (bank->size == BIT(fsize + 1))
stmqspi.c:730
else if (bank->size == BIT(fsize + 0))
stmqspi.c:811
if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
stmqspi.c:819
if (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) {
stmqspi.c:964
if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
stmqspi.c:965
!= BIT(SPI_FSEL_FLASH)) && ((status & SPIFLASH_BSY_BIT) == 0) &&
stmqspi.c:976
if (((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) &&
stmqspi.c:1281
pagesize = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? pagesize << 1 : pagesize;
stmqspi.c:1384
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:1619
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:1620
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
stmqspi.c:1680
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:1681
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
stmqspi.c:1725
bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
stmqspi.c:1729
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:1736
stmqspi_info->saved_cr | BIT(SPI_ABORT));
stmqspi.c:1815
bool flash1 = !(stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH));
stmqspi.c:1819
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:1837
dummy = (stmqspi_info->saved_cr & BIT(SPI_FSEL_FLASH)) ?
stmqspi.c:1856
stmqspi_info->saved_cr | BIT(SPI_ABORT));
stmqspi.c:1974
(stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH) ? count * 2 : count) - 1);
stmqspi.c:2017
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
stmqspi.c:2018
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
stmqspi.c:2028
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
stmqspi.c:2029
BIT(SPI_FSEL_FLASH))) != 0) {
stmqspi.c:2046
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
stmqspi.c:2047
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) {
stmqspi.c:2055
if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH))) != 0) {
stmqspi.c:2180
dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
stmqspi.c:2181
octal_dtr = IS_OCTOSPI && (stmqspi_info->saved_ccr & BIT(OCTOSPI_DDTR));
stmqspi.c:2220
stmqspi_info->saved_cr = stmqspi_info->saved_cr & ~BIT(SPI_FSEL_FLASH);
stmqspi.c:2278
stmqspi_info->saved_cr = stmqspi_info->saved_cr | BIT(SPI_FSEL_FLASH);
stmqspi.c:2323
fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
stmqspi.c:2326
if (bank->size == BIT((fsize + 1)))
stmqspi.c:2328
else if (bank->size == BIT((fsize + 0)))
stmqspi.c:2396
((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
stmqspi.c:2397
BIT(SPI_FSEL_FLASH))) != BIT(SPI_FSEL_FLASH)) ? "1" : "",
stmqspi.c:2398
((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) |
stmqspi.c:2399
BIT(SPI_FSEL_FLASH))) != 0) ? "2" : "",
stmqspi.h:43
#define QSPI_DCYC_MASK ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)
stmqspi.h:84
#define OCTOSPI_MTYP_MASK ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)
stmqspi.h:96
#define OCTOSPI_NO_DDTR (~BIT(OCTOSPI_DDTR)) /* no DTR for data, but maybe still DQS */
stmqspi.h:102
#define OCTOSPI_DCYC_MASK ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)
xtensa.c:645
if ((flags & XT_REGF_COPROC0) && (cpenable & BIT(0)) == 0)
xtensa.c:1643
bpena |= BIT(slot);
xtensa.c:2677
dbreakcval |= BIT(30);
xtensa.c:2679
dbreakcval |= BIT(31);
xtensa.c:2681
dbreakcval |= BIT(30) | BIT(31);
xtensa.h:44
#define XT_PS_WOE_MSK BIT(18)
xtensa.h:47
#define XT_PS_DIEXC_MSK BIT(2)
xtensa_debug_module.h:49
#define PWRCTL_JTAGDEBUGUSE(x) (((x)->dbg_mod.dap) ? (0) : BIT(7))
xtensa_debug_module.h:51
#define PWRCTL_CORERESET(x) (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
xtensa_debug_module.h:52
#define PWRCTL_DEBUGWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
xtensa_debug_module.h:53
#define PWRCTL_MEMWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(8) : BIT(1))
xtensa_debug_module.h:54
#define PWRCTL_COREWAKEUP(x) (((x)->dbg_mod.dap) ? BIT(0) : BIT(0))
xtensa_debug_module.h:56
#define PWRSTAT_DEBUGWASRESET_DM(d) (((d)->dap) ? BIT(28) : BIT(6))
xtensa_debug_module.h:57
#define PWRSTAT_COREWASRESET_DM(d) (((d)->dap) ? BIT(16) : BIT(4))
xtensa_debug_module.h:280
#define OCDDCR_ENABLEOCD BIT(0)
xtensa_debug_module.h:281
#define OCDDCR_DEBUGINTERRUPT BIT(1)
xtensa_debug_module.h:283
#define OCDDCR_STEPREQUEST BIT(3) /* NX only */
xtensa_debug_module.h:284
#define OCDDCR_BREAKINEN BIT(16)
xtensa_debug_module.h:285
#define OCDDCR_BREAKOUTEN BIT(17)
xtensa_debug_module.h:286
#define OCDDCR_DEBUGSWACTIVE BIT(20)
xtensa_debug_module.h:287
#define OCDDCR_RUNSTALLINEN BIT(21)
xtensa_debug_module.h:288
#define OCDDCR_DEBUGMODEOUTEN BIT(22)
xtensa_debug_module.h:293
#define OCDDSR_EXECEXCEPTION BIT(1)
xtensa_debug_module.h:294
#define OCDDSR_EXECBUSY BIT(2)
xtensa_debug_module.h:295
#define OCDDSR_EXECOVERRUN BIT(3)
xtensa_debug_module.h:296
#define OCDDSR_STOPPED BIT(4)
xtensa_debug_module.h:303
#define OCDDSR_DEBUGPENDBREAK BIT(16)
xtensa_debug_module.h:304
#define OCDDSR_DEBUGPENDHOST BIT(17)
xtensa_debug_module.h:305
#define OCDDSR_DEBUGPENDTRAX BIT(18)
xtensa_debug_module.h:306
#define OCDDSR_DEBUGINTBREAK BIT(20)
xtensa_debug_module.h:307
#define OCDDSR_DEBUGINTHOST BIT(21)
xtensa_debug_module.h:308
#define OCDDSR_DEBUGINTTRAX BIT(22)
xtensa_debug_module.h:310
#define OCDDSR_RUNSTALLSAMPLE BIT(24)
xtensa_debug_module.h:313
#define OCDDSR_DBGMODPOWERON BIT(31)
xtensa_debug_module.h:326
#define DEBUGCAUSE_IC BIT(0) /* ICOUNT exception */
xtensa_debug_module.h:327
#define DEBUGCAUSE_IB BIT(1) /* IBREAK exception */
xtensa_debug_module.h:328
#define DEBUGCAUSE_DB BIT(2) /* DBREAK exception */
xtensa_debug_module.h:329
#define DEBUGCAUSE_BI BIT(3) /* BREAK instruction encountered */
xtensa_debug_module.h:330
#define DEBUGCAUSE_BN BIT(4) /* BREAK.N instruction encountered */
xtensa_debug_module.h:331
#define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */
xtensa_debug_module.h:332
#define DEBUGCAUSE_VALID BIT(31) /* Pseudo-value to trigger reread (NX only) */
xtensa_debug_module.h:339
#define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */
xtensa_debug_module.h:340
#define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */
xtensa_debug_module.h:341
#define TRAXCTRL_PCMEN BIT(2) /* PC match enable */
xtensa_debug_module.h:344
#define TRAXCTRL_TMEN BIT(7) /* Tracemem Enable. Always set. */
xtensa_debug_module.h:345
#define TRAXCTRL_CNTU BIT(9) /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
xtensa_debug_module.h:350
#define TRAXCTRL_PTOWT BIT(16) /* Processor Trigger Out (OCD halt) enabled when stop triggered */
xtensa_debug_module.h:351
#define TRAXCTRL_PTOWS BIT(17) /* Processor Trigger Out (OCD halt) enabled when trace stop completes */
xtensa_debug_module.h:361
#define TRAXSTAT_TRACT BIT(0) /* Trace active flag. */
xtensa_debug_module.h:363
#define TRAXSTAT_PCMTG BIT(2) /* Stop trigger caused by PC match. Clears on TREN 1->0 */
xtensa_debug_module.h:365
#define TRAXSTAT_PTITG BIT(4) /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */
xtensa_debug_module.h:366
#define TRAXSTAT_CTITG BIT(5) /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */
xtensa_debug_module.h:379
#define TRAXADDR_TWSAT BIT(31) /* 1 if TWRAP has overflown, clear by disabling tren.*/