/* SPDX-License-Identifier: GPL-2.0-or-later *//*************************************************************************** * Copyright (C) 2016 - 2018 by Andreas Bolsch * * andreas.bolsch@mni.thm.de * ***************************************************************************//* ... */#ifndefOPENOCD_FLASH_NOR_STMQSPI_H#defineOPENOCD_FLASH_NOR_STMQSPI_H#include"spi.h"/* QSPI register offsets */#defineQSPI_CR(0x00)/* Control register */#defineQSPI_DCR(0x04)/* Device configuration register */#defineQSPI_SR(0x08)/* Status register */#defineQSPI_FCR(0x0C)/* Flag clear register */#defineQSPI_DLR(0x10)/* Data length register */#defineQSPI_CCR(0x14)/* Communication configuration register */#defineQSPI_AR(0x18)/* Address register */#defineQSPI_ABR(0x1C)/* Alternate bytes register */#defineQSPI_DR(0x20)/* Data register *//* common bits in QSPI_CR and OCTOSPI_CR */#defineSPI_FSEL_FLASH7/* Select flash 2 */#defineSPI_DUAL_FLASH6/* Dual flash mode */#defineSPI_ABORT1/* Abort bit *//* common bits in QSPI_DCR and OCTOSPI_DCR1 */#defineSPI_FSIZE_POS16/* bit position of FSIZE */#defineSPI_FSIZE_LEN5/* width of FSIZE field *//* common bits in QSPI_SR/FCR and OCTOSPI_SR/FCR */#defineSPI_BUSY5/* Busy flag */#defineSPI_FTF2/* FIFO threshold flag */#defineSPI_TCF1/* Transfer complete flag *//* fields in QSPI_CCR */#defineQSPI_DDRM31/* position of DDRM bit */#defineSPI_DMODE_POS24/* bit position of DMODE */#defineQSPI_DCYC_POS18/* bit position of DCYC */#defineQSPI_DCYC_LEN5/* width of DCYC field */#defineQSPI_DCYC_MASK((BIT(QSPI_DCYC_LEN)-1)<<QSPI_DCYC_POS)#defineSPI_ADSIZE_POS12/* bit position of ADSIZE */#defineQSPI_WRITE_MODE0x00000000U/* indirect write mode */#defineQSPI_READ_MODE0x04000000U/* indirect read mode */#defineQSPI_MM_MODE0x0C000000U/* memory mapped mode */#defineQSPI_ALTB_MODE0x0003C000U/* alternate byte mode */#defineQSPI_4LINE_MODE0x03000F00U/* 4 lines for data, addr, instr */#defineQSPI_NO_DATA(~0x03000000U)/* no data */#defineQSPI_NO_ALTB(~QSPI_ALTB_MODE)/* no alternate */#defineQSPI_NO_ADDR(~0x00000C00U)/* no address */#defineQSPI_ADDR3(0x2U<<SPI_ADSIZE_POS)/* 3 byte address */#defineQSPI_ADDR4(0x3U<<SPI_ADSIZE_POS)/* 4 byte address *//* OCTOSPI register offsets */#defineOCTOSPI_CR(0x000)/* Control register */#defineOCTOSPI_DCR1(0x008)/* Device configuration register 1 */#defineOCTOSPI_DCR2(0x00C)/* Device configuration register 2 */#defineOCTOSPI_DCR3(0x010)/* Device configuration register 3 */#defineOCTOSPI_SR(0x020)/* Status register */#defineOCTOSPI_FCR(0x024)/* Flag clear register */#defineOCTOSPI_DLR(0x040)/* Data length register */#defineOCTOSPI_AR(0x048)/* Address register */#defineOCTOSPI_DR(0x050)/* Data register */#defineOCTOSPI_CCR(0x100)/* Communication configuration register */#defineOCTOSPI_TCR(0x108)/* Timing configuration register */#defineOCTOSPI_IR(0x110)/* Instruction register */#defineOCTOSPI_WCCR(0x180)/* Write communication configuration register */#defineOCTOSPI_WIR(0x190)/* Write instruction register */#defineOCTOSPI_MAGIC(0x3FC)/* Magic ID register, deleted from RM, why? */#defineOCTO_MAGIC_ID0xA3C5DD01/* Magic ID, deleted from RM, why? *//* additional bits in OCTOSPI_CR */#defineOCTOSPI_WRITE_MODE0x00000000U/* indirect write mode */#defineOCTOSPI_READ_MODE0x10000000U/* indirect read mode */#defineOCTOSPI_MM_MODE0x30000000U/* memory mapped mode *//* additional fields in OCTOSPI_DCR1 */#defineOCTOSPI_MTYP_POS(24)/* bit position of MTYP */#defineOCTOSPI_MTYP_LEN(3)/* width of MTYP field */#defineOCTOSPI_MTYP_MASK((BIT(OCTOSPI_MTYP_LEN)-1)<<OCTOSPI_MTYP_POS)/* fields in OCTOSPI_CCR */#defineOCTOSPI_ALTB_MODE0x001F0000U/* alternate byte mode */#defineOCTOSPI_8LINE_MODE0x0F003F3FU/* 8 lines DTR for data, addr, instr */#defineOCTOSPI_NO_DATA(~0x0F000000U)/* no data */#defineOCTOSPI_NO_ALTB(~OCTOSPI_ALTB_MODE)/* no alternate */#defineOCTOSPI_NO_ADDR(~0x00000F00U)/* no address */#defineOCTOSPI_ADDR3(0x2U<<SPI_ADSIZE_POS)/* 3 byte address */#defineOCTOSPI_ADDR4(0x3U<<SPI_ADSIZE_POS)/* 4 byte address */#defineOCTOSPI_DQSEN29/* DQS enable */#defineOCTOSPI_DDTR27/* DTR for data */#defineOCTOSPI_NO_DDTR(~BIT(OCTOSPI_DDTR))/* no DTR for data, but maybe still DQS */#defineOCTOSPI_ISIZE_MASK(0x30)/* ISIZE field *//* fields in OCTOSPI_TCR */#defineOCTOSPI_DCYC_POS0/* bit position of DCYC */#defineOCTOSPI_DCYC_LEN5/* width of DCYC field */#defineOCTOSPI_DCYC_MASK((BIT(OCTOSPI_DCYC_LEN)-1)<<OCTOSPI_DCYC_POS)#defineIS_OCTOSPI(stmqspi_info->octo)#defineSPI_CR(IS_OCTOSPI?OCTOSPI_CR:QSPI_CR)#defineSPI_DCR(IS_OCTOSPI?OCTOSPI_DCR1:QSPI_DCR)#defineSPI_SR(IS_OCTOSPI?OCTOSPI_SR:QSPI_SR)#defineSPI_FCR(IS_OCTOSPI?OCTOSPI_FCR:QSPI_FCR)#defineSPI_DLR(IS_OCTOSPI?OCTOSPI_DLR:QSPI_DLR)#defineSPI_AR(IS_OCTOSPI?OCTOSPI_AR:QSPI_AR)#defineSPI_DR(IS_OCTOSPI?OCTOSPI_DR:QSPI_DR)#defineSPI_CCR(IS_OCTOSPI?OCTOSPI_CCR:QSPI_CCR)78 defines/* ... */#endif/* OPENOCD_FLASH_NOR_STMQSPI_H */