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CodeScopeSTM32 Libraries and SamplesHALRCC_PLLSAIInitTypeDef::PLLSAIP

RCC_PLLSAIInitTypeDef::PLLSAIP field

Specifies division factor for OTG FS and SDIO clocks. This parameter is only available in STM32F469xx/STM32F479xx devices. This parameter must be a value of RCCEx_PLLSAIP_Clock_Divider

Syntax

uint32_t PLLSAIP;

Examples

RCC_PLLSAIInitTypeDef::PLLSAIP is referenced by 61 libraries and example projects.

References

LocationReferrerText
stm32f4xx_hal_rcc_ex.h:110
uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
stm32f4xx_hal_rcc_ex.h:321
uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
stm32f4xx_hal_rcc_ex.c:456HAL_RCCEx_PeriphCLKConfig()
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
stm32f4xx_hal_rcc_ex.c:462HAL_RCCEx_PeriphCLKConfig()
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
stm32f4xx_hal_rcc_ex.c:510HAL_RCCEx_GetPeriphCLKConfig()
PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
stm32f4xx_hal_rcc_ex.c:1057HAL_RCCEx_PeriphCLKConfig()
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
stm32f4xx_hal_rcc_ex.c:1066HAL_RCCEx_PeriphCLKConfig()
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
stm32f4xx_hal_rcc_ex.c:2951HAL_RCCEx_EnablePLLSAI()
assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
stm32f4xx_hal_rcc_ex.c:2978HAL_RCCEx_EnablePLLSAI()
PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
stm32f4xx_hal_rcc_ex.c:2984HAL_RCCEx_EnablePLLSAI()
__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \

Data Use

Functions writing RCC_PLLSAIInitTypeDef::PLLSAIP
Functions reading RCC_PLLSAIInitTypeDef::PLLSAIP
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RCC_PLLSAIInitTypeDef::PLLSAIP
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Type of RCC_PLLSAIInitTypeDef::PLLSAIP
RCC_PLLSAIInitTypeDef::PLLSAIP
uint32_t
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