__HAL_RCC_PLLSAI_CONFIG - syntax, references, description

Syntax

#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))

Arguments

PLLSAIM

specifies the division factor for PLLSAI VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

PLLSAIN

specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.

PLLSAIP

specifies division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number in the range {2, 4, 6, or 8}.

PLLSAIQ

specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.

PLLSAIR

specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Notes

You have to set the PLLSAIM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 1 MHz to limit PLLI2S jitter. The PLLSAIM parameter is only used with STM32F446xx Devices You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz. the PLLSAIP parameter is only available with STM32F446xx Devices the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices

References

Location	Text
stm32f4xx_hal_rcc_ex.h:6064	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
stm32f4xx_hal_rcc_ex.h:6088	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
stm32f4xx_hal_rcc_ex.h:6110	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
stm32f4xx_hal_rcc_ex.c:445	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
stm32f4xx_hal_rcc_ex.c:462	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
stm32f4xx_hal_rcc_ex.c:1029	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
stm32f4xx_hal_rcc_ex.c:1047	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
stm32f4xx_hal_rcc_ex.c:1066	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
stm32f4xx_hal_rcc_ex.c:2309	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
stm32f4xx_hal_rcc_ex.c:2325	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
stm32f4xx_hal_rcc_ex.c:2977	__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
stm32f4xx_hal_rcc_ex.c:2984	__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
stm32f4xx_hal_rcc_ex.c:2990	__HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);

__HAL_RCC_PLLSAI_CONFIG macro

Syntax

Arguments

__PLLSAIM__

__PLLSAIN__

__PLLSAIP__

__PLLSAIQ__