HAL + 0/22 examples
CodeScope will show references to QSPI_HandleTypeDef::Instance from the following samples and libraries:
 
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CodeScopeSTM32 Libraries and SamplesHALQSPI_HandleTypeDef::Instance

QSPI_HandleTypeDef::Instance field

Syntax

QUADSPI_TypeDef *Instance;

Examples

QSPI_HandleTypeDef::Instance is referenced by 22 libraries and example projects.

References

LocationReferrerText
stm32f4xx_hal_qspi.h:98
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
stm32f4xx_hal_qspi.c:304HAL_QSPI_Init()
assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
stm32f4xx_hal_qspi.c:353HAL_QSPI_Init()
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
stm32f4xx_hal_qspi.c:362HAL_QSPI_Init()
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
stm32f4xx_hal_qspi.c:367HAL_QSPI_Init()
MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
stm32f4xx_hal_qspi.c:372HAL_QSPI_Init()
__HAL_QSPI_ENABLE(hqspi);
stm32f4xx_hal_qspi.c:402HAL_QSPI_DeInit()
__HAL_QSPI_DISABLE(hqspi);
stm32f4xx_hal_qspi.c:491HAL_QSPI_IRQHandler()
uint32_t flag = READ_REG(hqspi->Instance->SR);
stm32f4xx_hal_qspi.c:492HAL_QSPI_IRQHandler()
uint32_t itsource = READ_REG(hqspi->Instance->CR);
stm32f4xx_hal_qspi.c:497HAL_QSPI_IRQHandler()
data_reg = &hqspi->Instance->DR;
stm32f4xx_hal_qspi.c:502HAL_QSPI_IRQHandler()
while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
stm32f4xx_hal_qspi.c:515HAL_QSPI_IRQHandler()
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
stm32f4xx_hal_qspi.c:523HAL_QSPI_IRQHandler()
while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
stm32f4xx_hal_qspi.c:536HAL_QSPI_IRQHandler()
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
stm32f4xx_hal_qspi.c:558HAL_QSPI_IRQHandler()
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:561HAL_QSPI_IRQHandler()
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
stm32f4xx_hal_qspi.c:566HAL_QSPI_IRQHandler()
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
stm32f4xx_hal_qspi.c:569HAL_QSPI_IRQHandler()
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:590HAL_QSPI_IRQHandler()
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
stm32f4xx_hal_qspi.c:593HAL_QSPI_IRQHandler()
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:600HAL_QSPI_IRQHandler()
data_reg = &hqspi->Instance->DR;
stm32f4xx_hal_qspi.c:601HAL_QSPI_IRQHandler()
while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
stm32f4xx_hal_qspi.c:646HAL_QSPI_IRQHandler()
CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
stm32f4xx_hal_qspi.c:684HAL_QSPI_IRQHandler()
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
stm32f4xx_hal_qspi.c:687HAL_QSPI_IRQHandler()
if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
stm32f4xx_hal_qspi.c:690HAL_QSPI_IRQHandler()
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
stm32f4xx_hal_qspi.c:708HAL_QSPI_IRQHandler()
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
stm32f4xx_hal_qspi.c:711HAL_QSPI_IRQHandler()
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
stm32f4xx_hal_qspi.c:716HAL_QSPI_IRQHandler()
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
stm32f4xx_hal_qspi.c:719HAL_QSPI_IRQHandler()
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:757HAL_QSPI_IRQHandler()
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
stm32f4xx_hal_qspi.c:838HAL_QSPI_Command()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:918HAL_QSPI_Command_IT()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:932HAL_QSPI_Command_IT()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
stm32f4xx_hal_qspi.c:973HAL_QSPI_Transmit()
__IO uint32_t *data_reg = &hqspi->Instance->DR;
stm32f4xx_hal_qspi.c:988HAL_QSPI_Transmit()
hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:989HAL_QSPI_Transmit()
hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:993HAL_QSPI_Transmit()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
stm32f4xx_hal_qspi.c:1018HAL_QSPI_Transmit()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:1058HAL_QSPI_Receive()
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
stm32f4xx_hal_qspi.c:1059HAL_QSPI_Receive()
__IO uint32_t *data_reg = &hqspi->Instance->DR;
stm32f4xx_hal_qspi.c:1074HAL_QSPI_Receive()
hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:1075HAL_QSPI_Receive()
hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:1079HAL_QSPI_Receive()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
stm32f4xx_hal_qspi.c:1082HAL_QSPI_Receive()
WRITE_REG(hqspi->Instance->AR, addr_reg);
stm32f4xx_hal_qspi.c:1107HAL_QSPI_Receive()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:1158HAL_QSPI_Transmit_IT()
hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:1159HAL_QSPI_Transmit_IT()
hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:1163HAL_QSPI_Transmit_IT()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:1166HAL_QSPI_Transmit_IT()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
stm32f4xx_hal_qspi.c:1172HAL_QSPI_Transmit_IT()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
stm32f4xx_hal_qspi.c:1204HAL_QSPI_Receive_IT()
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
stm32f4xx_hal_qspi.c:1219HAL_QSPI_Receive_IT()
hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:1220HAL_QSPI_Receive_IT()
hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
stm32f4xx_hal_qspi.c:1224HAL_QSPI_Receive_IT()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:1227HAL_QSPI_Receive_IT()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
stm32f4xx_hal_qspi.c:1230HAL_QSPI_Receive_IT()
WRITE_REG(hqspi->Instance->AR, addr_reg);
stm32f4xx_hal_qspi.c:1236HAL_QSPI_Receive_IT()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
stm32f4xx_hal_qspi.c:1272HAL_QSPI_Transmit_DMA()
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
stm32f4xx_hal_qspi.c:1334HAL_QSPI_Transmit_DMA()
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
stm32f4xx_hal_qspi.c:1341HAL_QSPI_Transmit_DMA()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
stm32f4xx_hal_qspi.c:1383HAL_QSPI_Transmit_DMA()
if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
stm32f4xx_hal_qspi.c:1389HAL_QSPI_Transmit_DMA()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
stm32f4xx_hal_qspi.c:1392HAL_QSPI_Transmit_DMA()
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:1439HAL_QSPI_Receive_DMA()
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
stm32f4xx_hal_qspi.c:1440HAL_QSPI_Receive_DMA()
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
stm32f4xx_hal_qspi.c:1502HAL_QSPI_Receive_DMA()
__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
stm32f4xx_hal_qspi.c:1544HAL_QSPI_Receive_DMA()
WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
stm32f4xx_hal_qspi.c:1550HAL_QSPI_Receive_DMA()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
stm32f4xx_hal_qspi.c:1553HAL_QSPI_Receive_DMA()
WRITE_REG(hqspi->Instance->AR, addr_reg);
stm32f4xx_hal_qspi.c:1556HAL_QSPI_Receive_DMA()
if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
stm32f4xx_hal_qspi.c:1559HAL_QSPI_Receive_DMA()
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:1565HAL_QSPI_Receive_DMA()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
stm32f4xx_hal_qspi.c:1584HAL_QSPI_Receive_DMA()
if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK)
stm32f4xx_hal_qspi.c:1587HAL_QSPI_Receive_DMA()
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
stm32f4xx_hal_qspi.c:1590HAL_QSPI_Receive_DMA()
WRITE_REG(hqspi->Instance->AR, addr_reg);
stm32f4xx_hal_qspi.c:1596HAL_QSPI_Receive_DMA()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
stm32f4xx_hal_qspi.c:1599HAL_QSPI_Receive_DMA()
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:1693HAL_QSPI_AutoPolling()
WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
stm32f4xx_hal_qspi.c:1696HAL_QSPI_AutoPolling()
WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
stm32f4xx_hal_qspi.c:1699HAL_QSPI_AutoPolling()
WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
stm32f4xx_hal_qspi.c:1703HAL_QSPI_AutoPolling()
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
stm32f4xx_hal_qspi.c:1715HAL_QSPI_AutoPolling()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
stm32f4xx_hal_qspi.c:1793HAL_QSPI_AutoPolling_IT()
WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
stm32f4xx_hal_qspi.c:1796HAL_QSPI_AutoPolling_IT()
WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
stm32f4xx_hal_qspi.c:1799HAL_QSPI_AutoPolling_IT()
WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
stm32f4xx_hal_qspi.c:1802HAL_QSPI_AutoPolling_IT()
MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
stm32f4xx_hal_qspi.c:1806HAL_QSPI_AutoPolling_IT()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
stm32f4xx_hal_qspi.c:1816HAL_QSPI_AutoPolling_IT()
__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
stm32f4xx_hal_qspi.c:1894HAL_QSPI_MemoryMapped()
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
stm32f4xx_hal_qspi.c:1901HAL_QSPI_MemoryMapped()
WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
stm32f4xx_hal_qspi.c:1904HAL_QSPI_MemoryMapped()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
stm32f4xx_hal_qspi.c:1907HAL_QSPI_MemoryMapped()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
stm32f4xx_hal_qspi.c:2356HAL_QSPI_Abort()
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
stm32f4xx_hal_qspi.c:2359HAL_QSPI_Abort()
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:2369HAL_QSPI_Abort()
if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
stm32f4xx_hal_qspi.c:2372HAL_QSPI_Abort()
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
stm32f4xx_hal_qspi.c:2379HAL_QSPI_Abort()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:2388HAL_QSPI_Abort()
CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
stm32f4xx_hal_qspi.c:2423HAL_QSPI_Abort_IT()
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
stm32f4xx_hal_qspi.c:2425HAL_QSPI_Abort_IT()
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
stm32f4xx_hal_qspi.c:2428HAL_QSPI_Abort_IT()
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:2447HAL_QSPI_Abort_IT()
if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
stm32f4xx_hal_qspi.c:2450HAL_QSPI_Abort_IT()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:2453HAL_QSPI_Abort_IT()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
stm32f4xx_hal_qspi.c:2456HAL_QSPI_Abort_IT()
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
stm32f4xx_hal_qspi.c:2496HAL_QSPI_SetFifoThreshold()
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
stm32f4xx_hal_qspi.c:2517HAL_QSPI_GetFifoThreshold()
return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
stm32f4xx_hal_qspi.c:2543HAL_QSPI_SetFlashID()
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
stm32f4xx_hal_qspi.c:2580QSPI_DMARxCplt()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
stm32f4xx_hal_qspi.c:2594QSPI_DMATxCplt()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
stm32f4xx_hal_qspi.c:2646QSPI_DMAError()
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
stm32f4xx_hal_qspi.c:2670QSPI_DMAAbortCplt()
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
stm32f4xx_hal_qspi.c:2673QSPI_DMAAbortCplt()
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
stm32f4xx_hal_qspi.c:2676QSPI_DMAAbortCplt()
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
stm32f4xx_hal_qspi.c:2706QSPI_WaitFlagStateUntilTimeout()
while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
stm32f4xx_hal_qspi.c:2743QSPI_WaitFlagStateUntilTimeout_CPUCycle()
while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State);
stm32f4xx_hal_qspi.c:2767QSPI_Config()
WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
stm32f4xx_hal_qspi.c:2775QSPI_Config()
WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
stm32f4xx_hal_qspi.c:2781QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2790QSPI_Config()
WRITE_REG(hqspi->Instance->AR, cmd->Address);
stm32f4xx_hal_qspi.c:2797QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2810QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2818QSPI_Config()
WRITE_REG(hqspi->Instance->AR, cmd->Address);
stm32f4xx_hal_qspi.c:2825QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2837QSPI_Config()
WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
stm32f4xx_hal_qspi.c:2843QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2852QSPI_Config()
WRITE_REG(hqspi->Instance->AR, cmd->Address);
stm32f4xx_hal_qspi.c:2859QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2871QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
stm32f4xx_hal_qspi.c:2879QSPI_Config()
WRITE_REG(hqspi->Instance->AR, cmd->Address);
stm32f4xx_hal_qspi.c:2888QSPI_Config()
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |

Data Use

Type of QSPI_HandleTypeDef::Instance
QSPI_HandleTypeDef::Instance
all items filtered out