OpenOCD
log_levels::LOG_LVL_USER is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDlog_levels::LOG_LVL_USER

log_levels::LOG_LVL_USER

Syntax

LOG_LVL_USER = -1;

References

LocationReferrerText
log.h:43
LOG_LVL_USER = -1,
arm11.c:347arm11_arch_state()
LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr);
arm720t.c:234arm720t_arch_state()
LOG_USER("MMU: %s, Cache: %s",
arm7_9_common.c:2823arm7_9_setup_semihosting()
LOG_USER("current target isn't an ARM7/ARM9 target");
arm920t.c:525arm920t_arch_state()
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
arm926ejs.c:518arm926ejs_arch_state()
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
arm_tpiu_swo.c:187arm_tpiu_swo_handle_event()
LOG_USER("Error executing event %s on TPIU/SWO %s:\n%s",
armv4_5.c:795arm_arch_state()
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
armv7a.c:71armv7a_show_fault_registers()
LOG_USER("Data fault registers DFSR: %8.8" PRIx32
armv7a.c:73armv7a_show_fault_registers()
LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
armv7a.c:548armv7a_arch_state()
LOG_USER("D-Cache: %s, I-Cache: %s",
armv7a.c:552armv7a_arch_state()
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
armv7a_mmu.c:234armv7a_mmu_dump_table()
LOG_USER("Page Directory at (phys): %8.8" TARGET_PRIxADDR, ttb);
armv7a_mmu.c:273armv7a_mmu_dump_table()
LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
armv7a_mmu.c:286armv7a_mmu_dump_table()
LOG_USER("SSCT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
armv7a_mmu.c:323armv7a_mmu_dump_table()
LOG_USER("LPGE: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
armv7a_mmu.c:336armv7a_mmu_dump_table()
LOG_USER("SPGE: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
armv7m.c:741armv7m_arch_state()
LOG_USER("[%s] halted due to %s, current mode: %s %s\n"
armv8.c:1007armv8_show_fault_registers32()
LOG_USER("Data fault registers DFSR: %8.8" PRIx32
armv8.c:1009armv8_show_fault_registers32()
LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
armv8.c:1033armv8_decode_cacheability()
LOG_USER_N("UNPREDICTABLE");
armv8.c:1037armv8_decode_cacheability()
LOG_USER_N("Non-cacheable");
armv8.c:1042armv8_decode_cacheability()
LOG_USER_N("Write-Through Transient");
armv8.c:1045armv8_decode_cacheability()
LOG_USER_N("Write-Back Transient");
armv8.c:1048armv8_decode_cacheability()
LOG_USER_N("Write-Through Non-transient");
armv8.c:1051armv8_decode_cacheability()
LOG_USER_N("Write-Back Non-transient");
armv8.c:1055armv8_decode_cacheability()
LOG_USER_N(" Read-Allocate");
armv8.c:1057armv8_decode_cacheability()
LOG_USER_N(" No-Read Allocate");
armv8.c:1059armv8_decode_cacheability()
LOG_USER_N(" Write-Allocate");
armv8.c:1061armv8_decode_cacheability()
LOG_USER_N(" No-Write Allocate");
armv8.c:1067armv8_decode_memory_attr()
LOG_USER("Normal Memory, Inner Non-cacheable, "
armv8.c:1070armv8_decode_memory_attr()
LOG_USER("Normal Memory, Inner Write-through Cacheable, "
armv8.c:1074armv8_decode_memory_attr()
LOG_USER("Tagged Normal Memory, Inner Write-Back, "
armv8.c:1080armv8_decode_memory_attr()
LOG_USER_N("Device-nGnRnE Memory");
armv8.c:1083armv8_decode_memory_attr()
LOG_USER_N("Device-nGnRE Memory");
armv8.c:1086armv8_decode_memory_attr()
LOG_USER_N("Device-nGRE Memory");
armv8.c:1089armv8_decode_memory_attr()
LOG_USER_N("Device-GRE Memory");
armv8.c:1093armv8_decode_memory_attr()
LOG_USER(", XS=0");
armv8.c:1095armv8_decode_memory_attr()
LOG_USER_N("\n");
armv8.c:1097armv8_decode_memory_attr()
LOG_USER_N("Normal Memory, Inner ");
armv8.c:1099armv8_decode_memory_attr()
LOG_USER_N(", Outer ");
armv8.c:1101armv8_decode_memory_attr()
LOG_USER_N("\n");
armv8.c:1187armv8_mmu_translate_va_pa()
LOG_USER("%sshareable, %s",
armv8.c:1316armv8_aarch64_state()
LOG_USER("%s halted in %s state due to %s, current mode: %s\n"
armv8.c:1348armv8_arch_state()
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
armv8.c:1357armv8_arch_state()
LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
at91sam3.c:2427sam3_reg_fieldname()
LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
at91sam3.c:2563sam3_explain_ckgr_mor()
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
at91sam3.c:2565sam3_explain_ckgr_mor()
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
at91sam3.c:2567sam3_explain_ckgr_mor()
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
at91sam3.c:2569sam3_explain_ckgr_mor()
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
at91sam3.c:2590sam3_explain_ckgr_mor()
LOG_USER("(startup clks, time= %f uSecs)",
at91sam3.c:2593sam3_explain_ckgr_mor()
LOG_USER("(mainosc source: %s)",
at91sam3.c:2597sam3_explain_ckgr_mor()
LOG_USER("(clock failure enabled: %s)",
at91sam3.c:2608sam3_explain_chipid_cidr()
LOG_USER_N("\n");
at91sam3.c:2611sam3_explain_chipid_cidr()
LOG_USER("%s", eproc_names[v]);
at91sam3.c:2614sam3_explain_chipid_cidr()
LOG_USER("%s", nvpsize[v]);
at91sam3.c:2617sam3_explain_chipid_cidr()
LOG_USER("%s", nvpsize2[v]);
at91sam3.c:2620sam3_explain_chipid_cidr()
LOG_USER("%s", sramsize[v]);
at91sam3.c:2631sam3_explain_chipid_cidr()
LOG_USER("%s", cp);
at91sam3.c:2634sam3_explain_chipid_cidr()
LOG_USER("%s", nvptype[v]);
at91sam3.c:2637sam3_explain_chipid_cidr()
LOG_USER("(exists: %s)", _yes_or_no(v));
at91sam3.c:2645sam3_explain_ckgr_mcfr()
LOG_USER("(main ready: %s)", _yes_or_no(v));
at91sam3.c:2652sam3_explain_ckgr_mcfr()
LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
at91sam3.c:2663sam3_explain_ckgr_plla()
LOG_USER_N("\n");
at91sam3.c:2665sam3_explain_ckgr_plla()
LOG_USER_N("\n");
at91sam3.c:2668sam3_explain_ckgr_plla()
LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
at91sam3.c:2670sam3_explain_ckgr_plla()
LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
at91sam3.c:2673sam3_explain_ckgr_plla()
LOG_USER("\tPLLA Freq: %3.03f MHz",
at91sam3.c:2712sam3_explain_mckr()
LOG_USER("%s (%3.03f Mhz)",
at91sam3.c:2753sam3_explain_mckr()
LOG_USER("(%s)", cp);
at91sam3.c:2760sam3_explain_mckr()
LOG_USER("\t\tResult CPU Freq: %3.03f",
at91sam3.c:2925sam3_get_info()
LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
at91sam3.c:2935sam3_get_info()
LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
at91sam3.c:2936sam3_get_info()
LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
at91sam3.c:2937sam3_get_info()
LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
at91sam3.c:2938sam3_get_info()
LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
at91sam3.c:2939sam3_get_info()
LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
at91sam3.c:2941sam3_get_info()
LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
at91sam4.c:1927sam4_reg_fieldname()
LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
at91sam4.c:2072sam4_explain_ckgr_mor()
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
at91sam4.c:2074sam4_explain_ckgr_mor()
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
at91sam4.c:2076sam4_explain_ckgr_mor()
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
at91sam4.c:2078sam4_explain_ckgr_mor()
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
at91sam4.c:2099sam4_explain_ckgr_mor()
LOG_USER("(startup clks, time= %f uSecs)",
at91sam4.c:2102sam4_explain_ckgr_mor()
LOG_USER("(mainosc source: %s)",
at91sam4.c:2106sam4_explain_ckgr_mor()
LOG_USER("(clock failure enabled: %s)",
at91sam4.c:2117sam4_explain_chipid_cidr()
LOG_USER_N("\n");
at91sam4.c:2120sam4_explain_chipid_cidr()
LOG_USER("%s", eproc_names[v]);
at91sam4.c:2123sam4_explain_chipid_cidr()
LOG_USER("%s", nvpsize[v]);
at91sam4.c:2126sam4_explain_chipid_cidr()
LOG_USER("%s", nvpsize2[v]);
at91sam4.c:2129sam4_explain_chipid_cidr()
LOG_USER("%s", sramsize[v]);
at91sam4.c:2140sam4_explain_chipid_cidr()
LOG_USER("%s", cp);
at91sam4.c:2143sam4_explain_chipid_cidr()
LOG_USER("%s", nvptype[v]);
at91sam4.c:2146sam4_explain_chipid_cidr()
LOG_USER("(exists: %s)", _yes_or_no(v));
at91sam4.c:2154sam4_explain_ckgr_mcfr()
LOG_USER("(main ready: %s)", _yes_or_no(v));
at91sam4.c:2161sam4_explain_ckgr_mcfr()
LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
at91sam4.c:2172sam4_explain_ckgr_plla()
LOG_USER_N("\n");
at91sam4.c:2174sam4_explain_ckgr_plla()
LOG_USER_N("\n");
at91sam4.c:2177sam4_explain_ckgr_plla()
LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
at91sam4.c:2179sam4_explain_ckgr_plla()
LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
at91sam4.c:2182sam4_explain_ckgr_plla()
LOG_USER("\tPLLA Freq: %3.03f MHz",
at91sam4.c:2221sam4_explain_mckr()
LOG_USER("%s (%3.03f Mhz)",
at91sam4.c:2262sam4_explain_mckr()
LOG_USER("(%s)", cp);
at91sam4.c:2269sam4_explain_mckr()
LOG_USER("\t\tResult CPU Freq: %3.03f",
at91sam4.c:2418sam4_get_info()
LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
at91sam4.c:2428sam4_get_info()
LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
at91sam4.c:2429sam4_get_info()
LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
at91sam4.c:2430sam4_get_info()
LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
at91sam4.c:2431sam4_get_info()
LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
at91sam4.c:2432sam4_get_info()
LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
at91sam4.c:2434sam4_get_info()
LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
avr32_ap7k.c:551avr32_ap7k_arch_state()
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
cfi.c:2633cfi_probe()
LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
command.c:601command_run_line()
LOG_USER("%s", Jim_GetString(Jim_GetResult(interp), NULL));
command.c:671handle_echo()
LOG_USER_N("%s", CMD_ARGV[1]);
command.c:678handle_echo()
LOG_USER("%s", CMD_ARGV[0]);
command.c:734command_help_show_indent()
LOG_USER_N(" ");
command.c:750command_help_show_wrap()
LOG_USER("%.*s", (int)(cp - last), last);
command.c:1236command_init()
LOG_USER_N("%s", Jim_GetString(Jim_GetResult(interp), NULL));
core.c:422default_flash_blank_check()
LOG_USER("Running slow fallback erase check");
core.c:424default_flash_blank_check()
LOG_USER("Running slow fallback erase check - add working memory");
dsp5680xx.c:853eonce_pc_store()
LOG_USER("PC value: 0x%X%X\n", tmp[1], tmp[0]);
dsp5680xx.c:880dsp5680xx_arch_state()
LOG_USER("%s not implemented yet.", __func__);
dsp5680xx.c:904dsp5680xx_halt()
LOG_USER("Target already halted and in debug mode.");
dsp5680xx.c:908dsp5680xx_halt()
LOG_USER
dsp5680xx.c:1000dsp5680xx_resume()
LOG_USER("Target already running.");
dsp5680xx.c:1199dsp5680xx_read()
LOG_USER("%s: Invalid read size.", __func__);
dsp5680xx_flash.c:45dsp5680xx_build_sector_list()
LOG_USER("%s not tested yet.", __func__);
esirisc.c:1244esirisc_arch_state()
LOG_USER("target halted due to %s, exception: %s\n"
esp32_apptrace.c:144esp32_apptrace_console_dest_write()
LOG_USER_N("%.*s", size, data);
esp32_apptrace.c:588esp32_apptrace_cmd_init()
LOG_USER("App trace params: from %d cores, size %" PRId32 " bytes, stop_tmo %g s, poll period %" PRId32
esp32_apptrace.c:625esp32_apptrace_print_stats()
LOG_USER("Tracing is %s. Size is %" PRId32 " of %" PRId32 " @ %f (%f) KiB/s",
esp32_apptrace.c:631esp32_apptrace_print_stats()
LOG_USER("Data: blocks incomplete %" PRId32 ", lost bytes: %" PRId32,
esp32_apptrace.c:635esp32_apptrace_print_stats()
LOG_USER("Block read time [%f..%f] ms",
esp32_apptrace.c:638esp32_apptrace_print_stats()
LOG_USER("Block proc time [%f..%f] ms",
esp32_apptrace.c:646esp32_apptrace_wait4halt()
LOG_USER("Wait for halt...");
esp32_apptrace.c:652esp32_apptrace_wait4halt()
LOG_USER("%s: HALTED", target->cmd_name);
esp32_apptrace.c:760esp32_apptrace_connect_targets()
LOG_USER("Connect targets...");
esp32_apptrace.c:762esp32_apptrace_connect_targets()
LOG_USER("Disconnect targets...");
esp32_apptrace.c:904esp32_apptrace_process_data()
LOG_USER("%" PRId32 " ", ctx->tot_len);
esp32_sysview.c:86esp32_sysview_cmd_init()
LOG_USER("App trace params: from %d cores, size %u bytes, stop_tmo %g s, "
esp32_sysview.c:543esp32_sysview_process_data()
LOG_USER("%u ", ctx->tot_len);
gdb_server.c:171gdb_last_signal()
LOG_USER("undefined debug reason %d (%s) - target needs reset",
gdb_server.c:768gdb_output()
LOG_USER_N("%s", line);
gdb_server.c:4062handle_gdb_breakpoint_override_command()
LOG_USER("force %s breakpoints",
gdb_server.c:4065handle_gdb_breakpoint_override_command()
LOG_USER("breakpoint type is not overridden");
lakemont.c:469exit_probemode()
LOG_USER("core not in PM");
lakemont.c:591do_resume()
LOG_USER("target running");
lakemont.c:903lakemont_poll()
LOG_USER("hit hardware breakpoint (hwreg=%" PRIu32 ") at 0x%08" PRIx32, hwbreakpoint, eip);
lakemont.c:921lakemont_poll()
LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%" PRIu32 ") at 0x%08" PRIx32,
lakemont.c:941lakemont_poll()
LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
lakemont.c:946lakemont_poll()
LOG_USER("hit unknown breakpoint at 0x%08" PRIx32, eip);
lakemont.c:955lakemont_poll()
LOG_USER("unknown break reason at 0x%08" PRIx32, eip);
lakemont.c:970lakemont_arch_state()
LOG_USER("target halted due to %s at 0x%08" PRIx32 " in %s mode",
lakemont.c:1026lakemont_resume()
LOG_USER("target not halted");
lakemont.c:1083lakemont_step()
LOG_USER("step done from EIP 0x%08" PRIx32 " to 0x%08" PRIx32, eip,
log.c:124log_puts()
(level > LOG_LVL_USER) ? log_strings[level + 1] : "", string);
mips32.c:464mips32_arch_state()
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
mips32.c:1035mips32_read_config_dsp()
LOG_USER("DSP implemented: %s, rev %d", "yes", mips32->dsp_imp);
mips32.c:1037mips32_read_config_dsp()
LOG_USER("DSP implemented: %s", "no");
mips32.c:1048mips32_read_config_fpu()
LOG_USER("FPU implemented: %s", "no");
mips32.c:1090mips32_read_config_fpu()
LOG_USER("FPU implemented: %s", buf);
mips32.c:1157mips32_read_config_regs()
LOG_USER("ISA implemented: %s%s", "MIPS32, MIPS16", buf);
mips32.c:1162mips32_read_config_regs()
LOG_USER("ISA implemented: %s%s", "microMIPS32", buf);
mips32.c:1166mips32_read_config_regs()
LOG_USER("ISA implemented: %s%s", "MIPS32, microMIPS32", buf);
mips32.c:1170mips32_read_config_regs()
LOG_USER("ISA implemented: %s%s", "MIPS32", buf);
mips32.c:1408mips32_read_config_mmu()
LOG_USER("TLB Entries: %d (%d ways, %d sets per way)", tlb_entries, ways, sets);
mips64.c:364mips64_arch_state()
LOG_USER("target halted due to %s, pc: 0x%" PRIx64 "",
mips_m4k.h:41mips_m4k_isa_filter()
LOG_USER("Warning: isa bit changed due to isa not implemented");
options.c:53configuration_output_handler()
LOG_USER_N("%s", line);
riscv-011.c:1894handle_halt()
LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
riscv-011.c:2110read_memory()
LOG_USER("Core got an exception (0x%x) while reading from 0x%"
riscv-011.c:2113read_memory()
LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
server.c:760handle_shutdown_command()
LOG_USER("shutdown command invoked");
stm8.c:1288stm8_arch_state()
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
svf.c:475handle_svf_command()
LOG_USER("svf processing file: \"%s\"", CMD_ARGV[i]);
svf.c:577handle_svf_command()
LOG_USER_N("\r%d%% ", svf_percentage);
svf.c:584handle_svf_command()
LOG_USER_N("%3d%% %s", svf_percentage, svf_read_line);
svf.c:586handle_svf_command()
LOG_USER_N("%s", svf_read_line);
svf.c:1604svf_run_command()
LOG_USER("(Above Padding command skipped, as per -tap argument)");
target_request.c:57target_charmsg()
LOG_USER_N("%c", msg);
tcl.c:556jtag_tap_handle_event()
LOG_USER("%s", Jim_GetString(Jim_GetResult(jteap->interp), NULL));
tcl.c:1084handle_wait_srst_deassert()
LOG_USER("Waiting for srst assert + deassert for at most %dms", timeout_ms);
x86_32_common.c:990set_hwbp()
LOG_USER("%s hardware breakpoint %" PRIu32 " set at 0x%08" PRIx32 " (hwreg=%" PRIu8 ")", __func__,
x86_32_common.c:1012unset_hwbp()
LOG_USER("%s hardware breakpoint %" PRIu32 " removed from " TARGET_ADDR_FMT " (hwreg=%d)",
x86_32_common.c:1068set_swbp()
LOG_USER("%s software breakpoint %" PRIu32 " set at " TARGET_ADDR_FMT,
x86_32_common.c:1116unset_swbp()
LOG_USER("%s software breakpoint %" PRIu32 " removed from " TARGET_ADDR_FMT,
x86_32_common.c:1228set_watchpoint()
LOG_USER("'%s' watchpoint %d set at " TARGET_ADDR_FMT " with length %" PRIu32 " (hwreg=%d)",
x86_32_common.c:1257unset_watchpoint()
LOG_USER("'%s' watchpoint %d removed from " TARGET_ADDR_FMT " with length %" PRIu32 " (hwreg=%d)",
xscale.c:791xscale_arch_state()
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
xscale.c:815xscale_poll()
LOG_USER("error while polling TX register, reset CPU");
xsvf.c:265handle_xsvf_command()
LOG_USER("xsvf processing file: \"%s\"", filename);
xsvf.c:469handle_xsvf_command()
LOG_USER("%s mismatch, xsdrsize=%d retry=%d",
xsvf.c:500handle_xsvf_command()
LOG_USER("%s mismatch", op_name);
xsvf.c:733handle_xsvf_command()
LOG_USER("# %s", comment);
xsvf.c:920handle_xsvf_command()
LOG_USER("LSDR retry %d", attempt);
xsvf.c:944handle_xsvf_command()
LOG_USER("LSDR mismatch");

Data Use

Functions using log_levels::LOG_LVL_USER
log_levels::LOG_LVL_USER
all items filtered out