OpenOCD
arm_state
is only used within OpenOCD.
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OpenOCD
arm_state
arm_state enum
The PSR "T" and "J" bits define the mode of "classic ARM" cores.
Syntax
from
arm.h:150
enum
arm_state
{
ARM_STATE_ARM
,
ARM_STATE_THUMB
,
ARM_STATE_JAZELLE
,
ARM_STATE_THUMB_EE
,
ARM_STATE_AARCH64
,
}
;
Values
ARM_STATE_ARM
No summary provided.
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ARM_STATE_THUMB
No summary provided.
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ARM_STATE_JAZELLE
No summary provided.
Read more...
ARM_STATE_THUMB_EE
No summary provided.
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ARM_STATE_AARCH64
No summary provided.
Read more...
References
Location
Referrer
Scope
Text
arm.h:150
enum
arm_state
{
aarch64.c:964
aarch64_debug_entry()
enum
arm_state
core_state
;
arm.h:199
arm::core_state
arm
enum
arm_state
core_state
;
arm.h:277
arm_algorithm::core_state
arm_algorithm
enum
arm_state
core_state
;
arm_simulator.c:674
armv4_5_get_state()
static
enum
arm_state
armv4_5_get_state
(
struct
arm_sim_interface
*
sim
)
arm_simulator.c:681
armv4_5_set_state()
static
void
armv4_5_set_state
(
struct
arm_sim_interface
*
sim
,
enum
arm_state
mode
)
arm_simulator.h:20
arm_sim_interface::get_state
arm_sim_interface
enum
arm_state
(
*
get_state
)
(
struct
arm_sim_interface
*
sim
)
;
arm_simulator.h:21
arm_sim_interface::set_state::mode
void
(
*
set_state
)
(
struct
arm_sim_interface
*
sim
,
enum
arm_state
mode
)
;
armv4_5.c:468
arm_set_cpsr()
enum
arm_state
state
;
armv4_5.c:1399
armv4_5_run_algorithm_inner()
enum
arm_state
core_state
=
arm
->
core_state
;
armv8.c:939
armv8_set_cpsr()
enum
arm_state
state
=
0xFF
;
armv8_dpm.c:41
armv8_dpm_get_core_state()
enum
arm_state
armv8_dpm_get_core_state
(
struct
arm_dpm
*
dpm
)
armv8_dpm.c:544
armv8_dpm_modeswitch()
enum
arm_state
core_state
;
armv8_dpm.c:1300
armv8_dpm_handle_exception()
enum
arm_state
core_state
;
armv8_dpm.h:117
armv8_dpm_get_core_state()
enum
arm_state
armv8_dpm_get_core_state
(
struct
arm_dpm
*
dpm
)
;
feroceon.c:457
feroceon_bulk_write_memory()
enum
arm_state
core_state
=
arm
->
core_state
;
xscale.h:70
xscale_trace::core_state
xscale_trace
enum
arm_state
core_state
;
/* current core state (ARM, Thumb) */
Type Use
Variables of
arm_state
type
arm::core_state
arm_algorithm::core_state
arm_sim_interface::get_state
arm_sim_interface::set_state::mode
arm_set_cpsr()
arm_set_cpsr()::state
armv4_5_run_algorithm_inner()
armv4_5_run_algorithm_inner()::core_state
armv8_set_cpsr()
armv8_set_cpsr()::state
armv8_dpm_get_core_state()
armv8_dpm_modeswitch()
armv8_dpm_modeswitch()::core_state
armv8_dpm_handle_exception()
armv8_dpm_handle_exception()::core_state
armv4_5_get_state()
armv4_5_set_state()::mode
feroceon_bulk_write_memory()
feroceon_bulk_write_memory()::core_state
xscale_trace::core_state
aarch64_debug_entry()
aarch64_debug_entry()::core_state
all items filtered out
arm_state
Allocators of
arm_state
Deletors of
arm_state
arm_set_cpsr()::state
armv4_5_run_algorithm_inner()::core_state
armv8_set_cpsr()::state
armv8_dpm_modeswitch()::core_state
armv8_dpm_handle_exception()::core_state
armv4_5_set_state()::mode
feroceon_bulk_write_memory()::core_state
aarch64_debug_entry()::core_state
all items filtered out
arm_state
arm_set_cpsr()::state
armv4_5_run_algorithm_inner()::core_state
armv8_set_cpsr()::state
armv8_dpm_modeswitch()::core_state
armv8_dpm_handle_exception()::core_state
armv4_5_set_state()::mode
feroceon_bulk_write_memory()::core_state
aarch64_debug_entry()::core_state
all items filtered out