OpenOCD
arm_state::ARM_STATE_ARM is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDarm_state::ARM_STATE_ARM

arm_state::ARM_STATE_ARM

Syntax

ARM_STATE_ARM;

References

LocationReferrerText
arm.h:151
ARM_STATE_ARM,
aarch64.c:602aarch64_restore_one()
case ARM_STATE_ARM:
aduc702x.c:206aduc702x_write_block()
arm_algo.core_state = ARM_STATE_ARM;
arm11.c:417arm11_nextpc()
case ARM_STATE_ARM:
arm7_9_common.c:1289arm7_9_debug_entry()
arm->core_state = ARM_STATE_ARM;
arm7_9_common.c:1321arm7_9_debug_entry()
} else if (arm->core_state == ARM_STATE_ARM) {
arm7_9_common.c:1327arm7_9_debug_entry()
context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
arm7_9_common.c:1330arm7_9_debug_entry()
((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
arm7_9_common.c:1761arm7_9_resume()
if (arm->core_state == ARM_STATE_ARM)
arm7_9_common.c:1807arm7_9_resume()
if (arm->core_state == ARM_STATE_ARM)
arm7_9_common.c:1950arm7_9_step()
if (arm->core_state == ARM_STATE_ARM)
arm7_9_common.c:2626arm7_9_bulk_write_memory()
arm_algo.core_state = ARM_STATE_ARM;
arm_dpm.c:232arm_dpm_read_reg()
case ARM_STATE_ARM:
arm_dpm.c:1036arm_dpm_report_wfar()
case ARM_STATE_ARM:
arm_io.c:134arm_nandwrite()
armv4_5_algo.core_state = ARM_STATE_ARM;
arm_io.c:244arm_nandread()
armv4_5_algo.core_state = ARM_STATE_ARM;
arm_semihosting.c:115post_result()
} else if (arm->core_state == ARM_STATE_ARM) {
arm_semihosting.c:305arm_semihosting()
} else if (arm->core_state == ARM_STATE_ARM) {
arm_simulator.c:93arm_shifter_operand()
if (sim->get_state(sim) == ARM_STATE_ARM)
arm_simulator.c:236arm_simulate_step_core()
if (sim->get_state(sim) == ARM_STATE_ARM) {
arm_simulator.c:323arm_simulate_step_core()
sim->set_state(sim, ARM_STATE_ARM);
arm_simulator.c:333arm_simulate_step_core()
sim->set_state(sim, ARM_STATE_ARM);
arm_simulator.c:403arm_simulate_step_core()
sim->set_state(sim, ARM_STATE_ARM);
arm_simulator.c:494arm_simulate_step_core()
sim->set_state(sim, ARM_STATE_ARM);
arm_simulator.c:556arm_simulate_step_core()
sim->set_state(sim, ARM_STATE_ARM);
armv4_5.c:481arm_set_cpsr()
state = ARM_STATE_ARM;
armv4_5.c:925handle_arm_core_state_command()
arm->core_state = ARM_STATE_ARM;
armv4_5.c:1475armv4_5_run_algorithm_inner()
if (arm->core_state == ARM_STATE_ARM)
armv4_5.c:1633arm_checksum_memory()
arm_algo.core_state = ARM_STATE_ARM;
armv4_5.c:1714arm_blank_check_memory()
arm_algo.core_state = ARM_STATE_ARM;
armv8.c:954armv8_set_cpsr()
state = ARM_STATE_ARM;
armv8_dpm.c:52armv8_dpm_get_core_state()
return ARM_STATE_ARM;
cfi.c:1200cfi_intel_write_block()
arm_algo.core_state = ARM_STATE_ARM;
cfi.c:1792cfi_spansion_write_block()
armv4_5_algo.core_state = ARM_STATE_ARM;
cortex_a.c:864cortex_a_internal_restore()
case ARM_STATE_ARM:
etm.c:657etm_read_instruction()
if (ctx->core_state == ARM_STATE_ARM) {
etm.c:813etmv1_branch_address()
ctx->core_state = ARM_STATE_ARM;
etm.c:1092etmv1_analyze_trace()
next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
etm.c:1094etmv1_analyze_trace()
next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
etm.c:1430handle_etm_config_command()
etm_ctx->core_state = ARM_STATE_ARM;
feroceon.c:526feroceon_bulk_write_memory()
arm->core_state = ARM_STATE_ARM;
lpc2000.c:750lpc2000_iap_call()
arm_algo.core_state = ARM_STATE_ARM;
lpc2900.c:1258lpc2900_write()
arm_algo.core_state = ARM_STATE_ARM;
sh_qspi.c:546sh_qspi_write()
arm_algo.core_state = ARM_STATE_ARM;
sh_qspi.c:617sh_qspi_read()
arm_algo.core_state = ARM_STATE_ARM;
str7x.c:495str7x_write_block()
arm_algo.core_state = ARM_STATE_ARM;
str9x.c:397str9x_write_block()
arm_algo.core_state = ARM_STATE_ARM;
xscale.c:2599xscale_read_instruction()
if (xscale->trace.core_state == ARM_STATE_ARM) {
xscale.c:2673xscale_analyze_trace()
xscale->trace.core_state = ARM_STATE_ARM;
xscale.c:2764xscale_analyze_trace()
current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
xscale.c:2772xscale_analyze_trace()
current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
xscale.c:2837xscale_analyze_trace()
(xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
xscale.c:2848xscale_analyze_trace()
current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;

Data Use