arm::core_state is only used within OpenOCD.
 
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arm::core_state field

Record the current core state: ARM, Thumb, or otherwise.

Syntax

enum arm_state core_state;

References

LocationReferrerText
arm.h:199
enum arm_state core_state;
aarch64.c:601aarch64_restore_one()
switch (arm->core_state) {
aarch64.c:2065aarch64_write_cpu_memory_slow()
if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
aarch64.c:2103aarch64_write_cpu_memory_slow()
if (arm->core_state == ARM_STATE_AARCH64)
aarch64.c:2205aarch64_write_cpu_memory()
if (arm->core_state == ARM_STATE_AARCH64) {
aarch64.c:2262aarch64_read_cpu_memory_slow()
if (size > 4 && arm->core_state != ARM_STATE_AARCH64) {
aarch64.c:2297aarch64_read_cpu_memory_slow()
if (arm->core_state == ARM_STATE_AARCH64)
aarch64.c:2350aarch64_read_cpu_memory_fast()
if (arm->core_state == ARM_STATE_AARCH64) {
aarch64.c:2426aarch64_read_cpu_memory()
if (arm->core_state != ARM_STATE_AARCH64 && !(size == 4 && (address % 4) == 0))
aarch64.c:2463aarch64_read_cpu_memory()
if (arm->core_state == ARM_STATE_AARCH64) {
aarch64.c:3097aarch64_mcrmrc_command()
if (arm->core_state == ARM_STATE_AARCH64) {
arm11.c:416arm11_nextpc()
switch (arm11->arm.core_state) {
arm7_9_common.c:1119arm7_9_soft_reset_halt()
arm->core_state = ARM_STATE_THUMB;
arm7_9_common.c:1271arm7_9_debug_entry()
arm->core_state = ARM_STATE_THUMB;
arm7_9_common.c:1283arm7_9_debug_entry()
arm->core_state = ARM_STATE_JAZELLE;
arm7_9_common.c:1289arm7_9_debug_entry()
arm->core_state = ARM_STATE_ARM;
arm7_9_common.c:1317arm7_9_debug_entry()
if (arm->core_state == ARM_STATE_THUMB) {
arm7_9_common.c:1321arm7_9_debug_entry()
} else if (arm->core_state == ARM_STATE_ARM) {
arm7_9_common.c:1327arm7_9_debug_entry()
context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
arm7_9_common.c:1330arm7_9_debug_entry()
((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
arm7_9_common.c:1761arm7_9_resume()
if (arm->core_state == ARM_STATE_ARM)
arm7_9_common.c:1763arm7_9_resume()
else if (arm->core_state == ARM_STATE_THUMB)
arm7_9_common.c:1807arm7_9_resume()
if (arm->core_state == ARM_STATE_ARM)
arm7_9_common.c:1809arm7_9_resume()
else if (arm->core_state == ARM_STATE_THUMB)
arm7_9_common.c:1950arm7_9_step()
if (arm->core_state == ARM_STATE_ARM)
arm7_9_common.c:1952arm7_9_step()
else if (arm->core_state == ARM_STATE_THUMB)
arm_dpm.c:231arm_dpm_read_reg()
switch (dpm->arm->core_state) {
arm_dpm.c:1035arm_dpm_report_wfar()
switch (dpm->arm->core_state) {
arm_semihosting.c:104post_result()
arm->core_state = ARM_STATE_THUMB;
arm_semihosting.c:107post_result()
if (arm->core_state == ARM_STATE_AARCH64) {
arm_semihosting.c:115post_result()
} else if (arm->core_state == ARM_STATE_ARM) {
arm_semihosting.c:123post_result()
} else if (arm->core_state == ARM_STATE_THUMB) {
arm_semihosting.c:293arm_semihosting()
if (arm->core_state == ARM_STATE_AARCH64) {
arm_semihosting.c:305arm_semihosting()
} else if (arm->core_state == ARM_STATE_ARM) {
arm_semihosting.c:320arm_semihosting()
} else if (arm->core_state == ARM_STATE_THUMB) {
arm_semihosting.c:346arm_semihosting()
arm->core_state == ARM_STATE_AARCH64) {
arm_simulator.c:678armv4_5_get_state()
return arm->core_state;
arm_simulator.c:685armv4_5_set_state()
arm->core_state = mode;
armv4_5.c:483arm_set_cpsr()
arm->core_state = state;
armv4_5.c:487arm_set_cpsr()
arm_state_strings[arm->core_state]);
armv4_5.c:797arm_arch_state()
arm_state_strings[arm->core_state],
armv4_5.c:925handle_arm_core_state_command()
arm->core_state = ARM_STATE_ARM;
armv4_5.c:929handle_arm_core_state_command()
arm->core_state = ARM_STATE_THUMB;
armv4_5.c:932handle_arm_core_state_command()
command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
armv4_5.c:1399armv4_5_run_algorithm_inner()
enum arm_state core_state = arm->core_state;
armv4_5.c:1474armv4_5_run_algorithm_inner()
arm->core_state = arm_algorithm_info->core_state;
armv4_5.c:1475armv4_5_run_algorithm_inner()
if (arm->core_state == ARM_STATE_ARM)
armv4_5.c:1477armv4_5_run_algorithm_inner()
else if (arm->core_state == ARM_STATE_THUMB)
armv4_5.c:1569armv4_5_run_algorithm_inner()
arm->core_state = core_state;
armv7m.c:870armv7m_init_arch_info()
arm->core_state = ARM_STATE_THUMB;
armv8.c:961armv8_set_cpsr()
arm->core_state = state;
armv8.c:966armv8_set_cpsr()
armv8_state_strings[arm->core_state]);
armv8.c:1020armv8_show_fault_registers()
if (armv8->arm.core_state != ARM_STATE_AARCH64)
armv8.c:1319armv8_aarch64_state()
armv8_state_strings[arm->core_state],
armv8.c:1343armv8_arch_state()
if (arm->core_state == ARM_STATE_AARCH64)
armv8.c:1955armv8_get_gdb_arch()
return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm";
armv8.c:1965armv8_get_gdb_reg_list()
if (arm->core_state == ARM_STATE_AARCH64) {
armv8_dpm.c:318dpmv8_instr_write_data_r0_64()
if (dpm->arm->core_state != ARM_STATE_AARCH64)
armv8_dpm.c:398dpmv8_instr_read_data_r0_64()
if (dpm->arm->core_state != ARM_STATE_AARCH64) {
armv8_dpm.c:782armv8_dpm_read_current_registers()
if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC)
cortex_a.c:863cortex_a_internal_restore()
switch (arm->core_state) {
cortex_a.c:1208cortex_a_step()
stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB)
feroceon.c:457feroceon_bulk_write_memory()
enum arm_state core_state = arm->core_state;
feroceon.c:526feroceon_bulk_write_memory()
arm->core_state = ARM_STATE_ARM;
feroceon.c:573feroceon_bulk_write_memory()
arm->core_state = core_state;