PLLState
The new state of the PLL. This parameter can be a value of RCC_PLL_Config.
Read more...
PLLSource
RCC_PLLSource: PLL entry clock source. This parameter must be a value of RCC_PLL_Clock_Source.
Read more...
PLLM
PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 0 and Max_Data = 63.
Read more...
PLLN
PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432 except for STM32F411xE devices where the Min_Data = 192.
Read more...
PLLP
PLLP: Division factor for main system clock (SYSCLK). This parameter must be a value of RCC_PLLP_Clock_Divider.
Read more...
PLLQ
PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Read more...
PLLR
PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Read more...