PLLM
Division factor for PLL VCO input clock. This parameter can be a value of RCC_LL_EC_PLLM_DIV This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().
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PLLN
Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data =
RCC_PLLN_MIN_VALUE
and Max_Data =
RCC_PLLN_MIN_VALUE
This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().
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PLLP
Division for the main system clock. This parameter can be a value of RCC_LL_EC_PLLP_DIV This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().
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